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c609719b
WD
1/*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
c609719b
WD
6 */
7
8/*
9 * This provides a bit-banged interface to the ethernet MII management
10 * channel.
11 */
12
13#include <common.h>
c74c8e66 14#include <dm.h>
c609719b 15#include <miiphy.h>
5f184715 16#include <phy.h>
c609719b 17
63ff004c
MB
18#include <asm/types.h>
19#include <linux/list.h>
20#include <malloc.h>
21#include <net.h>
22
23/* local debug macro */
63ff004c
MB
24#undef MII_DEBUG
25
26#undef debug
27#ifdef MII_DEBUG
16a53238 28#define debug(fmt, args...) printf(fmt, ##args)
63ff004c 29#else
16a53238 30#define debug(fmt, args...)
63ff004c
MB
31#endif /* MII_DEBUG */
32
63ff004c
MB
33static struct list_head mii_devs;
34static struct mii_dev *current_mii;
35
0daac978
MF
36/*
37 * Lookup the mii_dev struct by the registered device name.
38 */
5f184715 39struct mii_dev *miiphy_get_dev_by_name(const char *devname)
0daac978
MF
40{
41 struct list_head *entry;
42 struct mii_dev *dev;
43
44 if (!devname) {
45 printf("NULL device name!\n");
46 return NULL;
47 }
48
49 list_for_each(entry, &mii_devs) {
50 dev = list_entry(entry, struct mii_dev, link);
51 if (strcmp(dev->name, devname) == 0)
52 return dev;
53 }
54
0daac978
MF
55 return NULL;
56}
57
d9785c14
MB
58/*****************************************************************************
59 *
60 * Initialize global data. Need to be called before any other miiphy routine.
61 */
5700bb63 62void miiphy_init(void)
d9785c14 63{
16a53238 64 INIT_LIST_HEAD(&mii_devs);
298035df 65 current_mii = NULL;
d9785c14
MB
66}
67
5f184715
AF
68static int legacy_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
69{
70 unsigned short val;
71 int ret;
72 struct legacy_mii_dev *ldev = bus->priv;
73
74 ret = ldev->read(bus->name, addr, reg, &val);
75
76 return ret ? -1 : (int)val;
77}
78
79static int legacy_miiphy_write(struct mii_dev *bus, int addr, int devad,
80 int reg, u16 val)
81{
82 struct legacy_mii_dev *ldev = bus->priv;
83
84 return ldev->write(bus->name, addr, reg, val);
85}
86
63ff004c
MB
87/*****************************************************************************
88 *
89 * Register read and write MII access routines for the device <name>.
1cdabc4b 90 * This API is now deprecated. Please use mdio_alloc and mdio_register, instead.
63ff004c 91 */
5700bb63 92void miiphy_register(const char *name,
16a53238 93 int (*read)(const char *devname, unsigned char addr,
f915c931 94 unsigned char reg, unsigned short *value),
16a53238 95 int (*write)(const char *devname, unsigned char addr,
f915c931 96 unsigned char reg, unsigned short value))
63ff004c 97{
63ff004c 98 struct mii_dev *new_dev;
5f184715 99 struct legacy_mii_dev *ldev;
07c07635
LW
100
101 BUG_ON(strlen(name) >= MDIO_NAME_LEN);
63ff004c 102
63ff004c 103 /* check if we have unique name */
5f184715 104 new_dev = miiphy_get_dev_by_name(name);
0daac978
MF
105 if (new_dev) {
106 printf("miiphy_register: non unique device name '%s'\n", name);
107 return;
63ff004c
MB
108 }
109
110 /* allocate memory */
5f184715
AF
111 new_dev = mdio_alloc();
112 ldev = malloc(sizeof(*ldev));
63ff004c 113
5f184715 114 if (new_dev == NULL || ldev == NULL) {
16a53238 115 printf("miiphy_register: cannot allocate memory for '%s'\n",
298035df 116 name);
746da1bd
PF
117 free(ldev);
118 mdio_free(new_dev);
63ff004c
MB
119 return;
120 }
63ff004c
MB
121
122 /* initalize mii_dev struct fields */
5f184715
AF
123 new_dev->read = legacy_miiphy_read;
124 new_dev->write = legacy_miiphy_write;
07c07635
LW
125 strncpy(new_dev->name, name, MDIO_NAME_LEN);
126 new_dev->name[MDIO_NAME_LEN - 1] = 0;
5f184715
AF
127 ldev->read = read;
128 ldev->write = write;
129 new_dev->priv = ldev;
63ff004c 130
16a53238 131 debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
5f184715 132 new_dev->name, ldev->read, ldev->write);
63ff004c
MB
133
134 /* add it to the list */
16a53238 135 list_add_tail(&new_dev->link, &mii_devs);
63ff004c
MB
136
137 if (!current_mii)
138 current_mii = new_dev;
139}
140
5f184715
AF
141struct mii_dev *mdio_alloc(void)
142{
143 struct mii_dev *bus;
144
145 bus = malloc(sizeof(*bus));
146 if (!bus)
147 return bus;
148
149 memset(bus, 0, sizeof(*bus));
150
151 /* initalize mii_dev struct fields */
152 INIT_LIST_HEAD(&bus->link);
153
154 return bus;
155}
156
cb6baca7
BM
157void mdio_free(struct mii_dev *bus)
158{
159 free(bus);
160}
161
5f184715
AF
162int mdio_register(struct mii_dev *bus)
163{
d39449b1 164 if (!bus || !bus->read || !bus->write)
5f184715
AF
165 return -1;
166
167 /* check if we have unique name */
168 if (miiphy_get_dev_by_name(bus->name)) {
169 printf("mdio_register: non unique device name '%s'\n",
170 bus->name);
171 return -1;
172 }
173
174 /* add it to the list */
175 list_add_tail(&bus->link, &mii_devs);
176
177 if (!current_mii)
178 current_mii = bus;
179
180 return 0;
181}
182
cb6baca7
BM
183int mdio_unregister(struct mii_dev *bus)
184{
185 if (!bus)
186 return 0;
187
188 /* delete it from the list */
189 list_del(&bus->link);
190
191 if (current_mii == bus)
192 current_mii = NULL;
193
194 return 0;
195}
196
5f184715
AF
197void mdio_list_devices(void)
198{
199 struct list_head *entry;
200
201 list_for_each(entry, &mii_devs) {
202 int i;
203 struct mii_dev *bus = list_entry(entry, struct mii_dev, link);
204
205 printf("%s:\n", bus->name);
206
207 for (i = 0; i < PHY_MAX_ADDR; i++) {
208 struct phy_device *phydev = bus->phymap[i];
209
210 if (phydev) {
211 printf("%d - %s", i, phydev->drv->name);
212
213 if (phydev->dev)
214 printf(" <--> %s\n", phydev->dev->name);
215 else
216 printf("\n");
217 }
218 }
219 }
220}
221
5700bb63 222int miiphy_set_current_dev(const char *devname)
63ff004c 223{
63ff004c
MB
224 struct mii_dev *dev;
225
5f184715 226 dev = miiphy_get_dev_by_name(devname);
0daac978
MF
227 if (dev) {
228 current_mii = dev;
229 return 0;
63ff004c
MB
230 }
231
5f184715
AF
232 printf("No such device: %s\n", devname);
233
63ff004c
MB
234 return 1;
235}
236
5f184715
AF
237struct mii_dev *mdio_get_current_dev(void)
238{
239 return current_mii;
240}
241
242struct phy_device *mdio_phydev_for_ethname(const char *ethname)
243{
244 struct list_head *entry;
245 struct mii_dev *bus;
246
247 list_for_each(entry, &mii_devs) {
248 int i;
249 bus = list_entry(entry, struct mii_dev, link);
250
251 for (i = 0; i < PHY_MAX_ADDR; i++) {
252 if (!bus->phymap[i] || !bus->phymap[i]->dev)
253 continue;
254
255 if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
256 return bus->phymap[i];
257 }
258 }
259
260 printf("%s is not a known ethernet\n", ethname);
261 return NULL;
262}
263
5700bb63 264const char *miiphy_get_current_dev(void)
63ff004c
MB
265{
266 if (current_mii)
267 return current_mii->name;
268
269 return NULL;
270}
271
ede16ea3
MF
272static struct mii_dev *miiphy_get_active_dev(const char *devname)
273{
274 /* If the current mii is the one we want, return it */
275 if (current_mii)
276 if (strcmp(current_mii->name, devname) == 0)
277 return current_mii;
278
279 /* Otherwise, set the active one to the one we want */
280 if (miiphy_set_current_dev(devname))
281 return NULL;
282 else
283 return current_mii;
284}
285
63ff004c
MB
286/*****************************************************************************
287 *
288 * Read to variable <value> from the PHY attached to device <devname>,
289 * use PHY address <addr> and register <reg>.
290 *
1cdabc4b
AF
291 * This API is deprecated. Use phy_read on a phy_device found via phy_connect
292 *
63ff004c
MB
293 * Returns:
294 * 0 on success
295 */
f915c931 296int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
298035df 297 unsigned short *value)
63ff004c 298{
5f184715 299 struct mii_dev *bus;
d67d5d52 300 int ret;
63ff004c 301
5f184715 302 bus = miiphy_get_active_dev(devname);
d67d5d52 303 if (!bus)
5f184715 304 return 1;
63ff004c 305
d67d5d52
AG
306 ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
307 if (ret < 0)
308 return 1;
309
310 *value = (unsigned short)ret;
311 return 0;
63ff004c
MB
312}
313
314/*****************************************************************************
315 *
316 * Write <value> to the PHY attached to device <devname>,
317 * use PHY address <addr> and register <reg>.
318 *
1cdabc4b
AF
319 * This API is deprecated. Use phy_write on a phy_device found by phy_connect
320 *
63ff004c
MB
321 * Returns:
322 * 0 on success
323 */
f915c931 324int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
298035df 325 unsigned short value)
63ff004c 326{
5f184715 327 struct mii_dev *bus;
63ff004c 328
5f184715
AF
329 bus = miiphy_get_active_dev(devname);
330 if (bus)
331 return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);
63ff004c 332
0daac978 333 return 1;
63ff004c
MB
334}
335
336/*****************************************************************************
337 *
338 * Print out list of registered MII capable devices.
339 */
16a53238 340void miiphy_listdev(void)
63ff004c
MB
341{
342 struct list_head *entry;
343 struct mii_dev *dev;
344
16a53238
AF
345 puts("MII devices: ");
346 list_for_each(entry, &mii_devs) {
347 dev = list_entry(entry, struct mii_dev, link);
348 printf("'%s' ", dev->name);
63ff004c 349 }
16a53238 350 puts("\n");
63ff004c
MB
351
352 if (current_mii)
16a53238 353 printf("Current device: '%s'\n", current_mii->name);
63ff004c
MB
354}
355
c609719b
WD
356/*****************************************************************************
357 *
358 * Read the OUI, manufacture's model number, and revision number.
359 *
360 * OUI: 22 bits (unsigned int)
361 * Model: 6 bits (unsigned char)
362 * Revision: 4 bits (unsigned char)
363 *
1cdabc4b
AF
364 * This API is deprecated.
365 *
c609719b
WD
366 * Returns:
367 * 0 on success
368 */
5700bb63 369int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
c609719b
WD
370 unsigned char *model, unsigned char *rev)
371{
372 unsigned int reg = 0;
8bf3b005 373 unsigned short tmp;
c609719b 374
16a53238
AF
375 if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
376 debug("PHY ID register 2 read failed\n");
377 return -1;
c609719b 378 }
8bf3b005 379 reg = tmp;
c609719b 380
16a53238 381 debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);
26c7bab8 382
c609719b
WD
383 if (reg == 0xFFFF) {
384 /* No physical device present at this address */
16a53238 385 return -1;
c609719b
WD
386 }
387
16a53238
AF
388 if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
389 debug("PHY ID register 1 read failed\n");
390 return -1;
c609719b 391 }
8bf3b005 392 reg |= tmp << 16;
16a53238 393 debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
26c7bab8 394
298035df
LJ
395 *oui = (reg >> 10);
396 *model = (unsigned char)((reg >> 4) & 0x0000003F);
397 *rev = (unsigned char)(reg & 0x0000000F);
16a53238 398 return 0;
c609719b
WD
399}
400
5f184715 401#ifndef CONFIG_PHYLIB
c609719b
WD
402/*****************************************************************************
403 *
404 * Reset the PHY.
1cdabc4b
AF
405 *
406 * This API is deprecated. Use PHYLIB.
407 *
c609719b
WD
408 * Returns:
409 * 0 on success
410 */
5700bb63 411int miiphy_reset(const char *devname, unsigned char addr)
c609719b
WD
412{
413 unsigned short reg;
ab5a0dcb 414 int timeout = 500;
c609719b 415
16a53238
AF
416 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
417 debug("PHY status read failed\n");
418 return -1;
f89920c3 419 }
16a53238
AF
420 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
421 debug("PHY reset failed\n");
422 return -1;
c609719b 423 }
5653fc33 424#ifdef CONFIG_PHY_RESET_DELAY
16a53238 425 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
5653fc33 426#endif
c609719b
WD
427 /*
428 * Poll the control register for the reset bit to go to 0 (it is
429 * auto-clearing). This should happen within 0.5 seconds per the
430 * IEEE spec.
431 */
c609719b 432 reg = 0x8000;
ab5a0dcb 433 while (((reg & 0x8000) != 0) && timeout--) {
8ef583a0 434 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
ab5a0dcb
SR
435 debug("PHY status read failed\n");
436 return -1;
c609719b 437 }
ab5a0dcb 438 udelay(1000);
c609719b
WD
439 }
440 if ((reg & 0x8000) == 0) {
16a53238 441 return 0;
c609719b 442 } else {
16a53238
AF
443 puts("PHY reset timed out\n");
444 return -1;
c609719b 445 }
16a53238 446 return 0;
c609719b 447}
5f184715 448#endif /* !PHYLIB */
c609719b 449
c609719b
WD
450/*****************************************************************************
451 *
71bc6e64 452 * Determine the ethernet speed (10/100/1000). Return 10 on error.
c609719b 453 */
5700bb63 454int miiphy_speed(const char *devname, unsigned char addr)
c609719b 455{
71bc6e64 456 u16 bmcr, anlpar;
c609719b 457
6fb6af6d 458#if defined(CONFIG_PHY_GIGE)
71bc6e64
LJ
459 u16 btsr;
460
461 /*
462 * Check for 1000BASE-X. If it is supported, then assume that the speed
463 * is 1000.
464 */
16a53238 465 if (miiphy_is_1000base_x(devname, addr))
71bc6e64 466 return _1000BASET;
16a53238 467
71bc6e64
LJ
468 /*
469 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
470 */
471 /* Check for 1000BASE-T. */
16a53238
AF
472 if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
473 printf("PHY 1000BT status");
71bc6e64
LJ
474 goto miiphy_read_failed;
475 }
476 if (btsr != 0xFFFF &&
16a53238 477 (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
71bc6e64 478 return _1000BASET;
6fb6af6d 479#endif /* CONFIG_PHY_GIGE */
855a496f 480
a56bd922 481 /* Check Basic Management Control Register first. */
16a53238
AF
482 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
483 printf("PHY speed");
71bc6e64 484 goto miiphy_read_failed;
c609719b 485 }
a56bd922 486 /* Check if auto-negotiation is on. */
8ef583a0 487 if (bmcr & BMCR_ANENABLE) {
a56bd922 488 /* Get auto-negotiation results. */
16a53238
AF
489 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
490 printf("PHY AN speed");
71bc6e64 491 goto miiphy_read_failed;
a56bd922 492 }
8ef583a0 493 return (anlpar & LPA_100) ? _100BASET : _10BASET;
a56bd922
WD
494 }
495 /* Get speed from basic control settings. */
8ef583a0 496 return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
a56bd922 497
5f841959 498miiphy_read_failed:
16a53238 499 printf(" read failed, assuming 10BASE-T\n");
71bc6e64 500 return _10BASET;
c609719b
WD
501}
502
c609719b
WD
503/*****************************************************************************
504 *
71bc6e64 505 * Determine full/half duplex. Return half on error.
c609719b 506 */
5700bb63 507int miiphy_duplex(const char *devname, unsigned char addr)
c609719b 508{
71bc6e64 509 u16 bmcr, anlpar;
c609719b 510
6fb6af6d 511#if defined(CONFIG_PHY_GIGE)
71bc6e64
LJ
512 u16 btsr;
513
514 /* Check for 1000BASE-X. */
16a53238 515 if (miiphy_is_1000base_x(devname, addr)) {
71bc6e64 516 /* 1000BASE-X */
16a53238
AF
517 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
518 printf("1000BASE-X PHY AN duplex");
71bc6e64
LJ
519 goto miiphy_read_failed;
520 }
521 }
522 /*
523 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
524 */
525 /* Check for 1000BASE-T. */
16a53238
AF
526 if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
527 printf("PHY 1000BT status");
71bc6e64
LJ
528 goto miiphy_read_failed;
529 }
530 if (btsr != 0xFFFF) {
531 if (btsr & PHY_1000BTSR_1000FD) {
532 return FULL;
533 } else if (btsr & PHY_1000BTSR_1000HD) {
534 return HALF;
855a496f
WD
535 }
536 }
6fb6af6d 537#endif /* CONFIG_PHY_GIGE */
855a496f 538
a56bd922 539 /* Check Basic Management Control Register first. */
16a53238
AF
540 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
541 puts("PHY duplex");
71bc6e64 542 goto miiphy_read_failed;
c609719b 543 }
a56bd922 544 /* Check if auto-negotiation is on. */
8ef583a0 545 if (bmcr & BMCR_ANENABLE) {
a56bd922 546 /* Get auto-negotiation results. */
16a53238
AF
547 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
548 puts("PHY AN duplex");
71bc6e64 549 goto miiphy_read_failed;
a56bd922 550 }
8ef583a0 551 return (anlpar & (LPA_10FULL | LPA_100FULL)) ?
71bc6e64 552 FULL : HALF;
a56bd922
WD
553 }
554 /* Get speed from basic control settings. */
8ef583a0 555 return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;
71bc6e64 556
5f841959 557miiphy_read_failed:
16a53238 558 printf(" read failed, assuming half duplex\n");
71bc6e64
LJ
559 return HALF;
560}
a56bd922 561
71bc6e64
LJ
562/*****************************************************************************
563 *
564 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
565 * 1000BASE-T, or on error.
566 */
5700bb63 567int miiphy_is_1000base_x(const char *devname, unsigned char addr)
71bc6e64
LJ
568{
569#if defined(CONFIG_PHY_GIGE)
570 u16 exsr;
571
16a53238
AF
572 if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
573 printf("PHY extended status read failed, assuming no "
71bc6e64
LJ
574 "1000BASE-X\n");
575 return 0;
576 }
8ef583a0 577 return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH));
71bc6e64
LJ
578#else
579 return 0;
580#endif
c609719b
WD
581}
582
6d0f6bcf 583#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
fc3e2165
WD
584/*****************************************************************************
585 *
586 * Determine link status
587 */
5700bb63 588int miiphy_link(const char *devname, unsigned char addr)
fc3e2165
WD
589{
590 unsigned short reg;
591
a3d991bd 592 /* dummy read; needed to latch some phys */
16a53238
AF
593 (void)miiphy_read(devname, addr, MII_BMSR, &reg);
594 if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
595 puts("MII_BMSR read failed, assuming no link\n");
596 return 0;
fc3e2165
WD
597 }
598
599 /* Determine if a link is active */
8ef583a0 600 if ((reg & BMSR_LSTATUS) != 0) {
16a53238 601 return 1;
fc3e2165 602 } else {
16a53238 603 return 0;
fc3e2165
WD
604 }
605}
606#endif