[people/ms/u-boot.git] / common / miiphyutil.c

/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This provides a bit-banged interface to the ethernet MII management
 * channel.
 */

#include <common.h>
#include <dm.h>
#include <miiphy.h>
#include <phy.h>

#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>

/* local debug macro */
#undef MII_DEBUG

#undef debug
#ifdef MII_DEBUG
#define debug(fmt, args...)	printf(fmt, ##args)
#else
#define debug(fmt, args...)
#endif /* MII_DEBUG */

static struct list_head mii_devs;
static struct mii_dev *current_mii;

/*
 * Lookup the mii_dev struct by the registered device name.
 */
struct mii_dev *miiphy_get_dev_by_name(const char *devname)
{
	struct list_head *entry;
	struct mii_dev *dev;

	if (!devname) {
		printf("NULL device name!\n");
		return NULL;
	}

	list_for_each(entry, &mii_devs) {
		dev = list_entry(entry, struct mii_dev, link);
		if (strcmp(dev->name, devname) == 0)
			return dev;
	}

	return NULL;
}

/*****************************************************************************
 *
 * Initialize global data. Need to be called before any other miiphy routine.
 */
void miiphy_init(void)
{
	INIT_LIST_HEAD(&mii_devs);
	current_mii = NULL;
}

struct mii_dev *mdio_alloc(void)
{
	struct mii_dev *bus;

	bus = malloc(sizeof(*bus));
	if (!bus)
		return bus;

	memset(bus, 0, sizeof(*bus));

	/* initalize mii_dev struct fields */
	INIT_LIST_HEAD(&bus->link);

	return bus;
}

void mdio_free(struct mii_dev *bus)
{
	free(bus);
}

int mdio_register(struct mii_dev *bus)
{
	if (!bus || !bus->read || !bus->write)
		return -1;

	/* check if we have unique name */
	if (miiphy_get_dev_by_name(bus->name)) {
		printf("mdio_register: non unique device name '%s'\n",
			bus->name);
		return -1;
	}

	/* add it to the list */
	list_add_tail(&bus->link, &mii_devs);

	if (!current_mii)
		current_mii = bus;

	return 0;
}

int mdio_register_seq(struct mii_dev *bus, int seq)
{
	int ret;

	/* Setup a unique name for each mdio bus */
	ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
	if (ret < 0)
		return ret;

	return mdio_register(bus);
}

int mdio_unregister(struct mii_dev *bus)
{
	if (!bus)
		return 0;

	/* delete it from the list */
	list_del(&bus->link);

	if (current_mii == bus)
		current_mii = NULL;

	return 0;
}

void mdio_list_devices(void)
{
	struct list_head *entry;

	list_for_each(entry, &mii_devs) {
		int i;
		struct mii_dev *bus = list_entry(entry, struct mii_dev, link);

		printf("%s:\n", bus->name);

		for (i = 0; i < PHY_MAX_ADDR; i++) {
			struct phy_device *phydev = bus->phymap[i];

			if (phydev) {
				printf("%x - %s", i, phydev->drv->name);

				if (phydev->dev)
					printf(" <--> %s\n", phydev->dev->name);
				else
					printf("\n");
			}
		}
	}
}

int miiphy_set_current_dev(const char *devname)
{
	struct mii_dev *dev;

	dev = miiphy_get_dev_by_name(devname);
	if (dev) {
		current_mii = dev;
		return 0;
	}

	printf("No such device: %s\n", devname);

	return 1;
}

struct mii_dev *mdio_get_current_dev(void)
{
	return current_mii;
}

struct phy_device *mdio_phydev_for_ethname(const char *ethname)
{
	struct list_head *entry;
	struct mii_dev *bus;

	list_for_each(entry, &mii_devs) {
		int i;
		bus = list_entry(entry, struct mii_dev, link);

		for (i = 0; i < PHY_MAX_ADDR; i++) {
			if (!bus->phymap[i] || !bus->phymap[i]->dev)
				continue;

			if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
				return bus->phymap[i];
		}
	}

	printf("%s is not a known ethernet\n", ethname);
	return NULL;
}

const char *miiphy_get_current_dev(void)
{
	if (current_mii)
		return current_mii->name;

	return NULL;
}

static struct mii_dev *miiphy_get_active_dev(const char *devname)
{
	/* If the current mii is the one we want, return it */
	if (current_mii)
		if (strcmp(current_mii->name, devname) == 0)
			return current_mii;

	/* Otherwise, set the active one to the one we want */
	if (miiphy_set_current_dev(devname))
		return NULL;
	else
		return current_mii;
}

/*****************************************************************************
 *
 * Read to variable <value> from the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * This API is deprecated. Use phy_read on a phy_device found via phy_connect
 *
 * Returns:
 *   0 on success
 */
int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
		 unsigned short *value)
{
	struct mii_dev *bus;
	int ret;

	bus = miiphy_get_active_dev(devname);
	if (!bus)
		return 1;

	ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
	if (ret < 0)
		return 1;

	*value = (unsigned short)ret;
	return 0;
}

/*****************************************************************************
 *
 * Write <value> to the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * This API is deprecated. Use phy_write on a phy_device found by phy_connect
 *
 * Returns:
 *   0 on success
 */
int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
		  unsigned short value)
{
	struct mii_dev *bus;

	bus = miiphy_get_active_dev(devname);
	if (bus)
		return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);

	return 1;
}

/*****************************************************************************
 *
 * Print out list of registered MII capable devices.
 */
void miiphy_listdev(void)
{
	struct list_head *entry;
	struct mii_dev *dev;

	puts("MII devices: ");
	list_for_each(entry, &mii_devs) {
		dev = list_entry(entry, struct mii_dev, link);
		printf("'%s' ", dev->name);
	}
	puts("\n");

	if (current_mii)
		printf("Current device: '%s'\n", current_mii->name);
}

/*****************************************************************************
 *
 * Read the OUI, manufacture's model number, and revision number.
 *
 * OUI:     22 bits (unsigned int)
 * Model:    6 bits (unsigned char)
 * Revision: 4 bits (unsigned char)
 *
 * This API is deprecated.
 *
 * Returns:
 *   0 on success
 */
int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
		 unsigned char *model, unsigned char *rev)
{
	unsigned int reg = 0;
	unsigned short tmp;

	if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
		debug("PHY ID register 2 read failed\n");
		return -1;
	}
	reg = tmp;

	debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);

	if (reg == 0xFFFF) {
		/* No physical device present at this address */
		return -1;
	}

	if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
		debug("PHY ID register 1 read failed\n");
		return -1;
	}
	reg |= tmp << 16;
	debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);

	*oui = (reg >> 10);
	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	*rev = (unsigned char)(reg & 0x0000000F);
	return 0;
}

#ifndef CONFIG_PHYLIB
/*****************************************************************************
 *
 * Reset the PHY.
 *
 * This API is deprecated. Use PHYLIB.
 *
 * Returns:
 *   0 on success
 */
int miiphy_reset(const char *devname, unsigned char addr)
{
	unsigned short reg;
	int timeout = 500;

	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
		debug("PHY status read failed\n");
		return -1;
	}
	if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
		debug("PHY reset failed\n");
		return -1;
	}
#ifdef CONFIG_PHY_RESET_DELAY
	udelay(CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
#endif
	/*
	 * Poll the control register for the reset bit to go to 0 (it is
	 * auto-clearing).  This should happen within 0.5 seconds per the
	 * IEEE spec.
	 */
	reg = 0x8000;
	while (((reg & 0x8000) != 0) && timeout--) {
		if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
			debug("PHY status read failed\n");
			return -1;
		}
		udelay(1000);
	}
	if ((reg & 0x8000) == 0) {
		return 0;
	} else {
		puts("PHY reset timed out\n");
		return -1;
	}
	return 0;
}
#endif /* !PHYLIB */

/*****************************************************************************
 *
 * Determine the ethernet speed (10/100/1000).  Return 10 on error.
 */
int miiphy_speed(const char *devname, unsigned char addr)
{
	u16 bmcr, anlpar, adv;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/*
	 * Check for 1000BASE-X.  If it is supported, then assume that the speed
	 * is 1000.
	 */
	if (miiphy_is_1000base_x(devname, addr))
		return _1000BASET;

	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
		printf("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF &&
			(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
		return _1000BASET;
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
		printf("PHY speed");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & BMCR_ANENABLE) {
		/* Get auto-negotiation results. */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			printf("PHY AN speed");
			goto miiphy_read_failed;
		}

		if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
			puts("PHY AN adv speed");
			goto miiphy_read_failed;
		}
		return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
	}
	/* Get speed from basic control settings. */
	return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;

miiphy_read_failed:
	printf(" read failed, assuming 10BASE-T\n");
	return _10BASET;
}

/*****************************************************************************
 *
 * Determine full/half duplex.  Return half on error.
 */
int miiphy_duplex(const char *devname, unsigned char addr)
{
	u16 bmcr, anlpar, adv;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/* Check for 1000BASE-X. */
	if (miiphy_is_1000base_x(devname, addr)) {
		/* 1000BASE-X */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			printf("1000BASE-X PHY AN duplex");
			goto miiphy_read_failed;
		}
	}
	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
		printf("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF) {
		if (btsr & PHY_1000BTSR_1000FD) {
			return FULL;
		} else if (btsr & PHY_1000BTSR_1000HD) {
			return HALF;
		}
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
		puts("PHY duplex");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & BMCR_ANENABLE) {
		/* Get auto-negotiation results. */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			puts("PHY AN duplex");
			goto miiphy_read_failed;
		}

		if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
			puts("PHY AN adv duplex");
			goto miiphy_read_failed;
		}
		return ((anlpar & adv) & (LPA_10FULL | LPA_100FULL)) ?
		    FULL : HALF;
	}
	/* Get speed from basic control settings. */
	return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;

miiphy_read_failed:
	printf(" read failed, assuming half duplex\n");
	return HALF;
}

/*****************************************************************************
 *
 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
 * 1000BASE-T, or on error.
 */
int miiphy_is_1000base_x(const char *devname, unsigned char addr)
{
#if defined(CONFIG_PHY_GIGE)
	u16 exsr;

	if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
		printf("PHY extended status read failed, assuming no "
			"1000BASE-X\n");
		return 0;
	}
	return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH));
#else
	return 0;
#endif
}

#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*****************************************************************************
 *
 * Determine link status
 */
int miiphy_link(const char *devname, unsigned char addr)
{
	unsigned short reg;

	/* dummy read; needed to latch some phys */
	(void)miiphy_read(devname, addr, MII_BMSR, &reg);
	if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
		puts("MII_BMSR read failed, assuming no link\n");
		return 0;
	}

	/* Determine if a link is active */
	if ((reg & BMSR_LSTATUS) != 0) {
		return 1;
	} else {
		return 0;
	}
}
#endif
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* This provides a bit-banged interface to the ethernet MII management
	10	* channel.
	11	*/
	12
	13	#include <common.h>
c74c8e66	14	#include <dm.h>
c609719b	15	#include <miiphy.h>
5f184715	16	#include <phy.h>
c609719b	17
63ff004c MB	18	#include <asm/types.h>
	19	#include <linux/list.h>
	20	#include <malloc.h>
	21	#include <net.h>
	22
	23	/* local debug macro */
63ff004c MB	24	#undef MII_DEBUG
	25
	26	#undef debug
	27	#ifdef MII_DEBUG
16a53238	28	#define debug(fmt, args...) printf(fmt, ##args)
63ff004c	29	#else
16a53238	30	#define debug(fmt, args...)
63ff004c MB	31	#endif /* MII_DEBUG */
63ff004c MB	32
63ff004c MB	33	static struct list_head mii_devs;
	34	static struct mii_dev *current_mii;
	35
0daac978 MF	36	/*
	37	* Lookup the mii_dev struct by the registered device name.
	38	*/
5f184715	39	struct mii_dev miiphy_get_dev_by_name(const char devname)
0daac978 MF	40	{
	41	struct list_head *entry;
	42	struct mii_dev *dev;
	43
	44	if (!devname) {
	45	printf("NULL device name!\n");
	46	return NULL;
	47	}
	48
	49	list_for_each(entry, &mii_devs) {
	50	dev = list_entry(entry, struct mii_dev, link);
	51	if (strcmp(dev->name, devname) == 0)
	52	return dev;
	53	}
	54
0daac978 MF	55	return NULL;
	56	}
	57
d9785c14 MB	58	/*****************************************************************************
	59	*
	60	* Initialize global data. Need to be called before any other miiphy routine.
	61	*/
5700bb63	62	void miiphy_init(void)
d9785c14	63	{
16a53238	64	INIT_LIST_HEAD(&mii_devs);
298035df	65	current_mii = NULL;
d9785c14 MB	66	}
d9785c14 MB	67
5f184715 AF	68	struct mii_dev *mdio_alloc(void)
	69	{
	70	struct mii_dev *bus;
	71
	72	bus = malloc(sizeof(*bus));
	73	if (!bus)
	74	return bus;
	75
	76	memset(bus, 0, sizeof(*bus));
	77
	78	/* initalize mii_dev struct fields */
	79	INIT_LIST_HEAD(&bus->link);
	80
	81	return bus;
	82	}
	83
cb6baca7 BM	84	void mdio_free(struct mii_dev *bus)
	85	{
	86	free(bus);
	87	}
	88
5f184715 AF	89	int mdio_register(struct mii_dev *bus)
5f184715 AF	90	{
d39449b1	91	if (!bus \|\| !bus->read \|\| !bus->write)
5f184715 AF	92	return -1;
	93
	94	/* check if we have unique name */
	95	if (miiphy_get_dev_by_name(bus->name)) {
	96	printf("mdio_register: non unique device name '%s'\n",
	97	bus->name);
	98	return -1;
	99	}
	100
	101	/* add it to the list */
	102	list_add_tail(&bus->link, &mii_devs);
	103
	104	if (!current_mii)
	105	current_mii = bus;
	106
	107	return 0;
	108	}
	109
79e2a6a0 MS	110	int mdio_register_seq(struct mii_dev *bus, int seq)
	111	{
	112	int ret;
	113
	114	/* Setup a unique name for each mdio bus */
	115	ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
	116	if (ret < 0)
	117	return ret;
	118
	119	return mdio_register(bus);
	120	}
	121
cb6baca7 BM	122	int mdio_unregister(struct mii_dev *bus)
	123	{
	124	if (!bus)
	125	return 0;
	126
	127	/* delete it from the list */
	128	list_del(&bus->link);
	129
	130	if (current_mii == bus)
	131	current_mii = NULL;
	132
	133	return 0;
	134	}
	135
5f184715 AF	136	void mdio_list_devices(void)
	137	{
	138	struct list_head *entry;
	139
	140	list_for_each(entry, &mii_devs) {
	141	int i;
	142	struct mii_dev *bus = list_entry(entry, struct mii_dev, link);
	143
	144	printf("%s:\n", bus->name);
	145
	146	for (i = 0; i < PHY_MAX_ADDR; i++) {
	147	struct phy_device *phydev = bus->phymap[i];
	148
	149	if (phydev) {
15a2acdf	150	printf("%x - %s", i, phydev->drv->name);
5f184715 AF	151
	152	if (phydev->dev)
	153	printf(" <--> %s\n", phydev->dev->name);
	154	else
	155	printf("\n");
	156	}
	157	}
	158	}
	159	}
	160
5700bb63	161	int miiphy_set_current_dev(const char *devname)
63ff004c	162	{
63ff004c MB	163	struct mii_dev *dev;
63ff004c MB	164
5f184715	165	dev = miiphy_get_dev_by_name(devname);
0daac978 MF	166	if (dev) {
	167	current_mii = dev;
	168	return 0;
63ff004c MB	169	}
63ff004c MB	170
5f184715 AF	171	printf("No such device: %s\n", devname);
5f184715 AF	172
63ff004c MB	173	return 1;
	174	}
	175
5f184715 AF	176	struct mii_dev *mdio_get_current_dev(void)
	177	{
	178	return current_mii;
	179	}
	180
	181	struct phy_device mdio_phydev_for_ethname(const char ethname)
	182	{
	183	struct list_head *entry;
	184	struct mii_dev *bus;
	185
	186	list_for_each(entry, &mii_devs) {
	187	int i;
	188	bus = list_entry(entry, struct mii_dev, link);
	189
	190	for (i = 0; i < PHY_MAX_ADDR; i++) {
	191	if (!bus->phymap[i] \|\| !bus->phymap[i]->dev)
	192	continue;
	193
	194	if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
	195	return bus->phymap[i];
	196	}
	197	}
	198
	199	printf("%s is not a known ethernet\n", ethname);
	200	return NULL;
	201	}
	202
5700bb63	203	const char *miiphy_get_current_dev(void)
63ff004c MB	204	{
	205	if (current_mii)
	206	return current_mii->name;
	207
	208	return NULL;
	209	}
	210
ede16ea3 MF	211	static struct mii_dev miiphy_get_active_dev(const char devname)
	212	{
	213	/* If the current mii is the one we want, return it */
	214	if (current_mii)
	215	if (strcmp(current_mii->name, devname) == 0)
	216	return current_mii;
	217
	218	/* Otherwise, set the active one to the one we want */
	219	if (miiphy_set_current_dev(devname))
	220	return NULL;
	221	else
	222	return current_mii;
	223	}
	224
63ff004c MB	225	/*****************************************************************************
	226	*
	227	* Read to variable <value> from the PHY attached to device <devname>,
	228	* use PHY address <addr> and register <reg>.
	229	*
1cdabc4b AF	230	* This API is deprecated. Use phy_read on a phy_device found via phy_connect
1cdabc4b AF	231	*
63ff004c MB	232	* Returns:
	233	* 0 on success
	234	*/
f915c931	235	int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
298035df	236	unsigned short *value)
63ff004c	237	{
5f184715	238	struct mii_dev *bus;
d67d5d52	239	int ret;
63ff004c	240
5f184715	241	bus = miiphy_get_active_dev(devname);
d67d5d52	242	if (!bus)
5f184715	243	return 1;
63ff004c	244
d67d5d52 AG	245	ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
	246	if (ret < 0)
	247	return 1;
	248
	249	*value = (unsigned short)ret;
	250	return 0;
63ff004c MB	251	}
	252
	253	/*****************************************************************************
	254	*
	255	* Write <value> to the PHY attached to device <devname>,
	256	* use PHY address <addr> and register <reg>.
	257	*
1cdabc4b AF	258	* This API is deprecated. Use phy_write on a phy_device found by phy_connect
1cdabc4b AF	259	*
63ff004c MB	260	* Returns:
	261	* 0 on success
	262	*/
f915c931	263	int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
298035df	264	unsigned short value)
63ff004c	265	{
5f184715	266	struct mii_dev *bus;
63ff004c	267
5f184715 AF	268	bus = miiphy_get_active_dev(devname);
	269	if (bus)
	270	return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);
63ff004c	271
0daac978	272	return 1;
63ff004c MB	273	}
	274
	275	/*****************************************************************************
	276	*
	277	* Print out list of registered MII capable devices.
	278	*/
16a53238	279	void miiphy_listdev(void)
63ff004c MB	280	{
	281	struct list_head *entry;
	282	struct mii_dev *dev;
	283
16a53238 AF	284	puts("MII devices: ");
	285	list_for_each(entry, &mii_devs) {
	286	dev = list_entry(entry, struct mii_dev, link);
	287	printf("'%s' ", dev->name);
63ff004c	288	}
16a53238	289	puts("\n");
63ff004c MB	290
63ff004c MB	291	if (current_mii)
16a53238	292	printf("Current device: '%s'\n", current_mii->name);
63ff004c MB	293	}
63ff004c MB	294
c609719b WD	295	/*****************************************************************************
	296	*
	297	* Read the OUI, manufacture's model number, and revision number.
	298	*
	299	* OUI: 22 bits (unsigned int)
	300	* Model: 6 bits (unsigned char)
	301	* Revision: 4 bits (unsigned char)
	302	*
1cdabc4b AF	303	* This API is deprecated.
1cdabc4b AF	304	*
c609719b WD	305	* Returns:
	306	* 0 on success
	307	*/
5700bb63	308	int miiphy_info(const char devname, unsigned char addr, unsigned int oui,
c609719b WD	309	unsigned char model, unsigned char rev)
	310	{
	311	unsigned int reg = 0;
8bf3b005	312	unsigned short tmp;
c609719b	313
16a53238 AF	314	if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
	315	debug("PHY ID register 2 read failed\n");
	316	return -1;
c609719b	317	}
8bf3b005	318	reg = tmp;
c609719b	319
16a53238	320	debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);
26c7bab8	321
c609719b WD	322	if (reg == 0xFFFF) {
c609719b WD	323	/* No physical device present at this address */
16a53238	324	return -1;
c609719b WD	325	}
c609719b WD	326
16a53238 AF	327	if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
	328	debug("PHY ID register 1 read failed\n");
	329	return -1;
c609719b	330	}
8bf3b005	331	reg \|= tmp << 16;
16a53238	332	debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
26c7bab8	333
298035df LJ	334	*oui = (reg >> 10);
	335	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	336	*rev = (unsigned char)(reg & 0x0000000F);
16a53238	337	return 0;
c609719b WD	338	}
c609719b WD	339
5f184715	340	#ifndef CONFIG_PHYLIB
c609719b WD	341	/*****************************************************************************
	342	*
	343	* Reset the PHY.
1cdabc4b AF	344	*
	345	* This API is deprecated. Use PHYLIB.
	346	*
c609719b WD	347	* Returns:
	348	* 0 on success
	349	*/
5700bb63	350	int miiphy_reset(const char *devname, unsigned char addr)
c609719b WD	351	{
c609719b WD	352	unsigned short reg;
ab5a0dcb	353	int timeout = 500;
c609719b	354
16a53238 AF	355	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
	356	debug("PHY status read failed\n");
	357	return -1;
f89920c3	358	}
16a53238 AF	359	if (miiphy_write(devname, addr, MII_BMCR, reg \| BMCR_RESET) != 0) {
	360	debug("PHY reset failed\n");
	361	return -1;
c609719b	362	}
5653fc33	363	#ifdef CONFIG_PHY_RESET_DELAY
16a53238	364	udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
5653fc33	365	#endif
c609719b WD	366	/*
	367	* Poll the control register for the reset bit to go to 0 (it is
	368	* auto-clearing). This should happen within 0.5 seconds per the
	369	* IEEE spec.
	370	*/
c609719b	371	reg = 0x8000;
ab5a0dcb	372	while (((reg & 0x8000) != 0) && timeout--) {
8ef583a0	373	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
ab5a0dcb SR	374	debug("PHY status read failed\n");
ab5a0dcb SR	375	return -1;
c609719b	376	}
ab5a0dcb	377	udelay(1000);
c609719b WD	378	}
c609719b WD	379	if ((reg & 0x8000) == 0) {
16a53238	380	return 0;
c609719b	381	} else {
16a53238 AF	382	puts("PHY reset timed out\n");
16a53238 AF	383	return -1;
c609719b	384	}
16a53238	385	return 0;
c609719b	386	}
5f184715	387	#endif /* !PHYLIB */
c609719b	388
c609719b WD	389	/*****************************************************************************
c609719b WD	390	*
71bc6e64	391	* Determine the ethernet speed (10/100/1000). Return 10 on error.
c609719b	392	*/
5700bb63	393	int miiphy_speed(const char *devname, unsigned char addr)
c609719b	394	{
8c83c030	395	u16 bmcr, anlpar, adv;
c609719b	396
6fb6af6d	397	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	398	u16 btsr;
	399
	400	/*
	401	* Check for 1000BASE-X. If it is supported, then assume that the speed
	402	* is 1000.
	403	*/
16a53238	404	if (miiphy_is_1000base_x(devname, addr))
71bc6e64	405	return _1000BASET;
16a53238	406
71bc6e64 LJ	407	/*
	408	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	409	*/
	410	/* Check for 1000BASE-T. */
16a53238 AF	411	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
16a53238 AF	412	printf("PHY 1000BT status");
71bc6e64 LJ	413	goto miiphy_read_failed;
	414	}
	415	if (btsr != 0xFFFF &&
16a53238	416	(btsr & (PHY_1000BTSR_1000FD \| PHY_1000BTSR_1000HD)))
71bc6e64	417	return _1000BASET;
6fb6af6d	418	#endif /* CONFIG_PHY_GIGE */
855a496f	419
a56bd922	420	/* Check Basic Management Control Register first. */
16a53238 AF	421	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
16a53238 AF	422	printf("PHY speed");
71bc6e64	423	goto miiphy_read_failed;
c609719b	424	}
a56bd922	425	/* Check if auto-negotiation is on. */
8ef583a0	426	if (bmcr & BMCR_ANENABLE) {
a56bd922	427	/* Get auto-negotiation results. */
16a53238 AF	428	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	429	printf("PHY AN speed");
71bc6e64	430	goto miiphy_read_failed;
a56bd922	431	}
8c83c030 DL	432
	433	if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
	434	puts("PHY AN adv speed");
	435	goto miiphy_read_failed;
	436	}
	437	return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
a56bd922 WD	438	}
a56bd922 WD	439	/* Get speed from basic control settings. */
8ef583a0	440	return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
a56bd922	441
5f841959	442	miiphy_read_failed:
16a53238	443	printf(" read failed, assuming 10BASE-T\n");
71bc6e64	444	return _10BASET;
c609719b WD	445	}
c609719b WD	446
c609719b WD	447	/*****************************************************************************
c609719b WD	448	*
71bc6e64	449	* Determine full/half duplex. Return half on error.
c609719b	450	*/
5700bb63	451	int miiphy_duplex(const char *devname, unsigned char addr)
c609719b	452	{
8c83c030	453	u16 bmcr, anlpar, adv;
c609719b	454
6fb6af6d	455	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	456	u16 btsr;
	457
	458	/* Check for 1000BASE-X. */
16a53238	459	if (miiphy_is_1000base_x(devname, addr)) {
71bc6e64	460	/* 1000BASE-X */
16a53238 AF	461	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	462	printf("1000BASE-X PHY AN duplex");
71bc6e64 LJ	463	goto miiphy_read_failed;
	464	}
	465	}
	466	/*
	467	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	468	*/
	469	/* Check for 1000BASE-T. */
16a53238 AF	470	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
16a53238 AF	471	printf("PHY 1000BT status");
71bc6e64 LJ	472	goto miiphy_read_failed;
	473	}
	474	if (btsr != 0xFFFF) {
	475	if (btsr & PHY_1000BTSR_1000FD) {
	476	return FULL;
	477	} else if (btsr & PHY_1000BTSR_1000HD) {
	478	return HALF;
855a496f WD	479	}
855a496f WD	480	}
6fb6af6d	481	#endif /* CONFIG_PHY_GIGE */
855a496f	482
a56bd922	483	/* Check Basic Management Control Register first. */
16a53238 AF	484	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
16a53238 AF	485	puts("PHY duplex");
71bc6e64	486	goto miiphy_read_failed;
c609719b	487	}
a56bd922	488	/* Check if auto-negotiation is on. */
8ef583a0	489	if (bmcr & BMCR_ANENABLE) {
a56bd922	490	/* Get auto-negotiation results. */
16a53238 AF	491	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	492	puts("PHY AN duplex");
71bc6e64	493	goto miiphy_read_failed;
a56bd922	494	}
8c83c030 DL	495
	496	if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
	497	puts("PHY AN adv duplex");
	498	goto miiphy_read_failed;
	499	}
	500	return ((anlpar & adv) & (LPA_10FULL \| LPA_100FULL)) ?
71bc6e64	501	FULL : HALF;
a56bd922 WD	502	}
a56bd922 WD	503	/* Get speed from basic control settings. */
8ef583a0	504	return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;
71bc6e64	505
5f841959	506	miiphy_read_failed:
16a53238	507	printf(" read failed, assuming half duplex\n");
71bc6e64 LJ	508	return HALF;
71bc6e64 LJ	509	}
a56bd922	510
71bc6e64 LJ	511	/*****************************************************************************
	512	*
	513	* Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
	514	* 1000BASE-T, or on error.
	515	*/
5700bb63	516	int miiphy_is_1000base_x(const char *devname, unsigned char addr)
71bc6e64 LJ	517	{
	518	#if defined(CONFIG_PHY_GIGE)
	519	u16 exsr;
	520
16a53238 AF	521	if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
16a53238 AF	522	printf("PHY extended status read failed, assuming no "
71bc6e64 LJ	523	"1000BASE-X\n");
	524	return 0;
	525	}
8ef583a0	526	return 0 != (exsr & (ESTATUS_1000XF \| ESTATUS_1000XH));
71bc6e64 LJ	527	#else
	528	return 0;
	529	#endif
c609719b WD	530	}
c609719b WD	531
6d0f6bcf	532	#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
fc3e2165 WD	533	/*****************************************************************************
	534	*
	535	* Determine link status
	536	*/
5700bb63	537	int miiphy_link(const char *devname, unsigned char addr)
fc3e2165 WD	538	{
	539	unsigned short reg;
	540
a3d991bd	541	/* dummy read; needed to latch some phys */
16a53238 AF	542	(void)miiphy_read(devname, addr, MII_BMSR, &reg);
	543	if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
	544	puts("MII_BMSR read failed, assuming no link\n");
	545	return 0;
fc3e2165 WD	546	}
	547
	548	/* Determine if a link is active */
8ef583a0	549	if ((reg & BMSR_LSTATUS) != 0) {
16a53238	550	return 1;
fc3e2165	551	} else {
16a53238	552	return 0;
fc3e2165 WD	553	}
	554	}
	555	#endif