[people/ms/u-boot.git] / common / miiphyutil.c

/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * This provides a bit-banged interface to the ethernet MII management
 * channel.
 */

#include <common.h>
#include <miiphy.h>

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>

/* local debug macro */
#undef MII_DEBUG

#undef debug
#ifdef MII_DEBUG
#define debug(fmt,args...)	printf (fmt ,##args)
#else
#define debug(fmt,args...)
#endif /* MII_DEBUG */

struct mii_dev {
	struct list_head link;
	char *name;
	int (*read) (char *devname, unsigned char addr,
		     unsigned char reg, unsigned short *value);
	int (*write) (char *devname, unsigned char addr,
		      unsigned char reg, unsigned short value);
};

static struct list_head mii_devs;
static struct mii_dev *current_mii;

/*****************************************************************************
 *
 * Initialize global data. Need to be called before any other miiphy routine.
 */
void miiphy_init ()
{
	INIT_LIST_HEAD (&mii_devs);
	current_mii = NULL;
}

/*****************************************************************************
 *
 * Register read and write MII access routines for the device <name>.
 */
void miiphy_register (char *name,
		      int (*read) (char *devname, unsigned char addr,
				   unsigned char reg, unsigned short *value),
		      int (*write) (char *devname, unsigned char addr,
				    unsigned char reg, unsigned short value))
{
	struct list_head *entry;
	struct mii_dev *new_dev;
	struct mii_dev *miidev;
	unsigned int name_len;

	/* check if we have unique name */
	list_for_each (entry, &mii_devs) {
		miidev = list_entry (entry, struct mii_dev, link);
		if (strcmp (miidev->name, name) == 0) {
			printf ("miiphy_register: non unique device name "
				"'%s'\n", name);
			return;
		}
	}

	/* allocate memory */
	name_len = strlen (name);
	new_dev =
	    (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);

	if (new_dev == NULL) {
		printf ("miiphy_register: cannot allocate memory for '%s'\n",
			name);
		return;
	}
	memset (new_dev, 0, sizeof (struct mii_dev) + name_len);

	/* initalize mii_dev struct fields */
	INIT_LIST_HEAD (&new_dev->link);
	new_dev->read = read;
	new_dev->write = write;
	new_dev->name = (char *)(new_dev + 1);
	strncpy (new_dev->name, name, name_len);
	new_dev->name[name_len] = '\0';

	debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
	       new_dev->name, new_dev->read, new_dev->write);

	/* add it to the list */
	list_add_tail (&new_dev->link, &mii_devs);

	if (!current_mii)
		current_mii = new_dev;
}

int miiphy_set_current_dev (char *devname)
{
	struct list_head *entry;
	struct mii_dev *dev;

	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);

		if (strcmp (devname, dev->name) == 0) {
			current_mii = dev;
			return 0;
		}
	}

	printf ("No such device: %s\n", devname);
	return 1;
}

char *miiphy_get_current_dev ()
{
	if (current_mii)
		return current_mii->name;

	return NULL;
}

/*****************************************************************************
 *
 * Read to variable <value> from the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * Returns:
 *   0 on success
 */
int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
		 unsigned short *value)
{
	struct list_head *entry;
	struct mii_dev *dev;
	int found_dev = 0;
	int read_ret = 0;

	if (!devname) {
		printf ("NULL device name!\n");
		return 1;
	}

	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);

		if (strcmp (devname, dev->name) == 0) {
			found_dev = 1;
			read_ret = dev->read (devname, addr, reg, value);
			break;
		}
	}

	if (found_dev == 0)
		printf ("No such device: %s\n", devname);

	return ((found_dev) ? read_ret : 1);
}

/*****************************************************************************
 *
 * Write <value> to the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * Returns:
 *   0 on success
 */
int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
		  unsigned short value)
{
	struct list_head *entry;
	struct mii_dev *dev;
	int found_dev = 0;
	int write_ret = 0;

	if (!devname) {
		printf ("NULL device name!\n");
		return 1;
	}

	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);

		if (strcmp (devname, dev->name) == 0) {
			found_dev = 1;
			write_ret = dev->write (devname, addr, reg, value);
			break;
		}
	}

	if (found_dev == 0)
		printf ("No such device: %s\n", devname);

	return ((found_dev) ? write_ret : 1);
}

/*****************************************************************************
 *
 * Print out list of registered MII capable devices.
 */
void miiphy_listdev (void)
{
	struct list_head *entry;
	struct mii_dev *dev;

	puts ("MII devices: ");
	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);
		printf ("'%s' ", dev->name);
	}
	puts ("\n");

	if (current_mii)
		printf ("Current device: '%s'\n", current_mii->name);
}

/*****************************************************************************
 *
 * Read the OUI, manufacture's model number, and revision number.
 *
 * OUI:     22 bits (unsigned int)
 * Model:    6 bits (unsigned char)
 * Revision: 4 bits (unsigned char)
 *
 * Returns:
 *   0 on success
 */
int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
		 unsigned char *model, unsigned char *rev)
{
	unsigned int reg = 0;
	unsigned short tmp;

	if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
		debug ("PHY ID register 2 read failed\n");
		return (-1);
	}
	reg = tmp;

	debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);

	if (reg == 0xFFFF) {
		/* No physical device present at this address */
		return (-1);
	}

	if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
		debug ("PHY ID register 1 read failed\n");
		return (-1);
	}
	reg |= tmp << 16;
	debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);

	*oui = (reg >> 10);
	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	*rev = (unsigned char)(reg & 0x0000000F);
	return (0);
}

/*****************************************************************************
 *
 * Reset the PHY.
 * Returns:
 *   0 on success
 */
int miiphy_reset (char *devname, unsigned char addr)
{
	unsigned short reg;
	int loop_cnt;

	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
		debug ("PHY status read failed\n");
		return (-1);
	}
	if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
		debug ("PHY reset failed\n");
		return (-1);
	}
#ifdef CONFIG_PHY_RESET_DELAY
	udelay (CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
#endif
	/*
	 * Poll the control register for the reset bit to go to 0 (it is
	 * auto-clearing).  This should happen within 0.5 seconds per the
	 * IEEE spec.
	 */
	loop_cnt = 0;
	reg = 0x8000;
	while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
		if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
			debug ("PHY status read failed\n");
			return (-1);
		}
	}
	if ((reg & 0x8000) == 0) {
		return (0);
	} else {
		puts ("PHY reset timed out\n");
		return (-1);
	}
	return (0);
}

/*****************************************************************************
 *
 * Determine the ethernet speed (10/100/1000).  Return 10 on error.
 */
int miiphy_speed (char *devname, unsigned char addr)
{
	u16 bmcr, anlpar;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/*
	 * Check for 1000BASE-X.  If it is supported, then assume that the speed
	 * is 1000.
	 */
	if (miiphy_is_1000base_x (devname, addr)) {
		return _1000BASET;
	}
	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
		printf ("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF &&
	    (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
		return _1000BASET;
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
		printf ("PHY speed");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & PHY_BMCR_AUTON) {
		/* Get auto-negotiation results. */
		if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
			printf ("PHY AN speed");
			goto miiphy_read_failed;
		}
		return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
	}
	/* Get speed from basic control settings. */
	return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;

      miiphy_read_failed:
	printf (" read failed, assuming 10BASE-T\n");
	return _10BASET;
}

/*****************************************************************************
 *
 * Determine full/half duplex.  Return half on error.
 */
int miiphy_duplex (char *devname, unsigned char addr)
{
	u16 bmcr, anlpar;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/* Check for 1000BASE-X. */
	if (miiphy_is_1000base_x (devname, addr)) {
		/* 1000BASE-X */
		if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
			printf ("1000BASE-X PHY AN duplex");
			goto miiphy_read_failed;
		}
	}
	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
		printf ("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF) {
		if (btsr & PHY_1000BTSR_1000FD) {
			return FULL;
		} else if (btsr & PHY_1000BTSR_1000HD) {
			return HALF;
		}
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
		puts ("PHY duplex");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & PHY_BMCR_AUTON) {
		/* Get auto-negotiation results. */
		if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
			puts ("PHY AN duplex");
			goto miiphy_read_failed;
		}
		return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ?
		    FULL : HALF;
	}
	/* Get speed from basic control settings. */
	return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;

      miiphy_read_failed:
	printf (" read failed, assuming half duplex\n");
	return HALF;
}

/*****************************************************************************
 *
 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
 * 1000BASE-T, or on error.
 */
int miiphy_is_1000base_x (char *devname, unsigned char addr)
{
#if defined(CONFIG_PHY_GIGE)
	u16 exsr;

	if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
		printf ("PHY extended status read failed, assuming no "
			"1000BASE-X\n");
		return 0;
	}
	return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH));
#else
	return 0;
#endif
}

#ifdef CFG_FAULT_ECHO_LINK_DOWN
/*****************************************************************************
 *
 * Determine link status
 */
int miiphy_link (char *devname, unsigned char addr)
{
	unsigned short reg;

	/* dummy read; needed to latch some phys */
	(void)miiphy_read (devname, addr, PHY_BMSR, &reg);
	if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
		puts ("PHY_BMSR read failed, assuming no link\n");
		return (0);
	}

	/* Determine if a link is active */
	if ((reg & PHY_BMSR_LS) != 0) {
		return (1);
	} else {
		return (0);
	}
}
#endif
#endif /* CONFIG_MII */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* This provides a bit-banged interface to the ethernet MII management
	26	* channel.
	27	*/
	28
	29	#include <common.h>
	30	#include <miiphy.h>
	31
c3517f91	32	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
63ff004c MB	33	#include <asm/types.h>
	34	#include <linux/list.h>
	35	#include <malloc.h>
	36	#include <net.h>
	37
	38	/* local debug macro */
63ff004c MB	39	#undef MII_DEBUG
	40
	41	#undef debug
	42	#ifdef MII_DEBUG
	43	#define debug(fmt,args...) printf (fmt ,##args)
	44	#else
	45	#define debug(fmt,args...)
	46	#endif /* MII_DEBUG */
	47
	48	struct mii_dev {
	49	struct list_head link;
	50	char *name;
298035df LJ	51	int (read) (char devname, unsigned char addr,
	52	unsigned char reg, unsigned short *value);
	53	int (write) (char devname, unsigned char addr,
	54	unsigned char reg, unsigned short value);
63ff004c MB	55	};
	56
	57	static struct list_head mii_devs;
	58	static struct mii_dev *current_mii;
	59
d9785c14 MB	60	/*****************************************************************************
	61	*
	62	* Initialize global data. Need to be called before any other miiphy routine.
	63	*/
298035df	64	void miiphy_init ()
d9785c14	65	{
298035df LJ	66	INIT_LIST_HEAD (&mii_devs);
298035df LJ	67	current_mii = NULL;
d9785c14 MB	68	}
d9785c14 MB	69
63ff004c MB	70	/*****************************************************************************
	71	*
	72	* Register read and write MII access routines for the device <name>.
	73	*/
298035df LJ	74	void miiphy_register (char *name,
	75	int (read) (char devname, unsigned char addr,
	76	unsigned char reg, unsigned short *value),
	77	int (write) (char devname, unsigned char addr,
	78	unsigned char reg, unsigned short value))
63ff004c MB	79	{
	80	struct list_head *entry;
	81	struct mii_dev *new_dev;
	82	struct mii_dev *miidev;
63ff004c MB	83	unsigned int name_len;
63ff004c MB	84
63ff004c	85	/* check if we have unique name */
298035df LJ	86	list_for_each (entry, &mii_devs) {
	87	miidev = list_entry (entry, struct mii_dev, link);
	88	if (strcmp (miidev->name, name) == 0) {
	89	printf ("miiphy_register: non unique device name "
	90	"'%s'\n", name);
63ff004c MB	91	return;
	92	}
	93	}
	94
	95	/* allocate memory */
298035df LJ	96	name_len = strlen (name);
	97	new_dev =
	98	(struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
63ff004c	99
298035df LJ	100	if (new_dev == NULL) {
	101	printf ("miiphy_register: cannot allocate memory for '%s'\n",
	102	name);
63ff004c MB	103	return;
63ff004c MB	104	}
298035df	105	memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
63ff004c MB	106
63ff004c MB	107	/* initalize mii_dev struct fields */
298035df	108	INIT_LIST_HEAD (&new_dev->link);
63ff004c MB	109	new_dev->read = read;
	110	new_dev->write = write;
	111	new_dev->name = (char *)(new_dev + 1);
298035df	112	strncpy (new_dev->name, name, name_len);
63ff004c MB	113	new_dev->name[name_len] = '\0';
63ff004c MB	114
298035df LJ	115	debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
298035df LJ	116	new_dev->name, new_dev->read, new_dev->write);
63ff004c MB	117
63ff004c MB	118	/* add it to the list */
298035df	119	list_add_tail (&new_dev->link, &mii_devs);
63ff004c MB	120
	121	if (!current_mii)
	122	current_mii = new_dev;
	123	}
	124
298035df	125	int miiphy_set_current_dev (char *devname)
63ff004c MB	126	{
	127	struct list_head *entry;
	128	struct mii_dev *dev;
	129
298035df LJ	130	list_for_each (entry, &mii_devs) {
298035df LJ	131	dev = list_entry (entry, struct mii_dev, link);
63ff004c	132
298035df	133	if (strcmp (devname, dev->name) == 0) {
63ff004c MB	134	current_mii = dev;
	135	return 0;
	136	}
	137	}
	138
298035df	139	printf ("No such device: %s\n", devname);
63ff004c MB	140	return 1;
	141	}
	142
298035df	143	char *miiphy_get_current_dev ()
63ff004c MB	144	{
	145	if (current_mii)
	146	return current_mii->name;
	147
	148	return NULL;
	149	}
	150
	151	/*****************************************************************************
	152	*
	153	* Read to variable <value> from the PHY attached to device <devname>,
	154	* use PHY address <addr> and register <reg>.
	155	*
	156	* Returns:
	157	* 0 on success
	158	*/
298035df LJ	159	int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
298035df LJ	160	unsigned short *value)
63ff004c MB	161	{
	162	struct list_head *entry;
	163	struct mii_dev *dev;
	164	int found_dev = 0;
	165	int read_ret = 0;
	166
	167	if (!devname) {
298035df	168	printf ("NULL device name!\n");
63ff004c MB	169	return 1;
	170	}
	171
298035df LJ	172	list_for_each (entry, &mii_devs) {
298035df LJ	173	dev = list_entry (entry, struct mii_dev, link);
63ff004c	174
298035df	175	if (strcmp (devname, dev->name) == 0) {
63ff004c	176	found_dev = 1;
298035df	177	read_ret = dev->read (devname, addr, reg, value);
63ff004c MB	178	break;
	179	}
	180	}
	181
	182	if (found_dev == 0)
298035df	183	printf ("No such device: %s\n", devname);
63ff004c MB	184
	185	return ((found_dev) ? read_ret : 1);
	186	}
	187
	188	/*****************************************************************************
	189	*
	190	* Write <value> to the PHY attached to device <devname>,
	191	* use PHY address <addr> and register <reg>.
	192	*
	193	* Returns:
	194	* 0 on success
	195	*/
298035df LJ	196	int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
298035df LJ	197	unsigned short value)
63ff004c MB	198	{
	199	struct list_head *entry;
	200	struct mii_dev *dev;
	201	int found_dev = 0;
	202	int write_ret = 0;
	203
	204	if (!devname) {
298035df	205	printf ("NULL device name!\n");
63ff004c MB	206	return 1;
	207	}
	208
298035df LJ	209	list_for_each (entry, &mii_devs) {
298035df LJ	210	dev = list_entry (entry, struct mii_dev, link);
63ff004c	211
298035df	212	if (strcmp (devname, dev->name) == 0) {
63ff004c	213	found_dev = 1;
298035df	214	write_ret = dev->write (devname, addr, reg, value);
63ff004c MB	215	break;
	216	}
	217	}
	218
	219	if (found_dev == 0)
298035df	220	printf ("No such device: %s\n", devname);
63ff004c MB	221
	222	return ((found_dev) ? write_ret : 1);
	223	}
	224
	225	/*****************************************************************************
	226	*
	227	* Print out list of registered MII capable devices.
	228	*/
298035df	229	void miiphy_listdev (void)
63ff004c MB	230	{
	231	struct list_head *entry;
	232	struct mii_dev *dev;
	233
298035df LJ	234	puts ("MII devices: ");
	235	list_for_each (entry, &mii_devs) {
	236	dev = list_entry (entry, struct mii_dev, link);
	237	printf ("'%s' ", dev->name);
63ff004c	238	}
298035df	239	puts ("\n");
63ff004c MB	240
63ff004c MB	241	if (current_mii)
298035df	242	printf ("Current device: '%s'\n", current_mii->name);
63ff004c MB	243	}
63ff004c MB	244
c609719b WD	245	/*****************************************************************************
	246	*
	247	* Read the OUI, manufacture's model number, and revision number.
	248	*
	249	* OUI: 22 bits (unsigned int)
	250	* Model: 6 bits (unsigned char)
	251	* Revision: 4 bits (unsigned char)
	252	*
	253	* Returns:
	254	* 0 on success
	255	*/
298035df	256	int miiphy_info (char devname, unsigned char addr, unsigned int oui,
c609719b WD	257	unsigned char model, unsigned char rev)
	258	{
	259	unsigned int reg = 0;
8bf3b005	260	unsigned short tmp;
c609719b	261
63ff004c	262	if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
26c7bab8	263	debug ("PHY ID register 2 read failed\n");
c609719b WD	264	return (-1);
c609719b WD	265	}
8bf3b005	266	reg = tmp;
c609719b	267
26c7bab8 SK	268	debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
26c7bab8 SK	269
c609719b WD	270	if (reg == 0xFFFF) {
	271	/* No physical device present at this address */
	272	return (-1);
	273	}
	274
63ff004c	275	if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
26c7bab8	276	debug ("PHY ID register 1 read failed\n");
c609719b WD	277	return (-1);
c609719b WD	278	}
8bf3b005	279	reg \|= tmp << 16;
26c7bab8 SK	280	debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
26c7bab8 SK	281
298035df LJ	282	*oui = (reg >> 10);
	283	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	284	*rev = (unsigned char)(reg & 0x0000000F);
c609719b WD	285	return (0);
	286	}
	287
c609719b WD	288	/*****************************************************************************
	289	*
	290	* Reset the PHY.
	291	* Returns:
	292	* 0 on success
	293	*/
63ff004c	294	int miiphy_reset (char *devname, unsigned char addr)
c609719b WD	295	{
	296	unsigned short reg;
	297	int loop_cnt;
	298
63ff004c	299	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
26c7bab8	300	debug ("PHY status read failed\n");
f89920c3 WD	301	return (-1);
f89920c3 WD	302	}
63ff004c	303	if (miiphy_write (devname, addr, PHY_BMCR, reg \| 0x8000) != 0) {
26c7bab8	304	debug ("PHY reset failed\n");
c609719b WD	305	return (-1);
c609719b WD	306	}
5653fc33 WD	307	#ifdef CONFIG_PHY_RESET_DELAY
	308	udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
	309	#endif
c609719b WD	310	/*
	311	* Poll the control register for the reset bit to go to 0 (it is
	312	* auto-clearing). This should happen within 0.5 seconds per the
	313	* IEEE spec.
	314	*/
	315	loop_cnt = 0;
	316	reg = 0x8000;
	317	while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
63ff004c	318	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
26c7bab8	319	debug ("PHY status read failed\n");
c609719b WD	320	return (-1);
	321	}
	322	}
	323	if ((reg & 0x8000) == 0) {
	324	return (0);
	325	} else {
4b9206ed	326	puts ("PHY reset timed out\n");
c609719b WD	327	return (-1);
	328	}
	329	return (0);
	330	}
	331
c609719b WD	332	/*****************************************************************************
c609719b WD	333	*
71bc6e64	334	* Determine the ethernet speed (10/100/1000). Return 10 on error.
c609719b	335	*/
63ff004c	336	int miiphy_speed (char *devname, unsigned char addr)
c609719b	337	{
71bc6e64	338	u16 bmcr, anlpar;
c609719b	339
6fb6af6d	340	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	341	u16 btsr;
	342
	343	/*
	344	* Check for 1000BASE-X. If it is supported, then assume that the speed
	345	* is 1000.
	346	*/
	347	if (miiphy_is_1000base_x (devname, addr)) {
	348	return _1000BASET;
	349	}
	350	/*
	351	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	352	*/
	353	/* Check for 1000BASE-T. */
	354	if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
	355	printf ("PHY 1000BT status");
	356	goto miiphy_read_failed;
	357	}
	358	if (btsr != 0xFFFF &&
	359	(btsr & (PHY_1000BTSR_1000FD \| PHY_1000BTSR_1000HD))) {
	360	return _1000BASET;
855a496f	361	}
6fb6af6d	362	#endif /* CONFIG_PHY_GIGE */
855a496f	363
a56bd922	364	/* Check Basic Management Control Register first. */
71bc6e64 LJ	365	if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
	366	printf ("PHY speed");
	367	goto miiphy_read_failed;
c609719b	368	}
a56bd922	369	/* Check if auto-negotiation is on. */
71bc6e64	370	if (bmcr & PHY_BMCR_AUTON) {
a56bd922	371	/* Get auto-negotiation results. */
71bc6e64 LJ	372	if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
	373	printf ("PHY AN speed");
	374	goto miiphy_read_failed;
a56bd922	375	}
71bc6e64	376	return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
a56bd922 WD	377	}
a56bd922 WD	378	/* Get speed from basic control settings. */
71bc6e64	379	return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
a56bd922	380
71bc6e64 LJ	381	miiphy_read_failed:
	382	printf (" read failed, assuming 10BASE-T\n");
	383	return _10BASET;
c609719b WD	384	}
c609719b WD	385
c609719b WD	386	/*****************************************************************************
c609719b WD	387	*
71bc6e64	388	* Determine full/half duplex. Return half on error.
c609719b	389	*/
63ff004c	390	int miiphy_duplex (char *devname, unsigned char addr)
c609719b	391	{
71bc6e64	392	u16 bmcr, anlpar;
c609719b	393
6fb6af6d	394	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	395	u16 btsr;
	396
	397	/* Check for 1000BASE-X. */
	398	if (miiphy_is_1000base_x (devname, addr)) {
	399	/* 1000BASE-X */
	400	if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
	401	printf ("1000BASE-X PHY AN duplex");
	402	goto miiphy_read_failed;
	403	}
	404	}
	405	/*
	406	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	407	*/
	408	/* Check for 1000BASE-T. */
	409	if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
	410	printf ("PHY 1000BT status");
	411	goto miiphy_read_failed;
	412	}
	413	if (btsr != 0xFFFF) {
	414	if (btsr & PHY_1000BTSR_1000FD) {
	415	return FULL;
	416	} else if (btsr & PHY_1000BTSR_1000HD) {
	417	return HALF;
855a496f WD	418	}
855a496f WD	419	}
6fb6af6d	420	#endif /* CONFIG_PHY_GIGE */
855a496f	421
a56bd922	422	/* Check Basic Management Control Register first. */
71bc6e64 LJ	423	if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
	424	puts ("PHY duplex");
	425	goto miiphy_read_failed;
c609719b	426	}
a56bd922	427	/* Check if auto-negotiation is on. */
71bc6e64	428	if (bmcr & PHY_BMCR_AUTON) {
a56bd922	429	/* Get auto-negotiation results. */
71bc6e64 LJ	430	if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
	431	puts ("PHY AN duplex");
	432	goto miiphy_read_failed;
a56bd922	433	}
71bc6e64 LJ	434	return (anlpar & (PHY_ANLPAR_10FD \| PHY_ANLPAR_TXFD)) ?
71bc6e64 LJ	435	FULL : HALF;
a56bd922 WD	436	}
a56bd922 WD	437	/* Get speed from basic control settings. */
71bc6e64 LJ	438	return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
	439
	440	miiphy_read_failed:
	441	printf (" read failed, assuming half duplex\n");
	442	return HALF;
	443	}
a56bd922	444
71bc6e64 LJ	445	/*****************************************************************************
	446	*
	447	* Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
	448	* 1000BASE-T, or on error.
	449	*/
	450	int miiphy_is_1000base_x (char *devname, unsigned char addr)
	451	{
	452	#if defined(CONFIG_PHY_GIGE)
	453	u16 exsr;
	454
	455	if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
	456	printf ("PHY extended status read failed, assuming no "
	457	"1000BASE-X\n");
	458	return 0;
	459	}
	460	return 0 != (exsr & (PHY_EXSR_1000XF \| PHY_EXSR_1000XH));
	461	#else
	462	return 0;
	463	#endif
c609719b WD	464	}
c609719b WD	465
fc3e2165 WD	466	#ifdef CFG_FAULT_ECHO_LINK_DOWN
	467	/*****************************************************************************
	468	*
	469	* Determine link status
	470	*/
63ff004c	471	int miiphy_link (char *devname, unsigned char addr)
fc3e2165 WD	472	{
	473	unsigned short reg;
	474
a3d991bd	475	/* dummy read; needed to latch some phys */
298035df	476	(void)miiphy_read (devname, addr, PHY_BMSR, &reg);
63ff004c	477	if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
4b9206ed	478	puts ("PHY_BMSR read failed, assuming no link\n");
fc3e2165 WD	479	return (0);
	480	}
	481
	482	/* Determine if a link is active */
	483	if ((reg & PHY_BMSR_LS) != 0) {
	484	return (1);
	485	} else {
	486	return (0);
	487	}
	488	}
	489	#endif
c3517f91	490	#endif /* CONFIG_MII */