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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Alex Zuepke <azu@sysgo.de> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
30 | #include <clps7111.h> | |
31 | ||
32 | #include <asm/proc-armv/ptrace.h> | |
33 | ||
34 | extern void reset_cpu(ulong addr); | |
35 | ||
36 | /* we always count down the max. */ | |
37 | #define TIMER_LOAD_VAL 0xffff | |
38 | ||
39 | /* macro to read the 16 bit timer */ | |
40 | #define READ_TIMER (IO_TC1D & 0xffff) | |
41 | ||
42 | #ifdef CONFIG_USE_IRQ | |
43 | /* enable IRQ/FIQ interrupts */ | |
44 | void enable_interrupts (void) | |
45 | { | |
46 | unsigned long temp; | |
47 | __asm__ __volatile__("mrs %0, cpsr\n" | |
48 | "bic %0, %0, #0x80\n" | |
49 | "msr cpsr_c, %0" | |
50 | : "=r" (temp) | |
51 | : | |
52 | : "memory"); | |
53 | } | |
54 | ||
55 | ||
56 | /* | |
57 | * disable IRQ/FIQ interrupts | |
58 | * returns true if interrupts had been enabled before we disabled them | |
59 | */ | |
60 | int disable_interrupts (void) | |
61 | { | |
62 | unsigned long old,temp; | |
63 | __asm__ __volatile__("mrs %0, cpsr\n" | |
64 | "orr %1, %0, #0x80\n" | |
65 | "msr cpsr_c, %1" | |
66 | : "=r" (old), "=r" (temp) | |
67 | : | |
68 | : "memory"); | |
69 | return (old & 0x80) == 0; | |
70 | } | |
71 | #else | |
72 | void enable_interrupts (void) | |
73 | { | |
74 | return; | |
75 | } | |
76 | int disable_interrupts (void) | |
77 | { | |
78 | return 0; | |
79 | } | |
80 | #endif | |
81 | ||
82 | ||
c609719b WD |
83 | void bad_mode (void) |
84 | { | |
85 | panic ("Resetting CPU ...\n"); | |
86 | reset_cpu (0); | |
87 | } | |
88 | ||
89 | void show_regs (struct pt_regs *regs) | |
90 | { | |
91 | unsigned long flags; | |
92 | const char *processor_modes[] = | |
8bde7f77 | 93 | { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", |
c609719b WD |
94 | "UK6_26", "UK7_26", |
95 | "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", | |
96 | "UK14_26", "UK15_26", | |
97 | "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", | |
98 | "UK6_32", "ABT_32", | |
99 | "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", | |
100 | "UK14_32", "SYS_32" | |
101 | }; | |
102 | ||
103 | flags = condition_codes (regs); | |
104 | ||
105 | printf ("pc : [<%08lx>] lr : [<%08lx>]\n" | |
106 | "sp : %08lx ip : %08lx fp : %08lx\n", | |
107 | instruction_pointer (regs), | |
108 | regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); | |
109 | printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", | |
110 | regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); | |
111 | printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", | |
112 | regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); | |
113 | printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", | |
114 | regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); | |
115 | printf ("Flags: %c%c%c%c", | |
116 | flags & CC_N_BIT ? 'N' : 'n', | |
117 | flags & CC_Z_BIT ? 'Z' : 'z', | |
118 | flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); | |
119 | printf (" IRQs %s FIQs %s Mode %s%s\n", | |
120 | interrupts_enabled (regs) ? "on" : "off", | |
121 | fast_interrupts_enabled (regs) ? "on" : "off", | |
122 | processor_modes[processor_mode (regs)], | |
123 | thumb_mode (regs) ? " (T)" : ""); | |
124 | } | |
125 | ||
126 | void do_undefined_instruction (struct pt_regs *pt_regs) | |
127 | { | |
128 | printf ("undefined instruction\n"); | |
129 | show_regs (pt_regs); | |
130 | bad_mode (); | |
131 | } | |
132 | ||
133 | void do_software_interrupt (struct pt_regs *pt_regs) | |
134 | { | |
135 | printf ("software interrupt\n"); | |
136 | show_regs (pt_regs); | |
137 | bad_mode (); | |
138 | } | |
139 | ||
140 | void do_prefetch_abort (struct pt_regs *pt_regs) | |
141 | { | |
142 | printf ("prefetch abort\n"); | |
143 | show_regs (pt_regs); | |
144 | bad_mode (); | |
145 | } | |
146 | ||
147 | void do_data_abort (struct pt_regs *pt_regs) | |
148 | { | |
149 | printf ("data abort\n"); | |
150 | show_regs (pt_regs); | |
151 | bad_mode (); | |
152 | } | |
153 | ||
154 | void do_not_used (struct pt_regs *pt_regs) | |
155 | { | |
156 | printf ("not used\n"); | |
157 | show_regs (pt_regs); | |
158 | bad_mode (); | |
159 | } | |
160 | ||
161 | void do_fiq (struct pt_regs *pt_regs) | |
162 | { | |
163 | printf ("fast interrupt request\n"); | |
164 | show_regs (pt_regs); | |
165 | bad_mode (); | |
166 | } | |
167 | ||
168 | void do_irq (struct pt_regs *pt_regs) | |
169 | { | |
170 | printf ("interrupt request\n"); | |
171 | show_regs (pt_regs); | |
172 | bad_mode (); | |
173 | } | |
174 | ||
175 | static ulong timestamp; | |
176 | static ulong lastdec; | |
177 | ||
178 | int interrupt_init (void) | |
179 | { | |
180 | /* disable all interrupts */ | |
181 | IO_INTMR1 = 0; | |
182 | ||
183 | /* operate timer 1 in prescale mode */ | |
184 | IO_SYSCON1 |= SYSCON1_TC1M; | |
185 | ||
186 | /* select 2kHz clock source for timer 1 */ | |
187 | IO_SYSCON1 &= ~SYSCON1_TC1S; | |
188 | ||
189 | /* set timer 1 counter */ | |
190 | lastdec = IO_TC1D = TIMER_LOAD_VAL; | |
191 | timestamp = 0; | |
192 | ||
193 | return (0); | |
194 | } | |
195 | ||
196 | /* | |
197 | * timer without interrupts | |
198 | */ | |
199 | ||
200 | void reset_timer (void) | |
201 | { | |
202 | reset_timer_masked (); | |
203 | } | |
204 | ||
205 | ulong get_timer (ulong base) | |
206 | { | |
207 | return get_timer_masked () - base; | |
208 | } | |
209 | ||
210 | void set_timer (ulong t) | |
211 | { | |
212 | timestamp = t; | |
213 | } | |
214 | ||
215 | void udelay (unsigned long usec) | |
216 | { | |
217 | ulong tmo; | |
218 | ||
219 | tmo = usec / 1000; | |
220 | tmo *= CFG_HZ; | |
221 | tmo /= 1000; | |
222 | ||
223 | tmo += get_timer (0); | |
224 | ||
225 | while (get_timer_masked () < tmo) | |
226 | /*NOP*/; | |
227 | } | |
228 | ||
229 | void reset_timer_masked (void) | |
230 | { | |
231 | /* reset time */ | |
232 | lastdec = READ_TIMER; | |
233 | timestamp = 0; | |
234 | } | |
235 | ||
236 | ulong get_timer_masked (void) | |
237 | { | |
238 | ulong now = READ_TIMER; | |
239 | ||
240 | if (lastdec >= now) { | |
241 | /* normal mode */ | |
242 | timestamp += lastdec - now; | |
243 | } else { | |
244 | /* we have an overflow ... */ | |
245 | timestamp += lastdec + TIMER_LOAD_VAL - now; | |
246 | } | |
247 | lastdec = now; | |
248 | ||
249 | return timestamp; | |
250 | } | |
251 | ||
252 | void udelay_masked (unsigned long usec) | |
253 | { | |
254 | ulong tmo; | |
255 | ||
256 | tmo = usec / 1000; | |
257 | tmo *= CFG_HZ; | |
258 | tmo /= 1000; | |
259 | ||
260 | reset_timer_masked (); | |
261 | ||
262 | while (get_timer_masked () < tmo) | |
263 | /*NOP*/; | |
264 | } |