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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Alex Zuepke <azu@sysgo.de> | |
9 | * | |
10 | * (C) Copyright 2002 | |
11 | * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> | |
12 | * | |
13 | * See file CREDITS for list of people who contributed to this | |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | */ | |
31 | ||
32 | #include <common.h> | |
33 | #include <arm920t.h> | |
34 | #if defined(CONFIG_S3C2400) | |
35 | #include <s3c2400.h> | |
36 | #elif defined(CONFIG_S3C2410) | |
37 | #include <s3c2410.h> | |
38 | #endif | |
39 | ||
40 | #include <asm/proc-armv/ptrace.h> | |
41 | ||
42 | extern void reset_cpu(ulong addr); | |
43 | int timer_load_val = 0; | |
44 | ||
45 | /* macro to read the 16 bit timer */ | |
48b42616 WD |
46 | static inline ulong READ_TIMER(void) |
47 | { | |
48 | S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); | |
49 | ||
50 | return (timers->TCNTO4 & 0xffff); | |
51 | } | |
c609719b WD |
52 | |
53 | #ifdef CONFIG_USE_IRQ | |
54 | /* enable IRQ interrupts */ | |
55 | void enable_interrupts (void) | |
56 | { | |
57 | unsigned long temp; | |
58 | __asm__ __volatile__("mrs %0, cpsr\n" | |
59 | "bic %0, %0, #0x80\n" | |
60 | "msr cpsr_c, %0" | |
61 | : "=r" (temp) | |
62 | : | |
63 | : "memory"); | |
64 | } | |
65 | ||
66 | ||
67 | /* | |
68 | * disable IRQ/FIQ interrupts | |
69 | * returns true if interrupts had been enabled before we disabled them | |
70 | */ | |
71 | int disable_interrupts (void) | |
72 | { | |
73 | unsigned long old,temp; | |
74 | __asm__ __volatile__("mrs %0, cpsr\n" | |
75 | "orr %1, %0, #0xc0\n" | |
76 | "msr cpsr_c, %1" | |
77 | : "=r" (old), "=r" (temp) | |
78 | : | |
79 | : "memory"); | |
80 | return (old & 0x80) == 0; | |
81 | } | |
82 | #else | |
83 | void enable_interrupts (void) | |
84 | { | |
85 | return; | |
86 | } | |
87 | int disable_interrupts (void) | |
88 | { | |
89 | return 0; | |
90 | } | |
91 | #endif | |
92 | ||
93 | ||
c609719b WD |
94 | void bad_mode (void) |
95 | { | |
96 | panic ("Resetting CPU ...\n"); | |
97 | reset_cpu (0); | |
98 | } | |
99 | ||
100 | void show_regs (struct pt_regs *regs) | |
101 | { | |
102 | unsigned long flags; | |
103 | const char *processor_modes[] = { | |
104 | "USER_26", "FIQ_26", "IRQ_26", "SVC_26", | |
105 | "UK4_26", "UK5_26", "UK6_26", "UK7_26", | |
106 | "UK8_26", "UK9_26", "UK10_26", "UK11_26", | |
107 | "UK12_26", "UK13_26", "UK14_26", "UK15_26", | |
108 | "USER_32", "FIQ_32", "IRQ_32", "SVC_32", | |
109 | "UK4_32", "UK5_32", "UK6_32", "ABT_32", | |
110 | "UK8_32", "UK9_32", "UK10_32", "UND_32", | |
111 | "UK12_32", "UK13_32", "UK14_32", "SYS_32", | |
112 | }; | |
113 | ||
114 | flags = condition_codes (regs); | |
115 | ||
116 | printf ("pc : [<%08lx>] lr : [<%08lx>]\n" | |
117 | "sp : %08lx ip : %08lx fp : %08lx\n", | |
118 | instruction_pointer (regs), | |
119 | regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); | |
120 | printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", | |
121 | regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); | |
122 | printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", | |
123 | regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); | |
124 | printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", | |
125 | regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); | |
126 | printf ("Flags: %c%c%c%c", | |
127 | flags & CC_N_BIT ? 'N' : 'n', | |
128 | flags & CC_Z_BIT ? 'Z' : 'z', | |
129 | flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); | |
130 | printf (" IRQs %s FIQs %s Mode %s%s\n", | |
131 | interrupts_enabled (regs) ? "on" : "off", | |
132 | fast_interrupts_enabled (regs) ? "on" : "off", | |
133 | processor_modes[processor_mode (regs)], | |
134 | thumb_mode (regs) ? " (T)" : ""); | |
135 | } | |
136 | ||
137 | void do_undefined_instruction (struct pt_regs *pt_regs) | |
138 | { | |
139 | printf ("undefined instruction\n"); | |
140 | show_regs (pt_regs); | |
141 | bad_mode (); | |
142 | } | |
143 | ||
144 | void do_software_interrupt (struct pt_regs *pt_regs) | |
145 | { | |
146 | printf ("software interrupt\n"); | |
147 | show_regs (pt_regs); | |
148 | bad_mode (); | |
149 | } | |
150 | ||
151 | void do_prefetch_abort (struct pt_regs *pt_regs) | |
152 | { | |
153 | printf ("prefetch abort\n"); | |
154 | show_regs (pt_regs); | |
155 | bad_mode (); | |
156 | } | |
157 | ||
158 | void do_data_abort (struct pt_regs *pt_regs) | |
159 | { | |
160 | printf ("data abort\n"); | |
161 | show_regs (pt_regs); | |
162 | bad_mode (); | |
163 | } | |
164 | ||
165 | void do_not_used (struct pt_regs *pt_regs) | |
166 | { | |
167 | printf ("not used\n"); | |
168 | show_regs (pt_regs); | |
169 | bad_mode (); | |
170 | } | |
171 | ||
172 | void do_fiq (struct pt_regs *pt_regs) | |
173 | { | |
174 | printf ("fast interrupt request\n"); | |
175 | show_regs (pt_regs); | |
176 | bad_mode (); | |
177 | } | |
178 | ||
179 | void do_irq (struct pt_regs *pt_regs) | |
180 | { | |
181 | printf ("interrupt request\n"); | |
182 | show_regs (pt_regs); | |
183 | bad_mode (); | |
184 | } | |
185 | ||
186 | static ulong timestamp; | |
187 | static ulong lastdec; | |
188 | ||
189 | int interrupt_init (void) | |
190 | { | |
48b42616 WD |
191 | S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); |
192 | ||
c609719b WD |
193 | /* use PWM Timer 4 because it has no output */ |
194 | /* prescaler for Timer 4 is 16 */ | |
48b42616 | 195 | timers->TCFG0 = 0x0f00; |
c609719b WD |
196 | if (timer_load_val == 0) |
197 | { | |
198 | /* | |
199 | * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 | |
200 | * (default) and prescaler = 16. Should be 10390 | |
201 | * @33.25MHz and 15625 @ 50 MHz | |
202 | */ | |
203 | timer_load_val = get_PCLK()/(2 * 16 * 100); | |
204 | } | |
205 | /* load value for 10 ms timeout */ | |
48b42616 | 206 | lastdec = timers->TCNTB4 = timer_load_val; |
c609719b | 207 | /* auto load, manual update of Timer 4 */ |
48b42616 | 208 | timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; |
c609719b | 209 | /* auto load, start Timer 4 */ |
48b42616 | 210 | timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; |
c609719b WD |
211 | timestamp = 0; |
212 | ||
213 | return (0); | |
214 | } | |
215 | ||
216 | /* | |
217 | * timer without interrupts | |
218 | */ | |
219 | ||
220 | void reset_timer (void) | |
221 | { | |
222 | reset_timer_masked (); | |
223 | } | |
224 | ||
225 | ulong get_timer (ulong base) | |
226 | { | |
227 | return get_timer_masked () - base; | |
228 | } | |
229 | ||
230 | void set_timer (ulong t) | |
231 | { | |
232 | timestamp = t; | |
233 | } | |
234 | ||
235 | void udelay (unsigned long usec) | |
236 | { | |
237 | ulong tmo; | |
238 | ||
239 | tmo = usec / 1000; | |
240 | tmo *= (timer_load_val * 100); | |
241 | tmo /= 1000; | |
242 | ||
243 | tmo += get_timer (0); | |
244 | ||
245 | while (get_timer_masked () < tmo) | |
246 | /*NOP*/; | |
247 | } | |
248 | ||
249 | void reset_timer_masked (void) | |
250 | { | |
251 | /* reset time */ | |
48b42616 | 252 | lastdec = READ_TIMER(); |
c609719b WD |
253 | timestamp = 0; |
254 | } | |
255 | ||
256 | ulong get_timer_masked (void) | |
257 | { | |
48b42616 | 258 | ulong now = READ_TIMER(); |
c609719b WD |
259 | |
260 | if (lastdec >= now) { | |
261 | /* normal mode */ | |
262 | timestamp += lastdec - now; | |
263 | } else { | |
264 | /* we have an overflow ... */ | |
265 | timestamp += lastdec + timer_load_val - now; | |
266 | } | |
267 | lastdec = now; | |
268 | ||
269 | return timestamp; | |
270 | } | |
271 | ||
272 | void udelay_masked (unsigned long usec) | |
273 | { | |
274 | ulong tmo; | |
275 | ||
276 | tmo = usec / 1000; | |
277 | tmo *= (timer_load_val * 100); | |
278 | tmo /= 1000; | |
279 | ||
280 | reset_timer_masked (); | |
281 | ||
282 | while (get_timer_masked () < tmo) | |
283 | /*NOP*/; | |
284 | } | |
285 | ||
286 | /* | |
287 | * This function is derived from PowerPC code (read timebase as long long). | |
288 | * On ARM it just returns the timer value. | |
289 | */ | |
290 | unsigned long long get_ticks(void) | |
291 | { | |
292 | return get_timer(0); | |
293 | } | |
294 | ||
295 | /* | |
296 | * This function is derived from PowerPC code (timebase clock frequency). | |
297 | * On ARM it returns the number of timer ticks per second. | |
298 | */ | |
299 | ulong get_tbclk (void) | |
300 | { | |
301 | ulong tbclk; | |
302 | ||
303 | #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) | |
304 | tbclk = timer_load_val * 100; | |
06d01dbe | 305 | #elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) |
c609719b | 306 | tbclk = CFG_HZ; |
06d01dbe WD |
307 | #else |
308 | # error "tbclk not configured" | |
c609719b WD |
309 | #endif |
310 | ||
311 | return tbclk; | |
312 | } |