[people/ms/u-boot.git] / cpu / arm_cortexa8 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>

extern omap3_sysinfo sysinfo;

extern u32 is_mem_sdr(void);

/******************************************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 *****************************************************************************/
static inline void delay(unsigned long loops)
{
	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
			  "bne 1b":"=r" (loops):"0"(loops));
}

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
	pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
	pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
	pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
	sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configrue non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: setup_auxcr()
 * Description: Write to AuxCR desired value using SMI.
 *              general use.
 *****************************************************************************/
void setup_auxcr()
{
	unsigned long i;
	volatile unsigned int j;
	/* Save r0, r12 and restore them after usage */
	__asm__ __volatile__("mov %0, r12":"=r"(j));
	__asm__ __volatile__("mov %0, r0":"=r"(i));

	/*
	 * GP Device ROM code API usage here
	 * r12 = AUXCR Write function and r0 value
	 */
	__asm__ __volatile__("mov r12, #0x3");
	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
	/* Enabling ASA */
	__asm__ __volatile__("orr r0, r0, #0x10");
	/* Enable L1NEON */
	__asm__ __volatile__("orr r0, r0, #1 << 5");
	/* SMI instruction to call ROM Code API */
	__asm__ __volatile__(".word 0xE1600070");
	__asm__ __volatile__("mov r0, %0":"=r"(i));
	__asm__ __volatile__("mov r12, %0":"=r"(j));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/*
	 * Right now flushing at low MPU speed.
	 * Need to move after clock init
	 */
	v7_flush_dcache_all(get_device_type());
#ifndef CONFIG_ICACHE_OFF
	icache_enable();
#endif

#ifdef CONFIG_L2_OFF
	l2cache_disable();
#else
	l2cache_enable();
#endif
	/*
	 * Writing to AuxCR in U-boot using SMI for GP DEV
	 * Currently SMI in Kernel on ES2 devices seems to have an issue
	 * Once that is resolved, we can postpone this config to kernel
	 */
	if (get_device_type() == GP_DEVICE)
		setup_auxcr();

	set_muxconf_regs();
	delay(100);

	prcm_init();

	per_clocks_enable();

	if (!in_sdram)
		sdrc_init();
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(watchdog_t *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Routine: dram_init
 * Description: sets uboots idea of sdram size
 *****************************************************************************/
int dram_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int size0 = 0, size1 = 0;

	/*
	 * If a second bank of DDR is attached to CS1 this is
	 * where it can be started.  Early init code will init
	 * memory on CS0.
	 */
	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
		do_sdrc_init(CS1, NOT_EARLY);
		make_cs1_contiguous();
	}

	size0 = get_sdr_cs_size(CS0);
	size1 = get_sdr_cs_size(CS1);

	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = size0;
	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
	gd->bd->bi_dram[1].size = size1;

	return 0;
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void raise(void)
{
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#ifdef CONFIG_NAND_OMAP_GPMC
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);

#endif /* CONFIG_NAND_OMAP_GPMC */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/sys_proto.h>
	38	#include <asm/arch/mem.h>
	39
	40	extern omap3_sysinfo sysinfo;
	41
6a6b62e3 SP	42	extern u32 is_mem_sdr(void);
6a6b62e3 SP	43
91eee546 DB	44	/******************************************************************************
	45	* Routine: delay
	46	* Description: spinning delay to use before udelay works
	47	*****************************************************************************/
	48	static inline void delay(unsigned long loops)
	49	{
	50	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
	51	"bne 1b":"=r" (loops):"0"(loops));
	52	}
	53
	54	/******************************************************************************
	55	* Routine: secure_unlock
	56	* Description: Setup security registers for access
	57	* (GP Device only)
	58	*****************************************************************************/
	59	void secure_unlock_mem(void)
	60	{
	61	pm_t pm_rt_ape_base = (pm_t )PM_RT_APE_BASE_ADDR_ARM;
	62	pm_t pm_gpmc_base = (pm_t )PM_GPMC_BASE_ADDR_ARM;
	63	pm_t pm_ocm_ram_base = (pm_t )PM_OCM_RAM_BASE_ADDR_ARM;
	64	pm_t pm_iva2_base = (pm_t )PM_IVA2_BASE_ADDR_ARM;
	65	sms_t sms_base = (sms_t )OMAP34XX_SMS_BASE;
	66
	67	/* Protection Module Register Target APE (PM_RT) */
	68	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	69	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	70	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	71	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	72
	73	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	74	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	75	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	76
	77	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	78	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	79	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	80	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	81
	82	/* IVA Changes */
	83	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	84	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	85	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	86
	87	/* SDRC region 0 public */
	88	writel(UNLOCK_1, &sms_base->rg_att0);
	89	}
	90
	91	/******************************************************************************
	92	* Routine: secureworld_exit()
	93	* Description: If chip is EMU and boot type is external
	94	* configure secure registers and exit secure world
	95	* general use.
	96	*****************************************************************************/
	97	void secureworld_exit()
	98	{
	99	unsigned long i;
	100
	101	/* configrue non-secure access control register */
	102	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	103	/* enabling co-processor CP10 and CP11 accesses in NS world */
	104	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	105	/*
	106	* allow allocation of locked TLBs and L2 lines in NS world
	107	* allow use of PLE registers in NS world also
108	*/
109	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
110	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
111
112	/* Enable ASA in ACR register */
113	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
114	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
115	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
116
117	/* Exiting secure world */
118	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
119	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
120	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
121	}
122
123	/******************************************************************************
124	* Routine: setup_auxcr()
125	* Description: Write to AuxCR desired value using SMI.
126	* general use.
127	*****************************************************************************/
128	void setup_auxcr()
129	{
130	unsigned long i;
131	volatile unsigned int j;
132	/* Save r0, r12 and restore them after usage */
133	__asm__ __volatile__("mov %0, r12":"=r"(j));
134	__asm__ __volatile__("mov %0, r0":"=r"(i));
135
136	/*
137	* GP Device ROM code API usage here
138	* r12 = AUXCR Write function and r0 value
139	*/
140	__asm__ __volatile__("mov r12, #0x3");
141	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
142	/* Enabling ASA */
143	__asm__ __volatile__("orr r0, r0, #0x10");
144	/* Enable L1NEON */
145	__asm__ __volatile__("orr r0, r0, #1 << 5");
146	/* SMI instruction to call ROM Code API */
147	__asm__ __volatile__(".word 0xE1600070");
148	__asm__ __volatile__("mov r0, %0":"=r"(i));
149	__asm__ __volatile__("mov r12, %0":"=r"(j));
150	}
151
152	/******************************************************************************
153	* Routine: try_unlock_sram()
154	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
155	* general use.
156	*****************************************************************************/
157	void try_unlock_memory()
158	{
159	int mode;
160	int in_sdram = is_running_in_sdram();
161
162	/*
163	* if GP device unlock device SRAM for general use
164	* secure code breaks for Secure/Emulation device - HS/E/T
165	*/
166	mode = get_device_type();
167	if (mode == GP_DEVICE)
168	secure_unlock_mem();
169
170	/*
171	* If device is EMU and boot is XIP external booting
172	* Unlock firewalls and disable L2 and put chip
173	* out of secure world
174	*
175	* Assuming memories are unlocked by the demon who put us in SDRAM
176	*/
177	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
178	&& (!in_sdram)) {
179	secure_unlock_mem();
180	secureworld_exit();
181	}
182
183	return;
184	}
185
186	/******************************************************************************
187	* Routine: s_init
188	* Description: Does early system init of muxing and clocks.
189	* - Called path is with SRAM stack.
190	*****************************************************************************/
191	void s_init(void)
192	{
193	int in_sdram = is_running_in_sdram();
194
195	watchdog_init();
196
197	try_unlock_memory();
198
199	/*
200	* Right now flushing at low MPU speed.
201	* Need to move after clock init
202	*/
203	v7_flush_dcache_all(get_device_type());
204	#ifndef CONFIG_ICACHE_OFF
205	icache_enable();
206	#endif
207
208	#ifdef CONFIG_L2_OFF
209	l2cache_disable();
210	#else
211	l2cache_enable();
212	#endif
213	/*
214	* Writing to AuxCR in U-boot using SMI for GP DEV
215	* Currently SMI in Kernel on ES2 devices seems to have an issue
216	* Once that is resolved, we can postpone this config to kernel
217	*/
218	if (get_device_type() == GP_DEVICE)
219	setup_auxcr();
220
221	set_muxconf_regs();
222	delay(100);
223
224	prcm_init();
225
226	per_clocks_enable();
227
228	if (!in_sdram)
229	sdrc_init();
230	}
231
232	/******************************************************************************
233	* Routine: wait_for_command_complete
234	* Description: Wait for posting to finish on watchdog
235	*****************************************************************************/
236	void wait_for_command_complete(watchdog_t *wd_base)
237	{
238	int pending = 1;
239	do {
240	pending = readl(&wd_base->wwps);
241	} while (pending);
242	}
243
244	/******************************************************************************
245	* Routine: watchdog_init
246	* Description: Shut down watch dogs
247	*****************************************************************************/
248	void watchdog_init(void)
249	{
250	watchdog_t wd2_base = (watchdog_t )WD2_BASE;
251	prcm_t prcm_base = (prcm_t )PRCM_BASE;
252
253	/*
254	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
255	* either taken care of by ROM (HS/EMU) or not accessible (GP).
256	* We need to take care of WD2-MPU or take a PRCM reset. WD3
257	* should not be running and does not generate a PRCM reset.
258	*/
259
260	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
261	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
262	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
263
264	writel(WD_UNLOCK1, &wd2_base->wspr);
265	wait_for_command_complete(wd2_base);
266	writel(WD_UNLOCK2, &wd2_base->wspr);
267	}
268
269	/******************************************************************************
270	* Routine: dram_init
271	* Description: sets uboots idea of sdram size
272	*****************************************************************************/
273	int dram_init(void)
274	{
275	DECLARE_GLOBAL_DATA_PTR;
276	unsigned int size0 = 0, size1 = 0;
91eee546 DB	277
	278	/*
	279	* If a second bank of DDR is attached to CS1 this is
	280	* where it can be started. Early init code will init
	281	* memory on CS0.
	282	*/
	283	if ((sysinfo.mtype == DDR_COMBO) \|\| (sysinfo.mtype == DDR_STACKED)) {
	284	do_sdrc_init(CS1, NOT_EARLY);
	285	make_cs1_contiguous();
	286	}
	287
	288	size0 = get_sdr_cs_size(CS0);
	289	size1 = get_sdr_cs_size(CS1);
	290
	291	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	292	gd->bd->bi_dram[0].size = size0;
	293	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
	294	gd->bd->bi_dram[1].size = size1;
	295
	296	return 0;
	297	}
	298
	299	/******************************************************************************
	300	* Dummy function to handle errors for EABI incompatibility
	301	*****************************************************************************/
	302	void raise(void)
	303	{
	304	}
	305
	306	/******************************************************************************
	307	* Dummy function to handle errors for EABI incompatibility
	308	*****************************************************************************/
	309	void abort(void)
	310	{
	311	}
	312
	313	#ifdef CONFIG_NAND_OMAP_GPMC
	314	/******************************************************************************
	315	* OMAP3 specific command to switch between NAND HW and SW ecc
	316	*****************************************************************************/
	317	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	318	{
	319	if (argc != 2)
	320	goto usage;
	321	if (strncmp(argv[1], "hw", 2) == 0)
	322	omap_nand_switch_ecc(1);
	323	else if (strncmp(argv[1], "sw", 2) == 0)
	324	omap_nand_switch_ecc(0);
	325	else
	326	goto usage;
	327
	328	return 0;
	329
	330	usage:
36003268	331	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	332	return 1;
	333	}
	334
	335	U_BOOT_CMD(
	336	nandecc, 2, 1, do_switch_ecc,
	337	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
a89c33db WD	338	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
a89c33db WD	339	);
91eee546 DB	340
91eee546 DB	341	#endif /* CONFIG_NAND_OMAP_GPMC */
6a6b62e3 SP	342
	343	#ifdef CONFIG_DISPLAY_BOARDINFO
	344	/**
	345	* Print board information
	346	*/
	347	int checkboard (void)
	348	{
	349	char *mem_s ;
	350
	351	if (is_mem_sdr())
	352	mem_s = "mSDR";
	353	else
	354	mem_s = "LPDDR";
	355
	356	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	357	sysinfo.nand_string);
	358
	359	return 0;
	360	}
	361	#endif /* CONFIG_DISPLAY_BOARDINFO */