[people/ms/u-boot.git] / cpu / arm_cortexa8 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>

extern omap3_sysinfo sysinfo;

extern u32 is_mem_sdr(void);

/******************************************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 *****************************************************************************/
static inline void delay(unsigned long loops)
{
	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
			  "bne 1b":"=r" (loops):"0"(loops));
}

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configrue non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: setup_auxcr()
 * Description: Write to AuxCR desired value using SMI.
 *              general use.
 *****************************************************************************/
void setup_auxcr()
{
	unsigned long i;
	volatile unsigned int j;
	/* Save r0, r12 and restore them after usage */
	__asm__ __volatile__("mov %0, r12":"=r"(j));
	__asm__ __volatile__("mov %0, r0":"=r"(i));

	/*
	 * GP Device ROM code API usage here
	 * r12 = AUXCR Write function and r0 value
	 */
	__asm__ __volatile__("mov r12, #0x3");
	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
	/* Enabling ASA */
	__asm__ __volatile__("orr r0, r0, #0x10");
	/* Enable L1NEON */
	__asm__ __volatile__("orr r0, r0, #1 << 5");
	/* SMI instruction to call ROM Code API */
	__asm__ __volatile__(".word 0xE1600070");
	__asm__ __volatile__("mov r0, %0":"=r"(i));
	__asm__ __volatile__("mov r12, %0":"=r"(j));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/*
	 * Right now flushing at low MPU speed.
	 * Need to move after clock init
	 */
	v7_flush_dcache_all(get_device_type());
#ifndef CONFIG_ICACHE_OFF
	icache_enable();
#endif

#ifdef CONFIG_L2_OFF
	l2_cache_disable();
#else
	l2_cache_enable();
#endif
	/*
	 * Writing to AuxCR in U-boot using SMI for GP DEV
	 * Currently SMI in Kernel on ES2 devices seems to have an issue
	 * Once that is resolved, we can postpone this config to kernel
	 */
	if (get_device_type() == GP_DEVICE)
		setup_auxcr();

	set_muxconf_regs();
	delay(100);

	prcm_init();

	per_clocks_enable();

	if (!in_sdram)
		sdrc_init();
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Routine: dram_init
 * Description: sets uboots idea of sdram size
 *****************************************************************************/
int dram_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int size0 = 0, size1 = 0;

	/*
	 * If a second bank of DDR is attached to CS1 this is
	 * where it can be started.  Early init code will init
	 * memory on CS0.
	 */
	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
		do_sdrc_init(CS1, NOT_EARLY);
		make_cs1_contiguous();
	}

	size0 = get_sdr_cs_size(CS0);
	size1 = get_sdr_cs_size(CS1);

	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = size0;
	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
	gd->bd->bi_dram[1].size = size1;

	return 0;
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#ifdef CONFIG_NAND_OMAP_GPMC
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);

#endif /* CONFIG_NAND_OMAP_GPMC */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/sys_proto.h>
	38	#include <asm/arch/mem.h>
06e758e7	39	#include <asm/cache.h>
91eee546 DB	40
	41	extern omap3_sysinfo sysinfo;
	42
6a6b62e3 SP	43	extern u32 is_mem_sdr(void);
6a6b62e3 SP	44
91eee546 DB	45	/******************************************************************************
	46	* Routine: delay
	47	* Description: spinning delay to use before udelay works
	48	*****************************************************************************/
	49	static inline void delay(unsigned long loops)
	50	{
	51	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
	52	"bne 1b":"=r" (loops):"0"(loops));
	53	}
	54
	55	/******************************************************************************
	56	* Routine: secure_unlock
	57	* Description: Setup security registers for access
	58	* (GP Device only)
	59	*****************************************************************************/
	60	void secure_unlock_mem(void)
	61	{
97a099ea DB	62	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	63	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	64	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	65	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	66	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	67
	68	/* Protection Module Register Target APE (PM_RT) */
	69	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	70	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	71	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	72	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	73
	74	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	75	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	76	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	77
	78	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	79	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	80	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	81	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	82
	83	/* IVA Changes */
	84	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	85	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	86	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	87
	88	/* SDRC region 0 public */
	89	writel(UNLOCK_1, &sms_base->rg_att0);
	90	}
	91
	92	/******************************************************************************
	93	* Routine: secureworld_exit()
	94	* Description: If chip is EMU and boot type is external
	95	* configure secure registers and exit secure world
	96	* general use.
	97	*****************************************************************************/
	98	void secureworld_exit()
	99	{
	100	unsigned long i;
	101
	102	/* configrue non-secure access control register */
	103	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	104	/* enabling co-processor CP10 and CP11 accesses in NS world */
	105	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	106	/*
	107	* allow allocation of locked TLBs and L2 lines in NS world
	108	* allow use of PLE registers in NS world also
	109	*/
	110	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	111	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	112
	113	/* Enable ASA in ACR register */
	114	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	115	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	116	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	117
	118	/* Exiting secure world */
	119	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	120	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	121	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	122	}
	123
	124	/******************************************************************************
	125	* Routine: setup_auxcr()
	126	* Description: Write to AuxCR desired value using SMI.
	127	* general use.
	128	*****************************************************************************/
	129	void setup_auxcr()
	130	{
131	unsigned long i;
132	volatile unsigned int j;
133	/* Save r0, r12 and restore them after usage */
134	__asm__ __volatile__("mov %0, r12":"=r"(j));
135	__asm__ __volatile__("mov %0, r0":"=r"(i));
136
137	/*
138	* GP Device ROM code API usage here
139	* r12 = AUXCR Write function and r0 value
140	*/
141	__asm__ __volatile__("mov r12, #0x3");
142	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
143	/* Enabling ASA */
144	__asm__ __volatile__("orr r0, r0, #0x10");
145	/* Enable L1NEON */
146	__asm__ __volatile__("orr r0, r0, #1 << 5");
147	/* SMI instruction to call ROM Code API */
148	__asm__ __volatile__(".word 0xE1600070");
149	__asm__ __volatile__("mov r0, %0":"=r"(i));
150	__asm__ __volatile__("mov r12, %0":"=r"(j));
151	}
152
153	/******************************************************************************
154	* Routine: try_unlock_sram()
155	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
156	* general use.
157	*****************************************************************************/
158	void try_unlock_memory()
159	{
160	int mode;
161	int in_sdram = is_running_in_sdram();
162
163	/*
164	* if GP device unlock device SRAM for general use
165	* secure code breaks for Secure/Emulation device - HS/E/T
166	*/
167	mode = get_device_type();
168	if (mode == GP_DEVICE)
169	secure_unlock_mem();
170
171	/*
172	* If device is EMU and boot is XIP external booting
173	* Unlock firewalls and disable L2 and put chip
174	* out of secure world
175	*
176	* Assuming memories are unlocked by the demon who put us in SDRAM
177	*/
178	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
179	&& (!in_sdram)) {
180	secure_unlock_mem();
181	secureworld_exit();
182	}
183
184	return;
185	}
186
187	/******************************************************************************
188	* Routine: s_init
189	* Description: Does early system init of muxing and clocks.
190	* - Called path is with SRAM stack.
191	*****************************************************************************/
192	void s_init(void)
193	{
194	int in_sdram = is_running_in_sdram();
195
196	watchdog_init();
197
198	try_unlock_memory();
199
200	/*
201	* Right now flushing at low MPU speed.
202	* Need to move after clock init
203	*/
204	v7_flush_dcache_all(get_device_type());
205	#ifndef CONFIG_ICACHE_OFF
206	icache_enable();
207	#endif
208
209	#ifdef CONFIG_L2_OFF
06e758e7	210	l2_cache_disable();
91eee546	211	#else
06e758e7	212	l2_cache_enable();
91eee546 DB	213	#endif
	214	/*
	215	* Writing to AuxCR in U-boot using SMI for GP DEV
	216	* Currently SMI in Kernel on ES2 devices seems to have an issue
	217	* Once that is resolved, we can postpone this config to kernel
	218	*/
	219	if (get_device_type() == GP_DEVICE)
	220	setup_auxcr();
	221
	222	set_muxconf_regs();
	223	delay(100);
	224
	225	prcm_init();
	226
	227	per_clocks_enable();
	228
	229	if (!in_sdram)
	230	sdrc_init();
	231	}
	232
	233	/******************************************************************************
	234	* Routine: wait_for_command_complete
	235	* Description: Wait for posting to finish on watchdog
	236	*****************************************************************************/
97a099ea	237	void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	238	{
	239	int pending = 1;
	240	do {
	241	pending = readl(&wd_base->wwps);
	242	} while (pending);
	243	}
	244
	245	/******************************************************************************
	246	* Routine: watchdog_init
	247	* Description: Shut down watch dogs
	248	*****************************************************************************/
	249	void watchdog_init(void)
	250	{
97a099ea DB	251	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	252	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	253
	254	/*
	255	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	256	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	257	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	258	* should not be running and does not generate a PRCM reset.
	259	*/
	260
	261	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	262	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	263	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	264
	265	writel(WD_UNLOCK1, &wd2_base->wspr);
	266	wait_for_command_complete(wd2_base);
	267	writel(WD_UNLOCK2, &wd2_base->wspr);
	268	}
	269
	270	/******************************************************************************
	271	* Routine: dram_init
	272	* Description: sets uboots idea of sdram size
	273	*****************************************************************************/
	274	int dram_init(void)
	275	{
	276	DECLARE_GLOBAL_DATA_PTR;
	277	unsigned int size0 = 0, size1 = 0;
91eee546 DB	278
	279	/*
	280	* If a second bank of DDR is attached to CS1 this is
	281	* where it can be started. Early init code will init
	282	* memory on CS0.
	283	*/
	284	if ((sysinfo.mtype == DDR_COMBO) \|\| (sysinfo.mtype == DDR_STACKED)) {
	285	do_sdrc_init(CS1, NOT_EARLY);
	286	make_cs1_contiguous();
	287	}
	288
	289	size0 = get_sdr_cs_size(CS0);
	290	size1 = get_sdr_cs_size(CS1);
	291
	292	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	293	gd->bd->bi_dram[0].size = size0;
	294	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
	295	gd->bd->bi_dram[1].size = size1;
	296
	297	return 0;
	298	}
	299
91eee546 DB	300	/******************************************************************************
	301	* Dummy function to handle errors for EABI incompatibility
	302	*****************************************************************************/
	303	void abort(void)
	304	{
	305	}
	306
	307	#ifdef CONFIG_NAND_OMAP_GPMC
	308	/******************************************************************************
	309	* OMAP3 specific command to switch between NAND HW and SW ecc
	310	*****************************************************************************/
	311	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	312	{
	313	if (argc != 2)
	314	goto usage;
	315	if (strncmp(argv[1], "hw", 2) == 0)
	316	omap_nand_switch_ecc(1);
	317	else if (strncmp(argv[1], "sw", 2) == 0)
	318	omap_nand_switch_ecc(0);
	319	else
	320	goto usage;
	321
	322	return 0;
	323
	324	usage:
36003268	325	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	326	return 1;
	327	}
	328
	329	U_BOOT_CMD(
	330	nandecc, 2, 1, do_switch_ecc,
	331	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
a89c33db WD	332	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
a89c33db WD	333	);
91eee546 DB	334
91eee546 DB	335	#endif /* CONFIG_NAND_OMAP_GPMC */
6a6b62e3 SP	336
	337	#ifdef CONFIG_DISPLAY_BOARDINFO
	338	/**
	339	* Print board information
	340	*/
	341	int checkboard (void)
	342	{
	343	char *mem_s ;
	344
	345	if (is_mem_sdr())
	346	mem_s = "mSDR";
	347	else
	348	mem_s = "LPDDR";
	349
	350	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	351	sysinfo.nand_string);
	352
	353	return 0;
	354	}
	355	#endif /* CONFIG_DISPLAY_BOARDINFO */