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91eee546 DB |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments | |
4 | * | |
5 | * Richard Woodruff <r-woodruff2@ti.com> | |
6 | * Syed Moahmmed Khasim <khasim@ti.com> | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
10 | * Marius Groeger <mgroeger@sysgo.de> | |
11 | * Alex Zuepke <azu@sysgo.de> | |
12 | * | |
13 | * (C) Copyright 2002 | |
792a09eb | 14 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
91eee546 DB |
15 | * |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #include <common.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/proc-armv/ptrace.h> | |
38 | ||
91eee546 DB |
39 | #ifdef CONFIG_USE_IRQ |
40 | /* enable IRQ interrupts */ | |
41 | void enable_interrupts(void) | |
42 | { | |
43 | unsigned long temp; | |
44 | __asm__ __volatile__("mrs %0, cpsr\n" | |
45 | "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp) | |
46 | ::"memory"); | |
47 | } | |
48 | ||
49 | /* | |
50 | * disable IRQ/FIQ interrupts | |
51 | * returns true if interrupts had been enabled before we disabled them | |
52 | */ | |
53 | int disable_interrupts(void) | |
54 | { | |
55 | unsigned long old, temp; | |
56 | __asm__ __volatile__("mrs %0, cpsr\n" | |
57 | "orr %1, %0, #0xc0\n" | |
58 | "msr cpsr_c, %1":"=r"(old), "=r"(temp) | |
59 | ::"memory"); | |
60 | return (old & 0x80) == 0; | |
61 | } | |
62 | #else | |
63 | void enable_interrupts(void) | |
64 | { | |
65 | return; | |
66 | } | |
67 | int disable_interrupts(void) | |
68 | { | |
69 | return 0; | |
70 | } | |
71 | #endif | |
72 | ||
73 | void bad_mode(void) | |
74 | { | |
75 | panic("Resetting CPU ...\n"); | |
76 | reset_cpu(0); | |
77 | } | |
78 | ||
79 | void show_regs(struct pt_regs *regs) | |
80 | { | |
81 | unsigned long flags; | |
82 | const char *processor_modes[] = { | |
83 | "USER_26", "FIQ_26", "IRQ_26", "SVC_26", | |
84 | "UK4_26", "UK5_26", "UK6_26", "UK7_26", | |
85 | "UK8_26", "UK9_26", "UK10_26", "UK11_26", | |
86 | "UK12_26", "UK13_26", "UK14_26", "UK15_26", | |
87 | "USER_32", "FIQ_32", "IRQ_32", "SVC_32", | |
88 | "UK4_32", "UK5_32", "UK6_32", "ABT_32", | |
89 | "UK8_32", "UK9_32", "UK10_32", "UND_32", | |
90 | "UK12_32", "UK13_32", "UK14_32", "SYS_32", | |
91 | }; | |
92 | ||
93 | flags = condition_codes(regs); | |
94 | ||
95 | printf("pc : [<%08lx>] lr : [<%08lx>]\n" | |
96 | "sp : %08lx ip : %08lx fp : %08lx\n", | |
97 | instruction_pointer(regs), | |
98 | regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); | |
99 | printf("r10: %08lx r9 : %08lx r8 : %08lx\n", | |
100 | regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); | |
101 | printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", | |
102 | regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); | |
103 | printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", | |
104 | regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); | |
105 | printf("Flags: %c%c%c%c", | |
106 | flags & CC_N_BIT ? 'N' : 'n', | |
107 | flags & CC_Z_BIT ? 'Z' : 'z', | |
108 | flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); | |
109 | printf(" IRQs %s FIQs %s Mode %s%s\n", | |
110 | interrupts_enabled(regs) ? "on" : "off", | |
111 | fast_interrupts_enabled(regs) ? "on" : "off", | |
112 | processor_modes[processor_mode(regs)], | |
113 | thumb_mode(regs) ? " (T)" : ""); | |
114 | } | |
115 | ||
116 | void do_undefined_instruction(struct pt_regs *pt_regs) | |
117 | { | |
118 | printf("undefined instruction\n"); | |
119 | show_regs(pt_regs); | |
120 | bad_mode(); | |
121 | } | |
122 | ||
123 | void do_software_interrupt(struct pt_regs *pt_regs) | |
124 | { | |
125 | printf("software interrupt\n"); | |
126 | show_regs(pt_regs); | |
127 | bad_mode(); | |
128 | } | |
129 | ||
130 | void do_prefetch_abort(struct pt_regs *pt_regs) | |
131 | { | |
132 | printf("prefetch abort\n"); | |
133 | show_regs(pt_regs); | |
134 | bad_mode(); | |
135 | } | |
136 | ||
137 | void do_data_abort(struct pt_regs *pt_regs) | |
138 | { | |
139 | printf("data abort\n"); | |
140 | show_regs(pt_regs); | |
141 | bad_mode(); | |
142 | } | |
143 | ||
144 | void do_not_used(struct pt_regs *pt_regs) | |
145 | { | |
146 | printf("not used\n"); | |
147 | show_regs(pt_regs); | |
148 | bad_mode(); | |
149 | } | |
150 | ||
151 | void do_fiq(struct pt_regs *pt_regs) | |
152 | { | |
153 | printf("fast interrupt request\n"); | |
154 | show_regs(pt_regs); | |
155 | bad_mode(); | |
156 | } | |
157 | ||
158 | void do_irq(struct pt_regs *pt_regs) | |
159 | { | |
160 | printf("interrupt request\n"); | |
161 | show_regs(pt_regs); | |
162 | bad_mode(); | |
163 | } | |
164 | ||
165 | ||
166 | static ulong timestamp; | |
167 | static ulong lastinc; | |
168 | static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; | |
169 | ||
d3a513c2 MP |
170 | /* |
171 | * Nothing really to do with interrupts, just starts up a counter. | |
172 | * We run the counter with 13MHz, divided by 8, resulting in timer | |
173 | * frequency of 1.625MHz. With 32bit counter register, counter | |
174 | * overflows in ~44min | |
175 | */ | |
176 | ||
177 | /* 13MHz / 8 = 1.625MHz */ | |
178 | #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) | |
179 | #define TIMER_LOAD_VAL 0xffffffff | |
180 | ||
91eee546 DB |
181 | int interrupt_init(void) |
182 | { | |
183 | /* start the counter ticking up, reload value on overflow */ | |
184 | writel(TIMER_LOAD_VAL, &timer_base->tldr); | |
185 | /* enable timer */ | |
81472d89 | 186 | writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, |
91eee546 DB |
187 | &timer_base->tclr); |
188 | ||
189 | reset_timer_masked(); /* init the timestamp and lastinc value */ | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | /* | |
195 | * timer without interrupts | |
196 | */ | |
197 | void reset_timer(void) | |
198 | { | |
199 | reset_timer_masked(); | |
200 | } | |
201 | ||
202 | ulong get_timer(ulong base) | |
203 | { | |
204 | return get_timer_masked() - base; | |
205 | } | |
206 | ||
207 | void set_timer(ulong t) | |
208 | { | |
209 | timestamp = t; | |
210 | } | |
211 | ||
d3a513c2 | 212 | /* delay x useconds */ |
91eee546 DB |
213 | void udelay(unsigned long usec) |
214 | { | |
d3a513c2 MP |
215 | long tmo = usec * (TIMER_CLOCK / 1000) / 1000; |
216 | unsigned long now, last = readl(&timer_base->tcrr); | |
217 | ||
218 | while (tmo > 0) { | |
219 | now = readl(&timer_base->tcrr); | |
220 | if (last > now) /* count up timer overflow */ | |
221 | tmo -= TIMER_LOAD_VAL - last + now; | |
222 | else | |
223 | tmo -= now - last; | |
224 | last = now; | |
91eee546 | 225 | } |
91eee546 DB |
226 | } |
227 | ||
228 | void reset_timer_masked(void) | |
229 | { | |
230 | /* reset time, capture current incrementer value time */ | |
d3a513c2 | 231 | lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); |
91eee546 DB |
232 | timestamp = 0; /* start "advancing" time stamp from 0 */ |
233 | } | |
234 | ||
235 | ulong get_timer_masked(void) | |
236 | { | |
d3a513c2 MP |
237 | /* current tick value */ |
238 | ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); | |
91eee546 DB |
239 | |
240 | if (now >= lastinc) /* normal mode (non roll) */ | |
241 | /* move stamp fordward with absoulte diff ticks */ | |
242 | timestamp += (now - lastinc); | |
243 | else /* we have rollover of incrementer */ | |
d3a513c2 MP |
244 | timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) |
245 | - lastinc) + now; | |
91eee546 DB |
246 | lastinc = now; |
247 | return timestamp; | |
248 | } | |
249 | ||
91eee546 DB |
250 | /* |
251 | * This function is derived from PowerPC code (read timebase as long long). | |
252 | * On ARM it just returns the timer value. | |
253 | */ | |
254 | unsigned long long get_ticks(void) | |
255 | { | |
256 | return get_timer(0); | |
257 | } | |
258 | ||
259 | /* | |
260 | * This function is derived from PowerPC code (timebase clock frequency). | |
261 | * On ARM it returns the number of timer ticks per second. | |
262 | */ | |
263 | ulong get_tbclk(void) | |
264 | { | |
d3a513c2 | 265 | return CONFIG_SYS_HZ; |
91eee546 | 266 | } |