[people/ms/u-boot.git] / cpu / ixp / cpu.c

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Alex Zuepke <azu@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 */

#include <common.h>
#include <command.h>
#include <asm/arch/ixp425.h>

#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif

int cpu_init (void)
{
	/*
	 * setup up stacks if necessary
	 */
#ifdef CONFIG_USE_IRQ
	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif

	pci_init();
	return 0;
}

int cleanup_before_linux (void)
{
	/*
	 * this function is called just before we call linux
	 * it prepares the processor for linux
	 *
	 * just disable everything that can disturb booting linux
	 */

	unsigned long i;

	disable_interrupts ();

	/* turn off I-cache */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	i &= ~0x1000;
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

	/* flush I-cache */
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));

	return (0);
}

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	printf ("resetting ...\n");

	udelay (50000);				/* wait 50 ms */
	disable_interrupts ();
	reset_cpu (0);

	/*NOTREACHED*/
	return (0);
}

/* taken from blob */
void icache_enable (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* set i-cache */
	i |= 0x1000;

	/* write back to control register */
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}

void icache_disable (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* clear i-cache */
	i &= ~0x1000;

	/* write back to control register */
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

	/* flush i-cache */
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}

int icache_status (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* return bit */
	return (i & 0x1000);
}

/* we will never enable dcache, because we have to setup MMU first */
void dcache_enable (void)
{
	return;
}

void dcache_disable (void)
{
	return;
}

int dcache_status (void)
{
	return 0;					/* always off */
}

/* FIXME */
/*
void pci_init(void)
{
	return;
}
*/
Commit	Line	Data
2d5b561e WD	1	/*
	2	* (C) Copyright 2002
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	*
	6	* (C) Copyright 2002
	7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	8	* Alex Zuepke <azu@sysgo.de>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/*
	30	* CPU specific code
	31	*/
	32
	33	#include <common.h>
	34	#include <command.h>
	35	#include <asm/arch/ixp425.h>
	36
d87080b7 WD	37	#ifdef CONFIG_USE_IRQ
	38	DECLARE_GLOBAL_DATA_PTR;
	39	#endif
	40
2d5b561e WD	41	int cpu_init (void)
	42	{
	43	/*
f6e20fc6	44	* setup up stacks if necessary
2d5b561e	45	*/
2d5b561e	46	#ifdef CONFIG_USE_IRQ
f6e20fc6 WD	47	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
f6e20fc6 WD	48	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
2d5b561e	49	#endif
f6e20fc6 WD	50
f6e20fc6 WD	51	pci_init();
2d5b561e WD	52	return 0;
	53	}
	54
	55	int cleanup_before_linux (void)
	56	{
	57	/*
	58	* this function is called just before we call linux
	59	* it prepares the processor for linux
	60	*
	61	* just disable everything that can disturb booting linux
	62	*/
	63
	64	unsigned long i;
	65
	66	disable_interrupts ();
	67
	68	/* turn off I-cache */
	69	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	70	i &= ~0x1000;
	71	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	72
	73	/* flush I-cache */
	74	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
	75
	76	return (0);
	77	}
	78
	79	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	80	{
f6e20fc6	81	printf ("resetting ...\n");
2d5b561e WD	82
	83	udelay (50000); /* wait 50 ms */
	84	disable_interrupts ();
	85	reset_cpu (0);
	86
	87	/NOTREACHED/
	88	return (0);
	89	}
	90
	91	/* taken from blob */
	92	void icache_enable (void)
	93	{
	94	register u32 i;
	95
	96	/* read control register */
	97	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	98
	99	/* set i-cache */
	100	i \|= 0x1000;
	101
	102	/* write back to control register */
	103	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	104	}
	105
	106	void icache_disable (void)
	107	{
	108	register u32 i;
	109
	110	/* read control register */
	111	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	112
	113	/* clear i-cache */
	114	i &= ~0x1000;
	115
	116	/* write back to control register */
	117	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	118
	119	/* flush i-cache */
	120	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
	121	}
	122
	123	int icache_status (void)
	124	{
	125	register u32 i;
	126
	127	/* read control register */
	128	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	129
	130	/* return bit */
	131	return (i & 0x1000);
	132	}
	133
	134	/* we will never enable dcache, because we have to setup MMU first */
	135	void dcache_enable (void)
	136	{
	137	return;
	138	}
	139
	140	void dcache_disable (void)
	141	{
	142	return;
	143	}
	144
	145	int dcache_status (void)
146	{
147	return 0; /* always off */
148	}
149
150	/* FIXME */
a1191902	151	/*
2d5b561e WD	152	void pci_init(void)
	153	{
	154	return;
	155	}
a1191902	156	*/