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Add MCF5282 support (without preloader)
[people/ms/u-boot.git] / cpu / mcf52x2 / fec.c
CommitLineData
bf9e3b38
WD		 1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <asm/fec.h>
27
28#ifdef CONFIG_M5272
29#include <asm/m5272.h>
30#include <asm/immap_5272.h>
31#endif
32
33#ifdef CONFIG_M5282
34#include <asm/m5282.h>
35#include <asm/immap_5282.h>
36#endif
37
38#include <net.h>
39#include <command.h>
40
41#ifdef CONFIG_M5272
42#define FEC_ADDR (CFG_MBAR + 0x840)
43#endif
44#ifdef CONFIG_M5282
45#define FEC_ADDR (CFG_MBAR + 0x1000)
46#endif
47
48#undef ET_DEBUG
49#undef MII_DEBUG
50
51#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
52
53#ifdef CFG_DISCOVER_PHY
54#include <miiphy.h>
55static void mii_discover_phy (void);
56#endif
57
58/* Ethernet Transmit and Receive Buffers */
59#define DBUF_LENGTH 1520
60
61#define TX_BUF_CNT 2
62
63#define TOUT_LOOP 100
64
65#define PKT_MAXBUF_SIZE 1518
66#define PKT_MINBUF_SIZE 64
67#define PKT_MAXBLR_SIZE 1520
68
69
70static char txbuf[DBUF_LENGTH];
71
72static uint rxIdx; /* index of the current RX buffer */
73static uint txIdx; /* index of the current TX buffer */
74
75/*
76 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
77 * immr->udata_bd address on Dual-Port RAM
78 * Provide for Double Buffering
79 */
80
81typedef volatile struct CommonBufferDescriptor {
82 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
83 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
84} RTXBD;
85
86static RTXBD *rtx = NULL;
87
88int eth_send (volatile void *packet, int length)
89{
90 int j, rc;
91 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
92
93 /* section 16.9.23.3
94 * Wait for ready
95 */
96 j = 0;
97 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
98 && (j < TOUT_LOOP)) {
99 udelay (1);
100 j++;
101 }
102 if (j >= TOUT_LOOP) {
103 printf ("TX not ready\n");
104 }
105
106 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
107 rtx->txbd[txIdx].cbd_datlen = length;
108 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
109
110 /* Activate transmit Buffer Descriptor polling */
111 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
112
113 j = 0;
114 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
115 && (j < TOUT_LOOP)) {
116 udelay (1);
117 j++;
118 }
119 if (j >= TOUT_LOOP) {
120 printf ("TX timeout\n");
121 }
122#ifdef ET_DEBUG
123 printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
124 __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
125 (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
126#endif
127
128 /* return only status bits */ ;
129 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
130
131 txIdx = (txIdx + 1) % TX_BUF_CNT;
132
133 return rc;
134}
135
136int eth_rx (void)
137{
138 int length;
139 volatile fec_t *fecp = (fec_t *) FEC_ADDR;
140
141 for (;;) {
142 /* section 16.9.23.2 */
143 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
144 length = -1;
145 break; /* nothing received - leave for() loop */
146 }
147
148 length = rtx->rxbd[rxIdx].cbd_datlen;
149
150 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
151#ifdef ET_DEBUG
152 printf ("%s[%d] err: %x\n",
153 __FUNCTION__, __LINE__,
154 rtx->rxbd[rxIdx].cbd_sc);
155#endif
156 } else {
157 /* Pass the packet up to the protocol layers. */
158 NetReceive (NetRxPackets[rxIdx], length - 4);
159 }
160
161 /* Give the buffer back to the FEC. */
162 rtx->rxbd[rxIdx].cbd_datlen = 0;
163
164 /* wrap around buffer index when necessary */
165 if ((rxIdx + 1) >= PKTBUFSRX) {
166 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
167 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
168 rxIdx = 0;
169 } else {
170 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
171 rxIdx++;
172 }
173
174 /* Try to fill Buffer Descriptors */
175 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
176 }
177
178 return length;
179}
180
181/**************************************************************
182 *
183 * FEC Ethernet Initialization Routine
184 *
185 *************************************************************/
186#define FEC_ECNTRL_ETHER_EN 0x00000002
187#define FEC_ECNTRL_RESET 0x00000001
188
189#define FEC_RCNTRL_BC_REJ 0x00000010
190#define FEC_RCNTRL_PROM 0x00000008
191#define FEC_RCNTRL_MII_MODE 0x00000004
192#define FEC_RCNTRL_DRT 0x00000002
193#define FEC_RCNTRL_LOOP 0x00000001
194
195#define FEC_TCNTRL_FDEN 0x00000004
196#define FEC_TCNTRL_HBC 0x00000002
197#define FEC_TCNTRL_GTS 0x00000001
198
199#define FEC_RESET_DELAY 50000
200
201int eth_init (bd_t * bd)
202{
9acb626f
HS		 203#ifndef CFG_ENET_BD_BASE
204 DECLARE_GLOBAL_DATA_PTR;
205#endif
bf9e3b38
WD		 206 int i;
207 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
208
209 /* Whack a reset.
210 * A delay is required between a reset of the FEC block and
211 * initialization of other FEC registers because the reset takes
212 * some time to complete. If you don't delay, subsequent writes
213 * to FEC registers might get killed by the reset routine which is
214 * still in progress.
215 */
216 fecp->fec_ecntrl = FEC_ECNTRL_RESET;
217 for (i = 0;
218 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
219 ++i) {
220 udelay (1);
221 }
222 if (i == FEC_RESET_DELAY) {
223 printf ("FEC_RESET_DELAY timeout\n");
224 return 0;
225 }
226
227 /* We use strictly polling mode only
228 */
229 fecp->fec_imask = 0;
230
231 /* Clear any pending interrupt */
232 fecp->fec_ievent = 0xffffffff;
233
234 /* Set station address */
235#define ea bd->bi_enetaddr
236 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
237 (ea[2] << 8) | (ea[3]);
238 fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
239#ifdef ET_DEBUG
240 printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
241 ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
242#endif
243#undef ea
244
245 /* Clear multicast address hash table
246 */
9acb626f
HS		 247#ifdef CONFIG_M5282
248 fecp->fec_ihash_table_high = 0;
249 fecp->fec_ihash_table_low = 0;
250#else
bf9e3b38
WD		 251 fecp->fec_hash_table_high = 0;
252 fecp->fec_hash_table_low = 0;
9acb626f 253#endif
bf9e3b38
WD		 254 /* Set maximum receive buffer size.
255 */
256 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
257
258 /*
259 * Setup Buffers and Buffer Desriptors
260 */
261 rxIdx = 0;
262 txIdx = 0;
263
264 if (!rtx) {
9acb626f 265#ifdef CFG_ENET_BD_BASE
bf9e3b38 266 rtx = (RTXBD *) CFG_ENET_BD_BASE;
9acb626f
HS		 267#else
268 rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
269 (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
270 +0xFF)
271 & ~0xFF)
272 );
273 debug("set ENET_DB_BASE to %lX\n",(long) rtx);
274#endif
bf9e3b38
WD		 275 }
276
277 /*
278 * Setup Receiver Buffer Descriptors (13.14.24.18)
279 * Settings:
280 * Empty, Wrap
281 */
282 for (i = 0; i < PKTBUFSRX; i++) {
283 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
284 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
285 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
286 }
287 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
288
289 /*
290 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
291 * Settings:
292 * Last, Tx CRC
293 */
294 for (i = 0; i < TX_BUF_CNT; i++) {
295 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
296 rtx->txbd[i].cbd_datlen = 0; /* Reset */
297 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
298 }
299 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
300
301 /* Set receive and transmit descriptor base
302 */
303 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
304 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
305
306 /* Enable MII mode
307 */
308#if 0 /* Full duplex mode */
309 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
310 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
311#else /* Half duplex mode */
9acb626f
HS		 312 fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
313 fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
bf9e3b38
WD		 314 fecp->fec_x_cntrl = 0;
315#endif
316 /* Set MII speed */
9acb626f
HS		 317 fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
318 fecp->fec_mii_speed *= 2;
bf9e3b38
WD		 319
320 /* Configure port B for MII.
321 */
322 /* port initialization was already made in cpu_init_f() */
323
324 /* Now enable the transmit and receive processing
325 */
326 fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
327
328#ifdef CFG_DISCOVER_PHY
329 /* wait for the PHY to wake up after reset */
330 mii_discover_phy ();
331#endif
332
333 /* And last, try to fill Rx Buffer Descriptors */
334 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
335
336 return 1;
337}
338
339void eth_halt (void)
340{
341 volatile fec_t *fecp = (fec_t *) FEC_ADDR;
342
343 fecp->fec_ecntrl = 0;
344}
345
346
347#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
348
349static int phyaddr = -1; /* didn't find a PHY yet */
350static uint phytype;
351
352/* Make MII read/write commands for the FEC.
353*/
354
355#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
356 (REG & 0x1f) << 18))
357
358#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
359 (REG & 0x1f) << 18) | \
360 (VAL & 0xffff))
361
362/* Interrupt events/masks.
363*/
364#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
365#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
366#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
367#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
368#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
369#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
370#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
371#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
372#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
373#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
374
375/* PHY identification
376 */
377#define PHY_ID_LXT970 0x78100000 /* LXT970 */
378#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
379#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
380#define PHY_ID_QS6612 0x01814400 /* QS6612 */
381#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
382#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
383#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
384
385/* send command to phy using mii, wait for result */
386static uint mii_send (uint mii_cmd)
387{
388 uint mii_reply;
389 volatile fec_t *ep = (fec_t *) (FEC_ADDR);
390
391 ep->fec_mii_data = mii_cmd; /* command to phy */
392
393 /* wait for mii complete */
394 while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
395 mii_reply = ep->fec_mii_data; /* result from phy */
396 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
397#ifdef ET_DEBUG
398 printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
399 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
400#endif
401 return (mii_reply & 0xffff); /* data read from phy */
402}
403#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
404
405#if defined(CFG_DISCOVER_PHY)
406static void mii_discover_phy (void)
407{
408#define MAX_PHY_PASSES 11
409 uint phyno;
410 int pass;
411
412 phyaddr = -1; /* didn't find a PHY yet */
413 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
414 if (pass > 1) {
415 /* PHY may need more time to recover from reset.
416 * The LXT970 needs 50ms typical, no maximum is
417 * specified, so wait 10ms before try again.
418 * With 11 passes this gives it 100ms to wake up.
419 */
420 udelay (10000); /* wait 10ms */
421 }
9acb626f 422 for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
bf9e3b38
WD		 423 phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
424#ifdef ET_DEBUG
425 printf ("PHY type 0x%x pass %d type ", phytype, pass);
426#endif
427 if (phytype != 0xffff) {
428 phyaddr = phyno;
429 phytype <<= 16;
430 phytype |= mii_send (mk_mii_read (phyno,
431 PHY_PHYIDR2));
432
433#ifdef ET_DEBUG
434 printf ("PHY @ 0x%x pass %d type ", phyno,
435 pass);
436 switch (phytype & 0xfffffff0) {
437 case PHY_ID_LXT970:
438 printf ("LXT970\n");
439 break;
440 case PHY_ID_LXT971:
441 printf ("LXT971\n");
442 break;
443 case PHY_ID_82555:
444 printf ("82555\n");
445 break;
446 case PHY_ID_QS6612:
447 printf ("QS6612\n");
448 break;
449 case PHY_ID_AMD79C784:
450 printf ("AMD79C784\n");
451 break;
452 case PHY_ID_LSI80225B:
453 printf ("LSI L80225/B\n");
454 break;
455 default:
456 printf ("0x%08x\n", phytype);
457 break;
458 }
459#endif
460 }
461 }
462 }
463 if (phyaddr < 0) {
464 printf ("No PHY device found.\n");
465 }
466}
467#endif /* CFG_DISCOVER_PHY */
468
469#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
470
471static int mii_init_done = 0;
472
473/****************************************************************************
474 * mii_init -- Initialize the MII for MII command without ethernet
475 * This function is a subset of eth_init
476 ****************************************************************************
477 */
478void mii_init (void)
479{
480 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
481
482 int i;
483
484 if (mii_init_done != 0) {
485 return;
486 }
487
488 /* Whack a reset.
489 * A delay is required between a reset of the FEC block and
490 * initialization of other FEC registers because the reset takes
491 * some time to complete. If you don't delay, subsequent writes
492 * to FEC registers might get killed by the reset routine which is
493 * still in progress.
494 */
495
496 fecp->fec_ecntrl = FEC_ECNTRL_RESET;
497 for (i = 0;
498 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
499 ++i) {
500 udelay (1);
501 }
502 if (i == FEC_RESET_DELAY) {
503 printf ("FEC_RESET_DELAY timeout\n");
504 return;
505 }
506
507 /* We use strictly polling mode only
508 */
509 fecp->fec_imask = 0;
510
511 /* Clear any pending interrupt
512 */
513 fecp->fec_ievent = 0xffffffff;
514
515 /* Set MII speed */
516 fecp->fec_mii_speed = 0x0e;
517
518 /* Configure port B for MII.
519 */
520 /* port initialization was already made in cpu_init_f() */
521
522 /* Now enable the transmit and receive processing */
523 fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
524
525 mii_init_done = 1;
526}
527
528/*****************************************************************************
529 * Read and write a MII PHY register, routines used by MII Utilities
530 *
531 * FIXME: These routines are expected to return 0 on success, but mii_send
532 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
533 * no PHY connected...
534 * For now always return 0.
535 * FIXME: These routines only work after calling eth_init() at least once!
536 * Otherwise they hang in mii_send() !!! Sorry!
537 *****************************************************************************/
538
63ff004c
MB		 539int mcf52x2_miiphy_read (char *devname, unsigned char addr,
540 unsigned char reg, unsigned short *value)
bf9e3b38
WD		 541{
542 short rdreg; /* register working value */
543
544#ifdef MII_DEBUG
545 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
546#endif
547 rdreg = mii_send (mk_mii_read (addr, reg));
548
549 *value = rdreg;
550
551#ifdef MII_DEBUG
552 printf ("0x%04x\n", *value);
553#endif
554
555 return 0;
556}
557
63ff004c
MB		 558int mcf52x2_miiphy_write (char *devname, unsigned char addr,
559 unsigned char reg, unsigned short value)
bf9e3b38
WD		 560{
561 short rdreg; /* register working value */
562
563#ifdef MII_DEBUG
564 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
565#endif
566
567 rdreg = mii_send (mk_mii_write (addr, reg, value));
568
569#ifdef MII_DEBUG
570 printf ("0x%04x\n", value);
571#endif
572
573 return 0;
574}
575#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
bf9e3b38 576#endif /* CFG_CMD_NET, FEC_ENET */
63ff004c
MB		 577
578int mcf52x2_miiphy_initialize(bd_t *bis)
579{
580#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
581#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
582 miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
583#endif
584#endif
585 return 0;
586}
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