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8ae158cd TL |
1 | /* |
2 | * | |
3 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
4 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <asm/processor.h> | |
27 | ||
28 | #include <asm/immap.h> | |
29 | ||
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
32 | /* | |
33 | * Low Power Divider specifications | |
34 | */ | |
35 | #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ | |
36 | #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ | |
37 | ||
38 | #define CLOCK_PLL_FVCO_MAX 540000000 | |
39 | #define CLOCK_PLL_FVCO_MIN 300000000 | |
40 | ||
41 | #define CLOCK_PLL_FSYS_MAX 266666666 | |
42 | #define CLOCK_PLL_FSYS_MIN 100000000 | |
43 | #define MHZ 1000000 | |
44 | ||
45 | void clock_enter_limp(int lpdiv) | |
46 | { | |
47 | volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; | |
48 | int i, j; | |
49 | ||
50 | /* Check bounds of divider */ | |
51 | if (lpdiv < CLOCK_LPD_MIN) | |
52 | lpdiv = CLOCK_LPD_MIN; | |
53 | if (lpdiv > CLOCK_LPD_MAX) | |
54 | lpdiv = CLOCK_LPD_MAX; | |
55 | ||
56 | /* Round divider down to nearest power of two */ | |
57 | for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; | |
58 | ||
59 | /* Apply the divider to the system clock */ | |
60 | ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); | |
61 | ||
62 | /* Enable Limp Mode */ | |
63 | ccm->misccr |= CCM_MISCCR_LIMP; | |
64 | } | |
65 | ||
66 | /* | |
67 | * brief Exit Limp mode | |
68 | * warning The PLL should be set and locked prior to exiting Limp mode | |
69 | */ | |
70 | void clock_exit_limp(void) | |
71 | { | |
72 | volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; | |
73 | volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; | |
74 | ||
75 | /* Exit Limp mode */ | |
76 | ccm->misccr &= ~CCM_MISCCR_LIMP; | |
77 | ||
78 | /* Wait for the PLL to lock */ | |
79 | while (!(pll->psr & PLL_PSR_LOCK)) ; | |
80 | } | |
81 | ||
82 | /* | |
83 | * get_clocks() fills in gd->cpu_clock and gd->bus_clk | |
84 | */ | |
85 | int get_clocks(void) | |
86 | { | |
9f751551 | 87 | |
8ae158cd TL |
88 | volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; |
89 | volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; | |
8ae158cd TL |
90 | int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; |
91 | int pllmult_pci[] = { 12, 6, 16, 8 }; | |
9f751551 | 92 | int vco = 0, bPci, temp, fbtemp, pcrvalue; |
8ae158cd TL |
93 | int *pPllmult = NULL; |
94 | u16 fbpll_mask; | |
9f751551 TL |
95 | |
96 | #ifdef CONFIG_M54455EVB | |
6d0f6bcf | 97 | volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3); |
9f751551 TL |
98 | #endif |
99 | u8 bootmode; | |
8ae158cd TL |
100 | |
101 | /* To determine PCI is present or not */ | |
102 | if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || | |
103 | ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { | |
104 | pPllmult = &pllmult_pci[0]; | |
9f751551 | 105 | fbpll_mask = 3; /* 11b */ |
8ae158cd TL |
106 | bPci = 1; |
107 | } else { | |
108 | pPllmult = &pllmult_nopci[0]; | |
9f751551 | 109 | fbpll_mask = 7; /* 111b */ |
8ae158cd TL |
110 | #ifdef CONFIG_PCI |
111 | gd->pci_clk = 0; | |
112 | #endif | |
113 | bPci = 0; | |
114 | } | |
115 | ||
116 | #ifdef CONFIG_M54455EVB | |
9f751551 | 117 | bootmode = (*cpld & 0x03); |
8ae158cd | 118 | |
9f751551 TL |
119 | if (bootmode != 3) { |
120 | /* Temporary read from CCR- fixed fb issue, must be the same clock | |
121 | as pci or input clock, causing cpld/fpga read inconsistancy */ | |
122 | fbtemp = pPllmult[ccm->ccr & fbpll_mask]; | |
8ae158cd | 123 | |
9f751551 TL |
124 | /* Break down into small pieces, code still in flex bus */ |
125 | pcrvalue = pll->pcr & 0xFFFFF0FF; | |
126 | temp = fbtemp - 1; | |
127 | pcrvalue |= PLL_PCR_OUTDIV3(temp); | |
128 | ||
129 | pll->pcr = pcrvalue; | |
130 | } | |
131 | #endif | |
132 | #ifdef CONFIG_M54451EVB | |
133 | /* No external logic to read the bootmode, hard coded from built */ | |
134 | #ifdef CONFIG_CF_SBF | |
135 | bootmode = 3; | |
136 | #else | |
137 | bootmode = 2; | |
138 | ||
139 | /* default value is 16 mul, set to 20 mul */ | |
140 | pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000; | |
8ae158cd | 141 | pll->pcr = pcrvalue; |
9f751551 TL |
142 | while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK); |
143 | #endif | |
144 | #endif | |
8ae158cd | 145 | |
9f751551 | 146 | if (bootmode == 0) { |
8ae158cd | 147 | /* RCON mode */ |
6d0f6bcf | 148 | vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; |
8ae158cd TL |
149 | |
150 | if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { | |
151 | /* invaild range, re-set in PCR */ | |
152 | int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; | |
153 | int i, j, bus; | |
154 | ||
155 | j = (pll->pcr & 0xFF000000) >> 24; | |
156 | for (i = j; i < 0xFF; i++) { | |
6d0f6bcf | 157 | vco = i * CONFIG_SYS_INPUT_CLKSRC; |
8ae158cd TL |
158 | if (vco >= CLOCK_PLL_FVCO_MIN) { |
159 | bus = vco / temp; | |
160 | if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) | |
161 | continue; | |
162 | else | |
163 | break; | |
164 | } | |
165 | } | |
166 | pcrvalue = pll->pcr & 0x00FF00FF; | |
167 | fbtemp = ((i - 1) << 8) | ((i - 1) << 12); | |
168 | pcrvalue |= ((i << 24) | fbtemp); | |
169 | ||
170 | pll->pcr = pcrvalue; | |
171 | } | |
172 | gd->vco_clk = vco; /* Vco clock */ | |
9f751551 | 173 | } else if (bootmode == 2) { |
8ae158cd | 174 | /* Normal mode */ |
6d0f6bcf | 175 | vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; |
9f751551 TL |
176 | if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { |
177 | /* Default value */ | |
178 | pcrvalue = (pll->pcr & 0x00FFFFFF); | |
179 | pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24; | |
180 | pll->pcr = pcrvalue; | |
6d0f6bcf | 181 | vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; |
9f751551 | 182 | } |
8ae158cd | 183 | gd->vco_clk = vco; /* Vco clock */ |
9f751551 | 184 | } else if (bootmode == 3) { |
8ae158cd | 185 | /* serial mode */ |
6d0f6bcf | 186 | vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; |
9f751551 | 187 | gd->vco_clk = vco; /* Vco clock */ |
8ae158cd | 188 | } |
8ae158cd TL |
189 | |
190 | if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { | |
191 | /* Limp mode */ | |
192 | } else { | |
6d0f6bcf | 193 | gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ |
8ae158cd TL |
194 | |
195 | temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; | |
196 | gd->cpu_clk = vco / temp; /* cpu clock */ | |
197 | ||
198 | temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; | |
199 | gd->bus_clk = vco / temp; /* bus clock */ | |
200 | ||
201 | temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; | |
202 | gd->flb_clk = vco / temp; /* FlexBus clock */ | |
203 | ||
204 | #ifdef CONFIG_PCI | |
205 | if (bPci) { | |
206 | temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; | |
207 | gd->pci_clk = vco / temp; /* PCI clock */ | |
208 | } | |
209 | #endif | |
210 | } | |
211 | ||
eec567a6 TL |
212 | #ifdef CONFIG_FSL_I2C |
213 | gd->i2c1_clk = gd->bus_clk; | |
214 | #endif | |
215 | ||
8ae158cd TL |
216 | return (0); |
217 | } |