[people/ms/u-boot.git] / cpu / mpc5xxx / pci_mpc5200.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)

#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <mpc5xxx.h>

/* System RAM mapped over PCI */
#define CONFIG_PCI_MEMORY_BUS	CFG_SDRAM_BASE
#define CONFIG_PCI_MEMORY_PHYS	CFG_SDRAM_BASE
#define CONFIG_PCI_MEMORY_SIZE	(1024 * 1024 * 1024)

/* PCIIWCR bit fields */
#define IWCR_MEM	(0 << 3)
#define IWCR_IO		(1 << 3)
#define IWCR_READ	(0 << 1)
#define IWCR_READLINE	(1 << 1)
#define IWCR_READMULT	(2 << 1)
#define IWCR_EN		(1 << 0)

static int mpc5200_read_config_dword(struct pci_controller *hose,
			      pci_dev_t dev, int offset, u32* value)
{
	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
	eieio();
	udelay(10);
	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
	eieio();
	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
	udelay(10);
	return 0;
}

static int mpc5200_write_config_dword(struct pci_controller *hose,
			      pci_dev_t dev, int offset, u32 value)
{
	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
	eieio();
	udelay(10);
	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
	eieio();
	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
	udelay(10);
	return 0;
}

void pci_mpc5xxx_init (struct pci_controller *hose)
{
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System space */
	pci_set_region(hose->regions + 0,
		       CONFIG_PCI_MEMORY_BUS,
		       CONFIG_PCI_MEMORY_PHYS,
		       CONFIG_PCI_MEMORY_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CONFIG_PCI_MEM_BUS,
		       CONFIG_PCI_MEM_PHYS,
		       CONFIG_PCI_MEM_SIZE,
		       PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CONFIG_PCI_IO_BUS,
		       CONFIG_PCI_IO_PHYS,
		       CONFIG_PCI_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 3;

	pci_register_hose(hose);

	/* GPIO Multiplexing - enable PCI */
	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);

	/* Set host bridge as pci master and enable memory decoding */
	*(vu_long *)MPC5XXX_PCI_CMD |=
		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;

	/* Set maximum latency timer */
	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);

	/* Set cache line size */
	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
		(CFG_CACHELINE_SIZE / 4);

	/* Map MBAR to PCI space */
	*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
	*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;

	/* Map RAM to PCI space */
	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;

	/* Enable snooping for RAM */
	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;

	/* Park XLB on PCI */
	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);

#if 0
	/* Enable piplining */
	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
#endif

	/* Disable interrupts from PCI controller */
	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
	*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);

	/* Disable initiator windows */
	*(vu_long *)MPC5XXX_PCI_IWCR = 0;

	/* Map PCI memory to physical space */
	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
		(CONFIG_PCI_MEM_BUS >> 16);
	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;

	/* Map PCI I/O to physical space */
	*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
		(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
		(CONFIG_PCI_IO_BUS >> 16);
	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;

	/* Reset the PCI bus */
	*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
	udelay(1000);
	*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
	udelay(1000);

	pci_set_ops(hose,
		pci_hose_read_config_byte_via_dword,
		pci_hose_read_config_word_via_dword,
		mpc5200_read_config_dword,
		pci_hose_write_config_byte_via_dword,
		pci_hose_write_config_word_via_dword,
		mpc5200_write_config_dword);

	udelay(1000);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif

	hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI && CONFIG_MPC5200 */
Commit	Line	Data
96e48cf6 WD	1	/*
	2	* (C) Copyright 2000-2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25
	26	#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
	27
	28	#include <asm/processor.h>
	29	#include <asm/io.h>
	30	#include <pci.h>
	31	#include <mpc5xxx.h>
	32
	33	/* System RAM mapped over PCI */
	34	#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
	35	#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
	36	#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
	37
	38	/* PCIIWCR bit fields */
	39	#define IWCR_MEM (0 << 3)
	40	#define IWCR_IO (1 << 3)
	41	#define IWCR_READ (0 << 1)
	42	#define IWCR_READLINE (1 << 1)
	43	#define IWCR_READMULT (2 << 1)
	44	#define IWCR_EN (1 << 0)
	45
	46	static int mpc5200_read_config_dword(struct pci_controller *hose,
	47	pci_dev_t dev, int offset, u32* value)
	48	{
	49	(volatile u32 )MPC5XXX_PCI_CAR = (1 << 31) \| dev \| offset;
	50	eieio();
35656de7	51	udelay(10);
96e48cf6 WD	52	value = in_le32((volatile u32 )CONFIG_PCI_IO_PHYS);
	53	eieio();
	54	(volatile u32 )MPC5XXX_PCI_CAR = 0;
35656de7	55	udelay(10);
96e48cf6 WD	56	return 0;
	57	}
	58
	59	static int mpc5200_write_config_dword(struct pci_controller *hose,
	60	pci_dev_t dev, int offset, u32 value)
	61	{
	62	(volatile u32 )MPC5XXX_PCI_CAR = (1 << 31) \| dev \| offset;
	63	eieio();
35656de7	64	udelay(10);
96e48cf6 WD	65	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
	66	eieio();
	67	(volatile u32 )MPC5XXX_PCI_CAR = 0;
35656de7	68	udelay(10);
96e48cf6 WD	69	return 0;
	70	}
	71
	72	void pci_mpc5xxx_init (struct pci_controller *hose)
	73	{
	74	hose->first_busno = 0;
	75	hose->last_busno = 0xff;
	76
	77	/* System space */
	78	pci_set_region(hose->regions + 0,
	79	CONFIG_PCI_MEMORY_BUS,
	80	CONFIG_PCI_MEMORY_PHYS,
	81	CONFIG_PCI_MEMORY_SIZE,
	82	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	83
	84	/* PCI memory space */
	85	pci_set_region(hose->regions + 1,
	86	CONFIG_PCI_MEM_BUS,
	87	CONFIG_PCI_MEM_PHYS,
	88	CONFIG_PCI_MEM_SIZE,
	89	PCI_REGION_MEM);
	90
	91	/* PCI IO space */
	92	pci_set_region(hose->regions + 2,
	93	CONFIG_PCI_IO_BUS,
	94	CONFIG_PCI_IO_PHYS,
	95	CONFIG_PCI_IO_SIZE,
	96	PCI_REGION_IO);
	97
	98	hose->region_count = 3;
	99
	100	pci_register_hose(hose);
	101
	102	/* GPIO Multiplexing - enable PCI */
	103	(vu_long )MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
42d1f039	104
96e48cf6 WD	105	/* Set host bridge as pci master and enable memory decoding */
	106	(vu_long )MPC5XXX_PCI_CMD \|=
	107	PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
42d1f039	108
96e48cf6 WD	109	/* Set maximum latency timer */
	110	(vu_long )MPC5XXX_PCI_CFG \|= (0xf800);
	111
	112	/* Set cache line size */
	113	(vu_long )MPC5XXX_PCI_CFG = ((vu_long )MPC5XXX_PCI_CFG & ~0xff) \|
	114	(CFG_CACHELINE_SIZE / 4);
42d1f039	115
96e48cf6 WD	116	/* Map MBAR to PCI space */
	117	(vu_long )MPC5XXX_PCI_BAR0 = CFG_MBAR;
	118	(vu_long )MPC5XXX_PCI_TBATR1 = CFG_MBAR \| 1;
42d1f039	119
96e48cf6 WD	120	/* Map RAM to PCI space */
	121	(vu_long )MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS \| (1 << 3);
	122	(vu_long )MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS \| 1;
	123
	124	/* Enable snooping for RAM */
	125	(vu_long )(MPC5XXX_XLBARB + 0x40) \|= (1 << 15);
	126	(vu_long )(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS \| 0x1d;
	127
	128	/* Park XLB on PCI */
	129	(vu_long )(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) \| (3 << 5));
	130	(vu_long )(MPC5XXX_XLBARB + 0x40) \|= (3 << 8) \| (3 << 5);
	131
373e6bec	132	#if 0
96e48cf6 WD	133	/* Enable piplining */
96e48cf6 WD	134	(vu_long )(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
373e6bec	135	#endif
42d1f039	136
96e48cf6 WD	137	/* Disable interrupts from PCI controller */
	138	(vu_long )MPC5XXX_PCI_GSCR &= ~(7 << 12);
	139	(vu_long )MPC5XXX_PCI_ICR &= ~(7 << 24);
42d1f039	140
96e48cf6 WD	141	/* Disable initiator windows */
96e48cf6 WD	142	(vu_long )MPC5XXX_PCI_IWCR = 0;
42d1f039	143
96e48cf6 WD	144	/* Map PCI memory to physical space */
	145	(vu_long )MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS \|
	146	(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) \|
	147	(CONFIG_PCI_MEM_BUS >> 16);
	148	(vu_long )MPC5XXX_PCI_IWCR \|= (IWCR_MEM \| IWCR_READ \| IWCR_EN) << 24;
	149
	150	/* Map PCI I/O to physical space */
	151	(vu_long )MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS \|
	152	(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) \|
	153	(CONFIG_PCI_IO_BUS >> 16);
	154	(vu_long )MPC5XXX_PCI_IWCR \|= (IWCR_IO \| IWCR_READ \| IWCR_EN) << 16;
	155
	156	/* Reset the PCI bus */
	157	(vu_long )MPC5XXX_PCI_GSCR \|= 1;
	158	udelay(1000);
	159	(vu_long )MPC5XXX_PCI_GSCR &= ~1;
	160	udelay(1000);
	161
	162	pci_set_ops(hose,
	163	pci_hose_read_config_byte_via_dword,
	164	pci_hose_read_config_word_via_dword,
	165	mpc5200_read_config_dword,
	166	pci_hose_write_config_byte_via_dword,
	167	pci_hose_write_config_word_via_dword,
	168	mpc5200_write_config_dword);
42d1f039	169
96e48cf6 WD	170	udelay(1000);
	171
	172	#ifdef CONFIG_PCI_SCAN_SHOW
	173	printf("PCI: Bus Dev VenId DevId Class Int\n");
	174	#endif
	175
	176	hose->last_busno = pci_hose_scan(hose);
	177	}
	178	#endif /* CONFIG_PCI && CONFIG_MPC5200 */