[people/ms/u-boot.git] / cpu / mpc83xx / cpu.c

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code for the MPC83xx family.
 *
 * Derived from the MPC8260 and MPC85xx.
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mpc83xx.h>
#include <asm/processor.h>
#include <libfdt.h>
#include <tsec.h>

DECLARE_GLOBAL_DATA_PTR;

int checkcpu(void)
{
	volatile immap_t *immr;
	ulong clock = gd->cpu_clk;
	u32 pvr = get_pvr();
	u32 spridr;
	char buf[32];
	int i;

	const struct cpu_type {
		char name[15];
		u32 partid;
	} cpu_type_list [] = {
		CPU_TYPE_ENTRY(8311),
		CPU_TYPE_ENTRY(8313),
		CPU_TYPE_ENTRY(8314),
		CPU_TYPE_ENTRY(8315),
		CPU_TYPE_ENTRY(8321),
		CPU_TYPE_ENTRY(8323),
		CPU_TYPE_ENTRY(8343),
		CPU_TYPE_ENTRY(8347_TBGA_),
		CPU_TYPE_ENTRY(8347_PBGA_),
		CPU_TYPE_ENTRY(8349),
		CPU_TYPE_ENTRY(8358_TBGA_),
		CPU_TYPE_ENTRY(8358_PBGA_),
		CPU_TYPE_ENTRY(8360),
		CPU_TYPE_ENTRY(8377),
		CPU_TYPE_ENTRY(8378),
		CPU_TYPE_ENTRY(8379),
	};

	immr = (immap_t *)CONFIG_SYS_IMMR;

	puts("CPU:   ");

	switch (pvr & 0xffff0000) {
		case PVR_E300C1:
			printf("e300c1, ");
			break;

		case PVR_E300C2:
			printf("e300c2, ");
			break;

		case PVR_E300C3:
			printf("e300c3, ");
			break;

		case PVR_E300C4:
			printf("e300c4, ");
			break;

		default:
			printf("Unknown core, ");
	}

	spridr = immr->sysconf.spridr;

	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
		if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
			puts("MPC");
			puts(cpu_type_list[i].name);
			if (IS_E_PROCESSOR(spridr))
				puts("E");
			if (REVID_MAJOR(spridr) >= 2)
				puts("A");
			printf(", Rev: %d.%d", REVID_MAJOR(spridr),
			       REVID_MINOR(spridr));
			break;
		}

	if (i == ARRAY_SIZE(cpu_type_list))
		printf("(SPRIDR %08x unknown), ", spridr);

	printf(" at %s MHz, ", strmhz(buf, clock));

	printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));

	return 0;
}


/*
 * Program a UPM with the code supplied in the table.
 *
 * The 'dummy' variable is used to increment the MAD. 'dummy' is
 * supposed to be a pointer to the memory of the device being
 * programmed by the UPM.  The data in the MDR is written into
 * memory and the MAD is incremented every time there's a write
 * to 'dummy'. Unfortunately, the current prototype for this
 * function doesn't allow for passing the address of this
 * device, and changing the prototype will break a number lots
 * of other code, so we need to use a round-about way of finding
 * the value for 'dummy'.
 *
 * The value can be extracted from the base address bits of the
 * Base Register (BR) associated with the specific UPM.  To find
 * that BR, we need to scan all 8 BRs until we find the one that
 * has its MSEL bits matching the UPM we want.  Once we know the
 * right BR, we can extract the base address bits from it.
 *
 * The MxMR and the BR and OR of the chosen bank should all be
 * configured before calling this function.
 *
 * Parameters:
 * upm: 0=UPMA, 1=UPMB, 2=UPMC
 * table: Pointer to an array of values to program
 * size: Number of elements in the array.  Must be 64 or less.
 */
void upmconfig (uint upm, uint *table, uint size)
{
#if defined(CONFIG_MPC834X)
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile lbus83xx_t *lbus = &immap->lbus;
	volatile uchar *dummy = NULL;
	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */
	uint i;

	/* Scan all the banks to determine the base address of the device */
	for (i = 0; i < 8; i++) {
		if ((lbus->bank[i].br & BR_MSEL) == msel) {
			dummy = (uchar *) (lbus->bank[i].br & BR_BA);
			break;
		}
	}

	if (!dummy) {
		printf("Error: %s() could not find matching BR\n", __FUNCTION__);
		hang();
	}

	/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;

	for (i = 0; i < size; i++) {
		lbus->mdr = table[i];
		__asm__ __volatile__ ("sync");
		*dummy = 0;	/* Write the value to memory and increment MAD */
		__asm__ __volatile__ ("sync");
		while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
	}

	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
	*mxmr &= 0xCFFFFFC0;
#else
	printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
	hang();
#endif
}


int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	ulong msr;
#ifndef MPC83xx_RESET
	ulong addr;
#endif

	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

#ifdef MPC83xx_RESET
	/* Interrupts and MMU off */
	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);

	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));

	/* enable Reset Control Reg */
	immap->reset.rpr = 0x52535445;
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* confirm Reset Control Reg is enabled */
	while(!((immap->reset.rcer) & RCER_CRE));

	printf("Resetting the board.");
	printf("\n");

	udelay(200);

	/* perform reset, only one bit */
	immap->reset.rcr = RCR_SWHR;

#else	/* ! MPC83xx_RESET */

	immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */

	/* Interrupts and MMU off */
	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);

	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));

	/*
	 * Trying to execute the next instruction at a non-existing address
	 * should cause a machine check, resulting in reset
	 */
	addr = CONFIG_SYS_RESET_ADDRESS;

	printf("resetting the board.");
	printf("\n");
	((void (*)(void)) addr) ();
#endif	/* MPC83xx_RESET */

	return 1;
}


/*
 * Get timebase clock frequency (like cpu_clk in Hz)
 */

unsigned long get_tbclk(void)
{
	ulong tbclk;

	tbclk = (gd->bus_clk + 3L) / 4L;

	return tbclk;
}


#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
	int re_enable = disable_interrupts();

	/* Reset the 83xx watchdog */
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	immr->wdt.swsrr = 0x556c;
	immr->wdt.swsrr = 0xaa39;

	if (re_enable)
		enable_interrupts ();
}
#endif

#if defined(CONFIG_DDR_ECC)
void dma_init(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile dma83xx_t *dma = &immap->dma;
	volatile u32 status = swab32(dma->dmasr0);
	volatile u32 dmamr0 = swab32(dma->dmamr0);

	debug("DMA-init\n");

	/* initialize DMASARn, DMADAR and DMAABCRn */
	dma->dmadar0 = (u32)0;
	dma->dmasar0 = (u32)0;
	dma->dmabcr0 = 0;

	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* clear CS bit */
	dmamr0 &= ~DMA_CHANNEL_START;
	dma->dmamr0 = swab32(dmamr0);
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* while the channel is busy, spin */
	while(status & DMA_CHANNEL_BUSY) {
		status = swab32(dma->dmasr0);
	}

	debug("DMA-init end\n");
}

uint dma_check(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile dma83xx_t *dma = &immap->dma;
	volatile u32 status = swab32(dma->dmasr0);
	volatile u32 byte_count = swab32(dma->dmabcr0);

	/* while the channel is busy, spin */
	while (status & DMA_CHANNEL_BUSY) {
		status = swab32(dma->dmasr0);
	}

	if (status & DMA_CHANNEL_TRANSFER_ERROR) {
		printf ("DMA Error: status = %x @ %d\n", status, byte_count);
	}

	return status;
}

int dma_xfer(void *dest, u32 count, void *src)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile dma83xx_t *dma = &immap->dma;
	volatile u32 dmamr0;

	/* initialize DMASARn, DMADAR and DMAABCRn */
	dma->dmadar0 = swab32((u32)dest);
	dma->dmasar0 = swab32((u32)src);
	dma->dmabcr0 = swab32(count);

	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* init direct transfer, clear CS bit */
	dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
			DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
			DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);

	dma->dmamr0 = swab32(dmamr0);

	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	/* set CS to start DMA transfer */
	dmamr0 |= DMA_CHANNEL_START;
	dma->dmamr0 = swab32(dmamr0);
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("isync");

	return ((int)dma_check());
}
#endif /*CONFIG_DDR_ECC*/

/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_TSEC_ENET)
	tsec_standard_init(bis);
#endif

	return 0;
}
Commit	Line	Data
f046ccd1	1	/*
03051c3d	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1 EL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
f046ccd1 EL	21	*/
	22
	23	/*
	24	* CPU specific code for the MPC83xx family.
	25	*
	26	* Derived from the MPC8260 and MPC85xx.
	27	*/
	28
	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <command.h>
	32	#include <mpc83xx.h>
	33	#include <asm/processor.h>
213bf8c8	34	#include <libfdt.h>
75b9d4ae	35	#include <tsec.h>
f046ccd1	36
d87080b7 WD	37	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	38
f046ccd1 EL	39	int checkcpu(void)
f046ccd1 EL	40	{
5f820439	41	volatile immap_t *immr;
f046ccd1 EL	42	ulong clock = gd->cpu_clk;
f046ccd1 EL	43	u32 pvr = get_pvr();
5f820439	44	u32 spridr;
f046ccd1	45	char buf[32];
e5c4ade4 KP	46	int i;
e5c4ade4 KP	47
e5c4ade4 KP	48	const struct cpu_type {
	49	char name[15];
	50	u32 partid;
	51	} cpu_type_list [] = {
	52	CPU_TYPE_ENTRY(8311),
	53	CPU_TYPE_ENTRY(8313),
	54	CPU_TYPE_ENTRY(8314),
	55	CPU_TYPE_ENTRY(8315),
	56	CPU_TYPE_ENTRY(8321),
	57	CPU_TYPE_ENTRY(8323),
	58	CPU_TYPE_ENTRY(8343),
	59	CPU_TYPE_ENTRY(8347_TBGA_),
	60	CPU_TYPE_ENTRY(8347_PBGA_),
	61	CPU_TYPE_ENTRY(8349),
	62	CPU_TYPE_ENTRY(8358_TBGA_),
	63	CPU_TYPE_ENTRY(8358_PBGA_),
	64	CPU_TYPE_ENTRY(8360),
	65	CPU_TYPE_ENTRY(8377),
	66	CPU_TYPE_ENTRY(8378),
	67	CPU_TYPE_ENTRY(8379),
	68	};
f046ccd1	69
6d0f6bcf	70	immr = (immap_t *)CONFIG_SYS_IMMR;
5f820439	71
54b2d434	72	puts("CPU: ");
95e7ef89 SW	73
	74	switch (pvr & 0xffff0000) {
	75	case PVR_E300C1:
	76	printf("e300c1, ");
	77	break;
	78
	79	case PVR_E300C2:
	80	printf("e300c2, ");
	81	break;
	82
	83	case PVR_E300C3:
	84	printf("e300c3, ");
	85	break;
	86
03051c3d DL	87	case PVR_E300C4:
	88	printf("e300c4, ");
	89	break;
	90
95e7ef89 SW	91	default:
95e7ef89 SW	92	printf("Unknown core, ");
f046ccd1 EL	93	}
f046ccd1 EL	94
5f820439	95	spridr = immr->sysconf.spridr;
6902df56	96
e5c4ade4 KP	97	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
	98	if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
	99	puts("MPC");
	100	puts(cpu_type_list[i].name);
	101	if (IS_E_PROCESSOR(spridr))
	102	puts("E");
	103	if (REVID_MAJOR(spridr) >= 2)
	104	puts("A");
	105	printf(", Rev: %d.%d", REVID_MAJOR(spridr),
	106	REVID_MINOR(spridr));
	107	break;
	108	}
	109
	110	if (i == ARRAY_SIZE(cpu_type_list))
	111	printf("(SPRIDR %08x unknown), ", spridr);
	112
	113	printf(" at %s MHz, ", strmhz(buf, clock));
	114
	115	printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
54b2d434	116
f046ccd1 EL	117	return 0;
	118	}
	119
	120
be5e6181	121	/*
2ad6b513 TT	122	* Program a UPM with the code supplied in the table.
	123	*
	124	* The 'dummy' variable is used to increment the MAD. 'dummy' is
	125	* supposed to be a pointer to the memory of the device being
	126	* programmed by the UPM. The data in the MDR is written into
97245557 S	127	* memory and the MAD is incremented every time there's a write
97245557 S	128	* to 'dummy'. Unfortunately, the current prototype for this
2ad6b513 TT	129	* function doesn't allow for passing the address of this
	130	* device, and changing the prototype will break a number lots
	131	* of other code, so we need to use a round-about way of finding
	132	* the value for 'dummy'.
	133	*
	134	* The value can be extracted from the base address bits of the
	135	* Base Register (BR) associated with the specific UPM. To find
	136	* that BR, we need to scan all 8 BRs until we find the one that
	137	* has its MSEL bits matching the UPM we want. Once we know the
	138	* right BR, we can extract the base address bits from it.
	139	*
	140	* The MxMR and the BR and OR of the chosen bank should all be
	141	* configured before calling this function.
	142	*
	143	* Parameters:
	144	* upm: 0=UPMA, 1=UPMB, 2=UPMC
	145	* table: Pointer to an array of values to program
	146	* size: Number of elements in the array. Must be 64 or less.
be5e6181	147	*/
f046ccd1 EL	148	void upmconfig (uint upm, uint *table, uint size)
f046ccd1 EL	149	{
2ad6b513	150	#if defined(CONFIG_MPC834X)
6d0f6bcf	151	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
2ad6b513 TT	152	volatile lbus83xx_t *lbus = &immap->lbus;
	153	volatile uchar *dummy = NULL;
	154	const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
	155	volatile u32 mxmr = &lbus->mamr + upm; / Pointer to mamr, mbmr, or mcmr */
	156	uint i;
	157
	158	/* Scan all the banks to determine the base address of the device */
	159	for (i = 0; i < 8; i++) {
	160	if ((lbus->bank[i].br & BR_MSEL) == msel) {
	161	dummy = (uchar *) (lbus->bank[i].br & BR_BA);
	162	break;
	163	}
	164	}
	165
	166	if (!dummy) {
	167	printf("Error: %s() could not find matching BR\n", __FUNCTION__);
	168	hang();
	169	}
	170
	171	/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
	172	mxmr = (mxmr & 0xCFFFFFC0) \| 0x10000000;
	173
	174	for (i = 0; i < size; i++) {
	175	lbus->mdr = table[i];
	176	__asm__ __volatile__ ("sync");
97245557	177	dummy = 0; / Write the value to memory and increment MAD */
2ad6b513	178	__asm__ __volatile__ ("sync");
97245557	179	while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
2ad6b513 TT	180	}
	181
	182	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
	183	*mxmr &= 0xCFFFFFC0;
	184	#else
	185	printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
	186	hang();
	187	#endif
f046ccd1 EL	188	}
	189
	190
	191	int
	192	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	193	{
07a2505f WD	194	ulong msr;
	195	#ifndef MPC83xx_RESET
	196	ulong addr;
	197	#endif
f046ccd1	198
6d0f6bcf	199	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
f046ccd1 EL	200
	201	#ifdef MPC83xx_RESET
	202	/* Interrupts and MMU off */
	203	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
	204
	205	msr &= ~( MSR_EE \| MSR_IR \| MSR_DR);
	206	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
	207
	208	/* enable Reset Control Reg */
	209	immap->reset.rpr = 0x52535445;
6d8ae5ab MB	210	__asm__ __volatile__ ("sync");
6d8ae5ab MB	211	__asm__ __volatile__ ("isync");
f046ccd1 EL	212
	213	/* confirm Reset Control Reg is enabled */
	214	while(!((immap->reset.rcer) & RCER_CRE));
	215
	216	printf("Resetting the board.");
	217	printf("\n");
	218
	219	udelay(200);
	220
	221	/* perform reset, only one bit */
07a2505f WD	222	immap->reset.rcr = RCR_SWHR;
	223
	224	#else /* ! MPC83xx_RESET */
f046ccd1	225
07a2505f WD	226	immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
	227
	228	/* Interrupts and MMU off */
	229	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
f046ccd1 EL	230
	231	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);
	232	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
	233
	234	/*
	235	* Trying to execute the next instruction at a non-existing address
	236	* should cause a machine check, resulting in reset
	237	*/
6d0f6bcf	238	addr = CONFIG_SYS_RESET_ADDRESS;
f046ccd1 EL	239
	240	printf("resetting the board.");
	241	printf("\n");
	242	((void (*)(void)) addr) ();
07a2505f WD	243	#endif /* MPC83xx_RESET */
07a2505f WD	244
f046ccd1 EL	245	return 1;
	246	}
	247
	248
	249	/*
	250	* Get timebase clock frequency (like cpu_clk in Hz)
	251	*/
	252
	253	unsigned long get_tbclk(void)
	254	{
f046ccd1 EL	255	ulong tbclk;
	256
	257	tbclk = (gd->bus_clk + 3L) / 4L;
	258
	259	return tbclk;
	260	}
	261
	262
	263	#if defined(CONFIG_WATCHDOG)
	264	void watchdog_reset (void)
	265	{
2ad6b513 TT	266	int re_enable = disable_interrupts();
	267
	268	/* Reset the 83xx watchdog */
6d0f6bcf	269	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
2ad6b513 TT	270	immr->wdt.swsrr = 0x556c;
	271	immr->wdt.swsrr = 0xaa39;
	272
	273	if (re_enable)
	274	enable_interrupts ();
f046ccd1	275	}
2ad6b513	276	#endif
62ec6418	277
61f25155 MB	278	#if defined(CONFIG_DDR_ECC)
	279	void dma_init(void)
	280	{
6d0f6bcf	281	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f6eda7f8	282	volatile dma83xx_t *dma = &immap->dma;
61f25155 MB	283	volatile u32 status = swab32(dma->dmasr0);
	284	volatile u32 dmamr0 = swab32(dma->dmamr0);
	285
	286	debug("DMA-init\n");
	287
	288	/* initialize DMASARn, DMADAR and DMAABCRn */
	289	dma->dmadar0 = (u32)0;
	290	dma->dmasar0 = (u32)0;
	291	dma->dmabcr0 = 0;
	292
	293	__asm__ __volatile__ ("sync");
	294	__asm__ __volatile__ ("isync");
	295
	296	/* clear CS bit */
	297	dmamr0 &= ~DMA_CHANNEL_START;
	298	dma->dmamr0 = swab32(dmamr0);
	299	__asm__ __volatile__ ("sync");
	300	__asm__ __volatile__ ("isync");
	301
	302	/* while the channel is busy, spin */
	303	while(status & DMA_CHANNEL_BUSY) {
	304	status = swab32(dma->dmasr0);
	305	}
	306
	307	debug("DMA-init end\n");
	308	}
	309
	310	uint dma_check(void)
	311	{
6d0f6bcf	312	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f6eda7f8	313	volatile dma83xx_t *dma = &immap->dma;
61f25155 MB	314	volatile u32 status = swab32(dma->dmasr0);
	315	volatile u32 byte_count = swab32(dma->dmabcr0);
	316
	317	/* while the channel is busy, spin */
	318	while (status & DMA_CHANNEL_BUSY) {
	319	status = swab32(dma->dmasr0);
	320	}
	321
	322	if (status & DMA_CHANNEL_TRANSFER_ERROR) {
	323	printf ("DMA Error: status = %x @ %d\n", status, byte_count);
	324	}
	325
	326	return status;
	327	}
	328
	329	int dma_xfer(void dest, u32 count, void src)
	330	{
6d0f6bcf	331	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f6eda7f8	332	volatile dma83xx_t *dma = &immap->dma;
61f25155 MB	333	volatile u32 dmamr0;
	334
	335	/* initialize DMASARn, DMADAR and DMAABCRn */
	336	dma->dmadar0 = swab32((u32)dest);
	337	dma->dmasar0 = swab32((u32)src);
	338	dma->dmabcr0 = swab32(count);
	339
	340	__asm__ __volatile__ ("sync");
	341	__asm__ __volatile__ ("isync");
	342
	343	/* init direct transfer, clear CS bit */
	344	dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT \|
	345	DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B \|
	346	DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
cf48eb9a	347
61f25155 MB	348	dma->dmamr0 = swab32(dmamr0);
	349
	350	__asm__ __volatile__ ("sync");
	351	__asm__ __volatile__ ("isync");
	352
	353	/* set CS to start DMA transfer */
	354	dmamr0 \|= DMA_CHANNEL_START;
	355	dma->dmamr0 = swab32(dmamr0);
	356	__asm__ __volatile__ ("sync");
	357	__asm__ __volatile__ ("isync");
	358
	359	return ((int)dma_check());
	360	}
	361	#endif /CONFIG_DDR_ECC/
dd35479a	362
75b9d4ae AF	363	/*
	364	* Initializes on-chip ethernet controllers.
	365	* to override, implement board_eth_init()
dd35479a	366	*/
dd35479a BW	367	int cpu_eth_init(bd_t *bis)
dd35479a BW	368	{
75b9d4ae AF	369	#if defined(CONFIG_TSEC_ENET)
75b9d4ae AF	370	tsec_standard_init(bis);
dd35479a	371	#endif
75b9d4ae	372
dd35479a BW	373	return 0;
dd35479a BW	374	}