projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 42d1f039 | 1 | /* |
| 82fd1f8d | 2 | * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. |
| 42d1f039 | 3 | * Copyright (C) 2003 Motorola,Inc. |
| 42d1f039 WD |
4 | * |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards | |
| 25 | * | |
| 26 | * The processor starts at 0xfffffffc and the code is first executed in the | |
| 27 | * last 4K page(0xfffff000-0xffffffff) in flash/rom. | |
| 28 | * | |
| 29 | */ | |
| 30 | ||
| 31 | #include <config.h> | |
| 32 | #include <mpc85xx.h> | |
| 561858ee | 33 | #include <timestamp.h> |
| 42d1f039 WD |
34 | #include <version.h> |
| 35 | ||
| 36 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
| 37 | ||
| 38 | #include <ppc_asm.tmpl> | |
| 39 | #include <ppc_defs.h> | |
| 40 | ||
| 41 | #include <asm/cache.h> | |
| 42 | #include <asm/mmu.h> | |
| 43 | ||
| 44 | #ifndef CONFIG_IDENT_STRING | |
| 45 | #define CONFIG_IDENT_STRING "" | |
| 46 | #endif | |
| 47 | ||
| 48 | #undef MSR_KERNEL | |
| 61a21e98 | 49 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ |
| 42d1f039 WD |
50 | |
| 51 | /* | |
| 52 | * Set up GOT: Global Offset Table | |
| 53 | * | |
| 54 | * Use r14 to access the GOT | |
| 55 | */ | |
| 56 | START_GOT | |
| 57 | GOT_ENTRY(_GOT2_TABLE_) | |
| 58 | GOT_ENTRY(_FIXUP_TABLE_) | |
| 59 | ||
| 7da53351 | 60 | #ifndef CONFIG_NAND_SPL |
| 42d1f039 WD |
61 | GOT_ENTRY(_start) |
| 62 | GOT_ENTRY(_start_of_vectors) | |
| 63 | GOT_ENTRY(_end_of_vectors) | |
| 64 | GOT_ENTRY(transfer_to_handler) | |
| 7da53351 | 65 | #endif |
| 42d1f039 WD |
66 | |
| 67 | GOT_ENTRY(__init_end) | |
| 68 | GOT_ENTRY(_end) | |
| 69 | GOT_ENTRY(__bss_start) | |
| 70 | END_GOT | |
| 71 | ||
| 72 | /* | |
| 73 | * e500 Startup -- after reset only the last 4KB of the effective | |
| 74 | * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg | |
| 75 | * section is located at THIS LAST page and basically does three | |
| 76 | * things: clear some registers, set up exception tables and | |
| 77 | * add more TLB entries for 'larger spaces'(e.g. the boot rom) to | |
| 78 | * continue the boot procedure. | |
| 79 | ||
| 80 | * Once the boot rom is mapped by TLB entries we can proceed | |
| 81 | * with normal startup. | |
| 82 | * | |
| 83 | */ | |
| 84 | ||
| 61a21e98 AF |
85 | .section .bootpg,"ax" |
| 86 | .globl _start_e500 | |
| 42d1f039 WD |
87 | |
| 88 | _start_e500: | |
| 97d80fc3 | 89 | |
| 61a21e98 | 90 | /* clear registers/arrays not reset by hardware */ |
| 42d1f039 | 91 | |
| 61a21e98 AF |
92 | /* L1 */ |
| 93 | li r0,2 | |
| 94 | mtspr L1CSR0,r0 /* invalidate d-cache */ | |
| 53677ef1 | 95 | mtspr L1CSR1,r0 /* invalidate i-cache */ |
| 42d1f039 WD |
96 | |
| 97 | mfspr r1,DBSR | |
| 98 | mtspr DBSR,r1 /* Clear all valid bits */ | |
| 99 | ||
| 61a21e98 AF |
100 | /* |
| 101 | * Enable L1 Caches early | |
| 102 | * | |
| 103 | */ | |
| 42d1f039 | 104 | |
| 82fd1f8d KG |
105 | #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) |
| 106 | /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ | |
| 107 | li r2,(32 + 0) | |
| 108 | mtspr L1CSR2,r2 | |
| 109 | #endif | |
| 110 | ||
| 61a21e98 AF |
111 | lis r2,L1CSR0_CPE@H /* enable parity */ |
| 112 | ori r2,r2,L1CSR0_DCE | |
| 113 | mtspr L1CSR0,r2 /* enable L1 Dcache */ | |
| 114 | isync | |
| 115 | mtspr L1CSR1,r2 /* enable L1 Icache */ | |
| 42d1f039 | 116 | isync |
| 61a21e98 | 117 | msync |
| 42d1f039 WD |
118 | |
| 119 | /* Setup interrupt vectors */ | |
| 343117bf | 120 | lis r1,TEXT_BASE@h |
| 61a21e98 | 121 | mtspr IVPR,r1 |
| 42d1f039 | 122 | |
| 343117bf | 123 | li r1,0x0100 |
| 42d1f039 | 124 | mtspr IVOR0,r1 /* 0: Critical input */ |
| 343117bf | 125 | li r1,0x0200 |
| 42d1f039 | 126 | mtspr IVOR1,r1 /* 1: Machine check */ |
| 343117bf | 127 | li r1,0x0300 |
| 42d1f039 | 128 | mtspr IVOR2,r1 /* 2: Data storage */ |
| 343117bf | 129 | li r1,0x0400 |
| 42d1f039 WD |
130 | mtspr IVOR3,r1 /* 3: Instruction storage */ |
| 131 | li r1,0x0500 | |
| 132 | mtspr IVOR4,r1 /* 4: External interrupt */ | |
| 133 | li r1,0x0600 | |
| 134 | mtspr IVOR5,r1 /* 5: Alignment */ | |
| 135 | li r1,0x0700 | |
| 136 | mtspr IVOR6,r1 /* 6: Program check */ | |
| 137 | li r1,0x0800 | |
| 138 | mtspr IVOR7,r1 /* 7: floating point unavailable */ | |
| 343117bf | 139 | li r1,0x0900 |
| 42d1f039 WD |
140 | mtspr IVOR8,r1 /* 8: System call */ |
| 141 | /* 9: Auxiliary processor unavailable(unsupported) */ | |
| 343117bf | 142 | li r1,0x0a00 |
| 42d1f039 | 143 | mtspr IVOR10,r1 /* 10: Decrementer */ |
| 343117bf WD |
144 | li r1,0x0b00 |
| 145 | mtspr IVOR11,r1 /* 11: Interval timer */ | |
| 146 | li r1,0x0c00 | |
| 3e0bc447 WD |
147 | mtspr IVOR12,r1 /* 12: Watchdog timer */ |
| 148 | li r1,0x0d00 | |
| 42d1f039 | 149 | mtspr IVOR13,r1 /* 13: Data TLB error */ |
| 343117bf | 150 | li r1,0x0e00 |
| 42d1f039 | 151 | mtspr IVOR14,r1 /* 14: Instruction TLB error */ |
| 343117bf | 152 | li r1,0x0f00 |
| 42d1f039 WD |
153 | mtspr IVOR15,r1 /* 15: Debug */ |
| 154 | ||
| 42d1f039 | 155 | /* Clear and set up some registers. */ |
| 87163180 | 156 | li r0,0x0000 |
| 42d1f039 WD |
157 | lis r1,0xffff |
| 158 | mtspr DEC,r0 /* prevent dec exceptions */ | |
| 159 | mttbl r0 /* prevent fit & wdt exceptions */ | |
| 160 | mttbu r0 | |
| 161 | mtspr TSR,r1 /* clear all timer exception status */ | |
| 162 | mtspr TCR,r0 /* disable all */ | |
| 163 | mtspr ESR,r0 /* clear exception syndrome register */ | |
| 164 | mtspr MCSR,r0 /* machine check syndrome register */ | |
| 165 | mtxer r0 /* clear integer exception register */ | |
| 42d1f039 | 166 | |
| dcc87dd5 SW |
167 | #ifdef CONFIG_SYS_BOOK3E_HV |
| 168 | mtspr MAS8,r0 /* make sure MAS8 is clear */ | |
| 169 | #endif | |
| 170 | ||
| 42d1f039 | 171 | /* Enable Time Base and Select Time Base Clock */ |
| 0ac6f8b7 | 172 | lis r0,HID0_EMCP@h /* Enable machine check */ |
| d9b94f28 | 173 | #if defined(CONFIG_ENABLE_36BIT_PHYS) |
| 87163180 | 174 | ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ |
| d9b94f28 | 175 | #endif |
| 1b3e4044 | 176 | #ifndef CONFIG_E500MC |
| 87163180 | 177 | ori r0,r0,HID0_TBEN@l /* Enable Timebase */ |
| 1b3e4044 | 178 | #endif |
| 42d1f039 | 179 | mtspr HID0,r0 |
| 42d1f039 | 180 | |
| 0f060c3b | 181 | #ifndef CONFIG_E500MC |
| 61a21e98 | 182 | li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ |
| 42d1f039 | 183 | mtspr HID1,r0 |
| 0f060c3b | 184 | #endif |
| 42d1f039 WD |
185 | |
| 186 | /* Enable Branch Prediction */ | |
| 187 | #if defined(CONFIG_BTB) | |
| 188 | li r0,0x201 /* BBFI = 1, BPEN = 1 */ | |
| 189 | mtspr BUCSR,r0 | |
| 42d1f039 WD |
190 | #endif |
| 191 | ||
| 6d0f6bcf | 192 | #if defined(CONFIG_SYS_INIT_DBCR) |
| 42d1f039 WD |
193 | lis r1,0xffff |
| 194 | ori r1,r1,0xffff | |
| 0ac6f8b7 | 195 | mtspr DBSR,r1 /* Clear all status bits */ |
| 6d0f6bcf JCPV |
196 | lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ |
| 197 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l | |
| 0ac6f8b7 | 198 | mtspr DBCR0,r0 |
| 42d1f039 WD |
199 | #endif |
| 200 | ||
| 22b6dbc1 HW |
201 | #ifdef CONFIG_MPC8569 |
| 202 | #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) | |
| 203 | #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) | |
| 204 | ||
| 205 | /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to | |
| 206 | * use address space which is more than 12bits, and it must be done in | |
| 207 | * the 4K boot page. So we set this bit here. | |
| 208 | */ | |
| 209 | ||
| 210 | /* create a temp mapping TLB0[0] for LBCR */ | |
| 211 | lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h | |
| 212 | ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l | |
| 213 | ||
| 214 | lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h | |
| 215 | ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l | |
| 216 | ||
| 217 | lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h | |
| 218 | ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l | |
| 219 | ||
| 220 | lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, | |
| 221 | (MAS3_SX|MAS3_SW|MAS3_SR))@h | |
| 222 | ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, | |
| 223 | (MAS3_SX|MAS3_SW|MAS3_SR))@l | |
| 224 | ||
| 225 | mtspr MAS0,r6 | |
| 226 | mtspr MAS1,r7 | |
| 227 | mtspr MAS2,r8 | |
| 228 | mtspr MAS3,r9 | |
| 229 | isync | |
| 230 | msync | |
| 231 | tlbwe | |
| 232 | ||
| 233 | /* Set LBCR register */ | |
| 234 | lis r4,CONFIG_SYS_LBCR_ADDR@h | |
| 235 | ori r4,r4,CONFIG_SYS_LBCR_ADDR@l | |
| 236 | ||
| 237 | lis r5,CONFIG_SYS_LBC_LBCR@h | |
| 238 | ori r5,r5,CONFIG_SYS_LBC_LBCR@l | |
| 239 | stw r5,0(r4) | |
| 240 | isync | |
| 241 | ||
| 242 | /* invalidate this temp TLB */ | |
| 243 | lis r4,CONFIG_SYS_LBC_ADDR@h | |
| 244 | ori r4,r4,CONFIG_SYS_LBC_ADDR@l | |
| 245 | tlbivax 0,r4 | |
| 246 | isync | |
| 247 | ||
| 248 | #endif /* CONFIG_MPC8569 */ | |
| 249 | ||
| 87163180 KG |
250 | lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h |
| 251 | ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l | |
| 252 | ||
| 7da53351 MH |
253 | #ifndef CONFIG_SYS_RAMBOOT |
| 254 | /* create a temp mapping in AS=1 to the 4M boot window */ | |
| f51f07eb DL |
255 | lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h |
| 256 | ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l | |
| 87163180 | 257 | |
| f51f07eb DL |
258 | lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h |
| 259 | ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l | |
| 87163180 | 260 | |
| f51f07eb DL |
261 | /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ |
| 262 | lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h | |
| 263 | ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l | |
| 7da53351 MH |
264 | #else |
| 265 | /* | |
| 266 | * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main | |
| 267 | * image has been relocated to TEXT_BASE on the second stage. | |
| 268 | */ | |
| 269 | lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h | |
| 270 | ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l | |
| 271 | ||
| 272 | lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h | |
| 273 | ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l | |
| 274 | ||
| 275 | lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h | |
| 276 | ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l | |
| 277 | #endif | |
| 87163180 KG |
278 | |
| 279 | mtspr MAS0,r6 | |
| 280 | mtspr MAS1,r7 | |
| 281 | mtspr MAS2,r8 | |
| 282 | mtspr MAS3,r9 | |
| 283 | isync | |
| 284 | msync | |
| 285 | tlbwe | |
| 286 | ||
| 287 | /* create a temp mapping in AS=1 to the stack */ | |
| 288 | lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h | |
| 289 | ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l | |
| 290 | ||
| 291 | lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h | |
| 292 | ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l | |
| 293 | ||
| 6d0f6bcf JCPV |
294 | lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h |
| 295 | ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l | |
| 87163180 | 296 | |
| 6d0f6bcf JCPV |
297 | lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h |
| 298 | ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l | |
| 87163180 KG |
299 | |
| 300 | mtspr MAS0,r6 | |
| 301 | mtspr MAS1,r7 | |
| 302 | mtspr MAS2,r8 | |
| 303 | mtspr MAS3,r9 | |
| 304 | isync | |
| 305 | msync | |
| 306 | tlbwe | |
| 307 | ||
| 1b72dbec SW |
308 | lis r6,MSR_IS|MSR_DS@h |
| 309 | ori r6,r6,MSR_IS|MSR_DS@l | |
| 87163180 KG |
310 | lis r7,switch_as@h |
| 311 | ori r7,r7,switch_as@l | |
| 312 | ||
| 313 | mtspr SPRN_SRR0,r7 | |
| 314 | mtspr SPRN_SRR1,r6 | |
| 315 | rfi | |
| 316 | ||
| 317 | switch_as: | |
| 3db0bef5 KG |
318 | /* L1 DCache is used for initial RAM */ |
| 319 | ||
| 320 | /* Allocate Initial RAM in data cache. | |
| 321 | */ | |
| 6d0f6bcf JCPV |
322 | lis r3,CONFIG_SYS_INIT_RAM_ADDR@h |
| 323 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
| b009f3ec KG |
324 | mfspr r2, L1CFG0 |
| 325 | andi. r2, r2, 0x1ff | |
| 326 | /* cache size * 1024 / (2 * L1 line size) */ | |
| 327 | slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) | |
| 3db0bef5 KG |
328 | mtctr r2 |
| 329 | li r0,0 | |
| 330 | 1: | |
| 331 | dcbz r0,r3 | |
| 332 | dcbtls 0,r0,r3 | |
| 6d0f6bcf | 333 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
| 3db0bef5 KG |
334 | bdnz 1b |
| 335 | ||
| 61a21e98 | 336 | /* Jump out the last 4K page and continue to 'normal' start */ |
| 6d0f6bcf | 337 | #ifdef CONFIG_SYS_RAMBOOT |
| 61a21e98 | 338 | b _start_cont |
| 3db0bef5 KG |
339 | #else |
| 340 | /* Calculate absolute address in FLASH and jump there */ | |
| 341 | /*--------------------------------------------------------------*/ | |
| 6d0f6bcf JCPV |
342 | lis r3,CONFIG_SYS_MONITOR_BASE@h |
| 343 | ori r3,r3,CONFIG_SYS_MONITOR_BASE@l | |
| 3db0bef5 KG |
344 | addi r3,r3,_start_cont - _start + _START_OFFSET |
| 345 | mtlr r3 | |
| 1e701e70 | 346 | blr |
| 3db0bef5 | 347 | #endif |
| 61a21e98 | 348 | |
| 61a21e98 AF |
349 | .text |
| 350 | .globl _start | |
| 351 | _start: | |
| 352 | .long 0x27051956 /* U-BOOT Magic Number */ | |
| 353 | .globl version_string | |
| 354 | version_string: | |
| 355 | .ascii U_BOOT_VERSION | |
| 561858ee | 356 | .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" |
| 61a21e98 AF |
357 | .ascii CONFIG_IDENT_STRING, "\0" |
| 358 | ||
| 359 | .align 4 | |
| 360 | .globl _start_cont | |
| 361 | _start_cont: | |
| 42d1f039 | 362 | /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ |
| 6d0f6bcf JCPV |
363 | lis r1,CONFIG_SYS_INIT_RAM_ADDR@h |
| 364 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l | |
| 42d1f039 WD |
365 | |
| 366 | li r0,0 | |
| 367 | stwu r0,-4(r1) | |
| 368 | stwu r0,-4(r1) /* Terminate call chain */ | |
| 369 | ||
| 370 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
| 371 | lis r0,RESET_VECTOR@h /* Address of reset vector */ | |
| 61a21e98 | 372 | ori r0,r0,RESET_VECTOR@l |
| 42d1f039 WD |
373 | stwu r1,-8(r1) /* Save back chain and move SP */ |
| 374 | stw r0,+12(r1) /* Save return addr (underflow vect) */ | |
| 375 | ||
| 376 | GET_GOT | |
| 87163180 KG |
377 | bl cpu_init_early_f |
| 378 | ||
| 379 | /* switch back to AS = 0 */ | |
| 380 | lis r3,(MSR_CE|MSR_ME|MSR_DE)@h | |
| 381 | ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l | |
| 382 | mtmsr r3 | |
| 383 | isync | |
| 384 | ||
| 42d1f039 | 385 | bl cpu_init_f |
| 42d1f039 | 386 | bl board_init_f |
| 0ac6f8b7 | 387 | isync |
| 42d1f039 | 388 | |
| 7da53351 | 389 | #ifndef CONFIG_NAND_SPL |
| 61a21e98 | 390 | . = EXC_OFF_SYS_RESET |
| 42d1f039 WD |
391 | .globl _start_of_vectors |
| 392 | _start_of_vectors: | |
| 61a21e98 | 393 | |
| 42d1f039 | 394 | /* Critical input. */ |
| 61a21e98 AF |
395 | CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) |
| 396 | ||
| 397 | /* Machine check */ | |
| 398 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) | |
| 42d1f039 WD |
399 | |
| 400 | /* Data Storage exception. */ | |
| 401 | STD_EXCEPTION(0x0300, DataStorage, UnknownException) | |
| 402 | ||
| 403 | /* Instruction Storage exception. */ | |
| 404 | STD_EXCEPTION(0x0400, InstStorage, UnknownException) | |
| 405 | ||
| 406 | /* External Interrupt exception. */ | |
| 61a21e98 | 407 | STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) |
| 42d1f039 WD |
408 | |
| 409 | /* Alignment exception. */ | |
| 410 | . = 0x0600 | |
| 411 | Alignment: | |
| 02032e8f | 412 | EXCEPTION_PROLOG(SRR0, SRR1) |
| 42d1f039 WD |
413 | mfspr r4,DAR |
| 414 | stw r4,_DAR(r21) | |
| 415 | mfspr r5,DSISR | |
| 416 | stw r5,_DSISR(r21) | |
| 417 | addi r3,r1,STACK_FRAME_OVERHEAD | |
| 418 | li r20,MSR_KERNEL | |
| 419 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
| 420 | lwz r6,GOT(transfer_to_handler) | |
| 421 | mtlr r6 | |
| 422 | blrl | |
| 423 | .L_Alignment: | |
| 61a21e98 AF |
424 | .long AlignmentException - _start + _START_OFFSET |
| 425 | .long int_return - _start + _START_OFFSET | |
| 42d1f039 WD |
426 | |
| 427 | /* Program check exception */ | |
| 428 | . = 0x0700 | |
| 429 | ProgramCheck: | |
| 02032e8f | 430 | EXCEPTION_PROLOG(SRR0, SRR1) |
| 42d1f039 WD |
431 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 432 | li r20,MSR_KERNEL | |
| 433 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
| 434 | lwz r6,GOT(transfer_to_handler) | |
| 435 | mtlr r6 | |
| 436 | blrl | |
| 437 | .L_ProgramCheck: | |
| 61a21e98 AF |
438 | .long ProgramCheckException - _start + _START_OFFSET |
| 439 | .long int_return - _start + _START_OFFSET | |
| 42d1f039 WD |
440 | |
| 441 | /* No FPU on MPC85xx. This exception is not supposed to happen. | |
| 442 | */ | |
| 443 | STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) | |
| 42d1f039 | 444 | |
| 343117bf | 445 | . = 0x0900 |
| 42d1f039 WD |
446 | /* |
| 447 | * r0 - SYSCALL number | |
| 448 | * r3-... arguments | |
| 449 | */ | |
| 450 | SystemCall: | |
| 61a21e98 AF |
451 | addis r11,r0,0 /* get functions table addr */ |
| 452 | ori r11,r11,0 /* Note: this code is patched in trap_init */ | |
| 453 | addis r12,r0,0 /* get number of functions */ | |
| 343117bf WD |
454 | ori r12,r12,0 |
| 455 | ||
| 61a21e98 | 456 | cmplw 0,r0,r12 |
| 343117bf WD |
457 | bge 1f |
| 458 | ||
| 61a21e98 | 459 | rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ |
| 343117bf WD |
460 | add r11,r11,r0 |
| 461 | lwz r11,0(r11) | |
| 462 | ||
| 61a21e98 | 463 | li r20,0xd00-4 /* Get stack pointer */ |
| 343117bf | 464 | lwz r12,0(r20) |
| 61a21e98 | 465 | subi r12,r12,12 /* Adjust stack pointer */ |
| 343117bf | 466 | li r0,0xc00+_end_back-SystemCall |
| 61a21e98 | 467 | cmplw 0,r0,r12 /* Check stack overflow */ |
| 343117bf WD |
468 | bgt 1f |
| 469 | stw r12,0(r20) | |
| 470 | ||
| 471 | mflr r0 | |
| 472 | stw r0,0(r12) | |
| 473 | mfspr r0,SRR0 | |
| 474 | stw r0,4(r12) | |
| 475 | mfspr r0,SRR1 | |
| 476 | stw r0,8(r12) | |
| 477 | ||
| 478 | li r12,0xc00+_back-SystemCall | |
| 479 | mtlr r12 | |
| 480 | mtspr SRR0,r11 | |
| 481 | ||
| 482 | 1: SYNC | |
| 42d1f039 WD |
483 | rfi |
| 484 | _back: | |
| 485 | ||
| 343117bf WD |
486 | mfmsr r11 /* Disable interrupts */ |
| 487 | li r12,0 | |
| 488 | ori r12,r12,MSR_EE | |
| 489 | andc r11,r11,r12 | |
| 490 | SYNC /* Some chip revs need this... */ | |
| 491 | mtmsr r11 | |
| 42d1f039 WD |
492 | SYNC |
| 493 | ||
| 343117bf WD |
494 | li r12,0xd00-4 /* restore regs */ |
| 495 | lwz r12,0(r12) | |
| 42d1f039 | 496 | |
| 343117bf WD |
497 | lwz r11,0(r12) |
| 498 | mtlr r11 | |
| 499 | lwz r11,4(r12) | |
| 500 | mtspr SRR0,r11 | |
| 501 | lwz r11,8(r12) | |
| 502 | mtspr SRR1,r11 | |
| 42d1f039 | 503 | |
| 343117bf WD |
504 | addi r12,r12,12 /* Adjust stack pointer */ |
| 505 | li r20,0xd00-4 | |
| 506 | stw r12,0(r20) | |
| 42d1f039 WD |
507 | |
| 508 | SYNC | |
| 509 | rfi | |
| 510 | _end_back: | |
| 511 | ||
| 343117bf WD |
512 | STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) |
| 513 | STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) | |
| 514 | STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) | |
| 42d1f039 | 515 | |
| 343117bf WD |
516 | STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) |
| 517 | STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) | |
| 42d1f039 | 518 | |
| 343117bf | 519 | CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) |
| 42d1f039 | 520 | |
| 343117bf | 521 | .globl _end_of_vectors |
| 42d1f039 WD |
522 | _end_of_vectors: |
| 523 | ||
| 524 | ||
| 61a21e98 | 525 | . = . + (0x100 - ( . & 0xff )) /* align for debug */ |
| 42d1f039 WD |
526 | |
| 527 | /* | |
| 528 | * This code finishes saving the registers to the exception frame | |
| 529 | * and jumps to the appropriate handler for the exception. | |
| 530 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
| 531 | */ | |
| 532 | .globl transfer_to_handler | |
| 533 | transfer_to_handler: | |
| 534 | stw r22,_NIP(r21) | |
| 535 | lis r22,MSR_POW@h | |
| 536 | andc r23,r23,r22 | |
| 537 | stw r23,_MSR(r21) | |
| 538 | SAVE_GPR(7, r21) | |
| 539 | SAVE_4GPRS(8, r21) | |
| 540 | SAVE_8GPRS(12, r21) | |
| 541 | SAVE_8GPRS(24, r21) | |
| 542 | ||
| 543 | mflr r23 | |
| 544 | andi. r24,r23,0x3f00 /* get vector offset */ | |
| 545 | stw r24,TRAP(r21) | |
| 546 | li r22,0 | |
| 547 | stw r22,RESULT(r21) | |
| 548 | mtspr SPRG2,r22 /* r1 is now kernel sp */ | |
| 549 | ||
| 550 | lwz r24,0(r23) /* virtual address of handler */ | |
| 551 | lwz r23,4(r23) /* where to go when done */ | |
| 552 | mtspr SRR0,r24 | |
| 553 | mtspr SRR1,r20 | |
| 554 | mtlr r23 | |
| 555 | SYNC | |
| 556 | rfi /* jump to handler, enable MMU */ | |
| 557 | ||
| 558 | int_return: | |
| 559 | mfmsr r28 /* Disable interrupts */ | |
| 560 | li r4,0 | |
| 561 | ori r4,r4,MSR_EE | |
| 562 | andc r28,r28,r4 | |
| 563 | SYNC /* Some chip revs need this... */ | |
| 564 | mtmsr r28 | |
| 565 | SYNC | |
| 566 | lwz r2,_CTR(r1) | |
| 567 | lwz r0,_LINK(r1) | |
| 568 | mtctr r2 | |
| 569 | mtlr r0 | |
| 570 | lwz r2,_XER(r1) | |
| 571 | lwz r0,_CCR(r1) | |
| 572 | mtspr XER,r2 | |
| 573 | mtcrf 0xFF,r0 | |
| 574 | REST_10GPRS(3, r1) | |
| 575 | REST_10GPRS(13, r1) | |
| 576 | REST_8GPRS(23, r1) | |
| 577 | REST_GPR(31, r1) | |
| 578 | lwz r2,_NIP(r1) /* Restore environment */ | |
| 579 | lwz r0,_MSR(r1) | |
| 580 | mtspr SRR0,r2 | |
| 581 | mtspr SRR1,r0 | |
| 582 | lwz r0,GPR0(r1) | |
| 583 | lwz r2,GPR2(r1) | |
| 584 | lwz r1,GPR1(r1) | |
| 585 | SYNC | |
| 586 | rfi | |
| 587 | ||
| 588 | crit_return: | |
| 589 | mfmsr r28 /* Disable interrupts */ | |
| 590 | li r4,0 | |
| 591 | ori r4,r4,MSR_EE | |
| 592 | andc r28,r28,r4 | |
| 593 | SYNC /* Some chip revs need this... */ | |
| 594 | mtmsr r28 | |
| 595 | SYNC | |
| 596 | lwz r2,_CTR(r1) | |
| 597 | lwz r0,_LINK(r1) | |
| 598 | mtctr r2 | |
| 599 | mtlr r0 | |
| 600 | lwz r2,_XER(r1) | |
| 601 | lwz r0,_CCR(r1) | |
| 602 | mtspr XER,r2 | |
| 603 | mtcrf 0xFF,r0 | |
| 604 | REST_10GPRS(3, r1) | |
| 605 | REST_10GPRS(13, r1) | |
| 606 | REST_8GPRS(23, r1) | |
| 607 | REST_GPR(31, r1) | |
| 608 | lwz r2,_NIP(r1) /* Restore environment */ | |
| 609 | lwz r0,_MSR(r1) | |
| 61a21e98 AF |
610 | mtspr SPRN_CSRR0,r2 |
| 611 | mtspr SPRN_CSRR1,r0 | |
| 42d1f039 WD |
612 | lwz r0,GPR0(r1) |
| 613 | lwz r2,GPR2(r1) | |
| 614 | lwz r1,GPR1(r1) | |
| 615 | SYNC | |
| 616 | rfci | |
| 617 | ||
| 61a21e98 AF |
618 | mck_return: |
| 619 | mfmsr r28 /* Disable interrupts */ | |
| 620 | li r4,0 | |
| 621 | ori r4,r4,MSR_EE | |
| 622 | andc r28,r28,r4 | |
| 623 | SYNC /* Some chip revs need this... */ | |
| 624 | mtmsr r28 | |
| 625 | SYNC | |
| 626 | lwz r2,_CTR(r1) | |
| 627 | lwz r0,_LINK(r1) | |
| 628 | mtctr r2 | |
| 629 | mtlr r0 | |
| 630 | lwz r2,_XER(r1) | |
| 631 | lwz r0,_CCR(r1) | |
| 632 | mtspr XER,r2 | |
| 633 | mtcrf 0xFF,r0 | |
| 634 | REST_10GPRS(3, r1) | |
| 635 | REST_10GPRS(13, r1) | |
| 636 | REST_8GPRS(23, r1) | |
| 637 | REST_GPR(31, r1) | |
| 638 | lwz r2,_NIP(r1) /* Restore environment */ | |
| 639 | lwz r0,_MSR(r1) | |
| 640 | mtspr SPRN_MCSRR0,r2 | |
| 641 | mtspr SPRN_MCSRR1,r0 | |
| 642 | lwz r0,GPR0(r1) | |
| 643 | lwz r2,GPR2(r1) | |
| 644 | lwz r1,GPR1(r1) | |
| 645 | SYNC | |
| 646 | rfmci | |
| 647 | ||
| 42d1f039 WD |
648 | /* Cache functions. |
| 649 | */ | |
| 54e091d3 | 650 | .globl invalidate_icache |
| 42d1f039 WD |
651 | invalidate_icache: |
| 652 | mfspr r0,L1CSR1 | |
| 61a21e98 AF |
653 | ori r0,r0,L1CSR1_ICFI |
| 654 | msync | |
| 655 | isync | |
| 42d1f039 WD |
656 | mtspr L1CSR1,r0 |
| 657 | isync | |
| 61a21e98 | 658 | blr /* entire I cache */ |
| 42d1f039 | 659 | |
| 54e091d3 | 660 | .globl invalidate_dcache |
| 42d1f039 WD |
661 | invalidate_dcache: |
| 662 | mfspr r0,L1CSR0 | |
| 61a21e98 | 663 | ori r0,r0,L1CSR0_DCFI |
| 42d1f039 WD |
664 | msync |
| 665 | isync | |
| 666 | mtspr L1CSR0,r0 | |
| 667 | isync | |
| 668 | blr | |
| 669 | ||
| 670 | .globl icache_enable | |
| 671 | icache_enable: | |
| 672 | mflr r8 | |
| 673 | bl invalidate_icache | |
| 674 | mtlr r8 | |
| 675 | isync | |
| 676 | mfspr r4,L1CSR1 | |
| 677 | ori r4,r4,0x0001 | |
| 678 | oris r4,r4,0x0001 | |
| 679 | mtspr L1CSR1,r4 | |
| 680 | isync | |
| 681 | blr | |
| 682 | ||
| 683 | .globl icache_disable | |
| 684 | icache_disable: | |
| 685 | mfspr r0,L1CSR1 | |
| 61a21e98 AF |
686 | lis r3,0 |
| 687 | ori r3,r3,L1CSR1_ICE | |
| 688 | andc r0,r0,r3 | |
| 42d1f039 WD |
689 | mtspr L1CSR1,r0 |
| 690 | isync | |
| 691 | blr | |
| 692 | ||
| 693 | .globl icache_status | |
| 694 | icache_status: | |
| 695 | mfspr r3,L1CSR1 | |
| 61a21e98 | 696 | andi. r3,r3,L1CSR1_ICE |
| 42d1f039 WD |
697 | blr |
| 698 | ||
| 699 | .globl dcache_enable | |
| 700 | dcache_enable: | |
| 701 | mflr r8 | |
| 702 | bl invalidate_dcache | |
| 703 | mtlr r8 | |
| 704 | isync | |
| 705 | mfspr r0,L1CSR0 | |
| 706 | ori r0,r0,0x0001 | |
| 707 | oris r0,r0,0x0001 | |
| 708 | msync | |
| 709 | isync | |
| 710 | mtspr L1CSR0,r0 | |
| 711 | isync | |
| 712 | blr | |
| 713 | ||
| 714 | .globl dcache_disable | |
| 715 | dcache_disable: | |
| 61a21e98 AF |
716 | mfspr r3,L1CSR0 |
| 717 | lis r4,0 | |
| 718 | ori r4,r4,L1CSR0_DCE | |
| 719 | andc r3,r3,r4 | |
| 42d1f039 WD |
720 | mtspr L1CSR0,r0 |
| 721 | isync | |
| 722 | blr | |
| 723 | ||
| 724 | .globl dcache_status | |
| 725 | dcache_status: | |
| 726 | mfspr r3,L1CSR0 | |
| 61a21e98 | 727 | andi. r3,r3,L1CSR0_DCE |
| 42d1f039 WD |
728 | blr |
| 729 | ||
| 730 | .globl get_pir | |
| 731 | get_pir: | |
| 61a21e98 | 732 | mfspr r3,PIR |
| 42d1f039 WD |
733 | blr |
| 734 | ||
| 735 | .globl get_pvr | |
| 736 | get_pvr: | |
| 61a21e98 | 737 | mfspr r3,PVR |
| 42d1f039 WD |
738 | blr |
| 739 | ||
| 97d80fc3 WD |
740 | .globl get_svr |
| 741 | get_svr: | |
| 61a21e98 | 742 | mfspr r3,SVR |
| 97d80fc3 WD |
743 | blr |
| 744 | ||
| 42d1f039 WD |
745 | .globl wr_tcr |
| 746 | wr_tcr: | |
| 61a21e98 | 747 | mtspr TCR,r3 |
| 42d1f039 WD |
748 | blr |
| 749 | ||
| 750 | /*------------------------------------------------------------------------------- */ | |
| 751 | /* Function: in8 */ | |
| 752 | /* Description: Input 8 bits */ | |
| 753 | /*------------------------------------------------------------------------------- */ | |
| 754 | .globl in8 | |
| 755 | in8: | |
| 756 | lbz r3,0x0000(r3) | |
| 757 | blr | |
| 758 | ||
| 759 | /*------------------------------------------------------------------------------- */ | |
| 760 | /* Function: out8 */ | |
| 761 | /* Description: Output 8 bits */ | |
| 762 | /*------------------------------------------------------------------------------- */ | |
| 763 | .globl out8 | |
| 764 | out8: | |
| 765 | stb r4,0x0000(r3) | |
| 1487adbd | 766 | sync |
| 42d1f039 WD |
767 | blr |
| 768 | ||
| 769 | /*------------------------------------------------------------------------------- */ | |
| 770 | /* Function: out16 */ | |
| 771 | /* Description: Output 16 bits */ | |
| 772 | /*------------------------------------------------------------------------------- */ | |
| 773 | .globl out16 | |
| 774 | out16: | |
| 775 | sth r4,0x0000(r3) | |
| 1487adbd | 776 | sync |
| 42d1f039 WD |
777 | blr |
| 778 | ||
| 779 | /*------------------------------------------------------------------------------- */ | |
| 780 | /* Function: out16r */ | |
| 781 | /* Description: Byte reverse and output 16 bits */ | |
| 782 | /*------------------------------------------------------------------------------- */ | |
| 783 | .globl out16r | |
| 784 | out16r: | |
| 785 | sthbrx r4,r0,r3 | |
| 1487adbd | 786 | sync |
| 42d1f039 WD |
787 | blr |
| 788 | ||
| 789 | /*------------------------------------------------------------------------------- */ | |
| 790 | /* Function: out32 */ | |
| 791 | /* Description: Output 32 bits */ | |
| 792 | /*------------------------------------------------------------------------------- */ | |
| 793 | .globl out32 | |
| 794 | out32: | |
| 795 | stw r4,0x0000(r3) | |
| 1487adbd | 796 | sync |
| 42d1f039 WD |
797 | blr |
| 798 | ||
| 799 | /*------------------------------------------------------------------------------- */ | |
| 800 | /* Function: out32r */ | |
| 801 | /* Description: Byte reverse and output 32 bits */ | |
| 802 | /*------------------------------------------------------------------------------- */ | |
| 803 | .globl out32r | |
| 804 | out32r: | |
| 805 | stwbrx r4,r0,r3 | |
| 1487adbd | 806 | sync |
| 42d1f039 WD |
807 | blr |
| 808 | ||
| 809 | /*------------------------------------------------------------------------------- */ | |
| 810 | /* Function: in16 */ | |
| 811 | /* Description: Input 16 bits */ | |
| 812 | /*------------------------------------------------------------------------------- */ | |
| 813 | .globl in16 | |
| 814 | in16: | |
| 815 | lhz r3,0x0000(r3) | |
| 816 | blr | |
| 817 | ||
| 818 | /*------------------------------------------------------------------------------- */ | |
| 819 | /* Function: in16r */ | |
| 820 | /* Description: Input 16 bits and byte reverse */ | |
| 821 | /*------------------------------------------------------------------------------- */ | |
| 822 | .globl in16r | |
| 823 | in16r: | |
| 824 | lhbrx r3,r0,r3 | |
| 825 | blr | |
| 826 | ||
| 827 | /*------------------------------------------------------------------------------- */ | |
| 828 | /* Function: in32 */ | |
| 829 | /* Description: Input 32 bits */ | |
| 830 | /*------------------------------------------------------------------------------- */ | |
| 831 | .globl in32 | |
| 832 | in32: | |
| 833 | lwz 3,0x0000(3) | |
| 834 | blr | |
| 835 | ||
| 836 | /*------------------------------------------------------------------------------- */ | |
| 837 | /* Function: in32r */ | |
| 838 | /* Description: Input 32 bits and byte reverse */ | |
| 839 | /*------------------------------------------------------------------------------- */ | |
| 840 | .globl in32r | |
| 841 | in32r: | |
| 842 | lwbrx r3,r0,r3 | |
| 843 | blr | |
| 7da53351 | 844 | #endif /* !CONFIG_NAND_SPL */ |
| 42d1f039 | 845 | |
| 42d1f039 WD |
846 | /*------------------------------------------------------------------------------*/ |
| 847 | ||
| d30f9043 KG |
848 | /* |
| 849 | * void write_tlb(mas0, mas1, mas2, mas3, mas7) | |
| 850 | */ | |
| 851 | .globl write_tlb | |
| 852 | write_tlb: | |
| 853 | mtspr MAS0,r3 | |
| 854 | mtspr MAS1,r4 | |
| 855 | mtspr MAS2,r5 | |
| 856 | mtspr MAS3,r6 | |
| 857 | #ifdef CONFIG_ENABLE_36BIT_PHYS | |
| 858 | mtspr MAS7,r7 | |
| 859 | #endif | |
| 860 | li r3,0 | |
| 861 | #ifdef CONFIG_SYS_BOOK3E_HV | |
| 862 | mtspr MAS8,r3 | |
| 863 | #endif | |
| 864 | isync | |
| 865 | tlbwe | |
| 866 | msync | |
| 867 | isync | |
| 868 | blr | |
| 869 | ||
| 42d1f039 WD |
870 | /* |
| 871 | * void relocate_code (addr_sp, gd, addr_moni) | |
| 872 | * | |
| 873 | * This "function" does not return, instead it continues in RAM | |
| 874 | * after relocating the monitor code. | |
| 875 | * | |
| 876 | * r3 = dest | |
| 877 | * r4 = src | |
| 878 | * r5 = length in bytes | |
| 879 | * r6 = cachelinesize | |
| 880 | */ | |
| 881 | .globl relocate_code | |
| 882 | relocate_code: | |
| 61a21e98 AF |
883 | mr r1,r3 /* Set new stack pointer */ |
| 884 | mr r9,r4 /* Save copy of Init Data pointer */ | |
| 885 | mr r10,r5 /* Save copy of Destination Address */ | |
| 42d1f039 | 886 | |
| 61a21e98 | 887 | mr r3,r5 /* Destination Address */ |
| 6d0f6bcf JCPV |
888 | lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
| 889 | ori r4,r4,CONFIG_SYS_MONITOR_BASE@l | |
| 42d1f039 WD |
890 | lwz r5,GOT(__init_end) |
| 891 | sub r5,r5,r4 | |
| 6d0f6bcf | 892 | li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ |
| 42d1f039 WD |
893 | |
| 894 | /* | |
| 895 | * Fix GOT pointer: | |
| 896 | * | |
| 6d0f6bcf | 897 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address |
| 42d1f039 WD |
898 | * |
| 899 | * Offset: | |
| 900 | */ | |
| 61a21e98 | 901 | sub r15,r10,r4 |
| 42d1f039 WD |
902 | |
| 903 | /* First our own GOT */ | |
| 61a21e98 | 904 | add r14,r14,r15 |
| 42d1f039 | 905 | /* the the one used by the C code */ |
| 61a21e98 | 906 | add r30,r30,r15 |
| 42d1f039 WD |
907 | |
| 908 | /* | |
| 909 | * Now relocate code | |
| 910 | */ | |
| 911 | ||
| 912 | cmplw cr1,r3,r4 | |
| 913 | addi r0,r5,3 | |
| 914 | srwi. r0,r0,2 | |
| 915 | beq cr1,4f /* In place copy is not necessary */ | |
| 916 | beq 7f /* Protect against 0 count */ | |
| 917 | mtctr r0 | |
| 918 | bge cr1,2f | |
| 919 | ||
| 920 | la r8,-4(r4) | |
| 921 | la r7,-4(r3) | |
| 922 | 1: lwzu r0,4(r8) | |
| 923 | stwu r0,4(r7) | |
| 924 | bdnz 1b | |
| 925 | b 4f | |
| 926 | ||
| 927 | 2: slwi r0,r0,2 | |
| 928 | add r8,r4,r0 | |
| 929 | add r7,r3,r0 | |
| 930 | 3: lwzu r0,-4(r8) | |
| 931 | stwu r0,-4(r7) | |
| 932 | bdnz 3b | |
| 933 | ||
| 934 | /* | |
| 935 | * Now flush the cache: note that we must start from a cache aligned | |
| 936 | * address. Otherwise we might miss one cache line. | |
| 937 | */ | |
| 938 | 4: cmpwi r6,0 | |
| 939 | add r5,r3,r5 | |
| 940 | beq 7f /* Always flush prefetch queue in any case */ | |
| 941 | subi r0,r6,1 | |
| 942 | andc r3,r3,r0 | |
| 943 | mr r4,r3 | |
| 944 | 5: dcbst 0,r4 | |
| 945 | add r4,r4,r6 | |
| 946 | cmplw r4,r5 | |
| 947 | blt 5b | |
| 948 | sync /* Wait for all dcbst to complete on bus */ | |
| 949 | mr r4,r3 | |
| 950 | 6: icbi 0,r4 | |
| 951 | add r4,r4,r6 | |
| 952 | cmplw r4,r5 | |
| 953 | blt 6b | |
| 954 | 7: sync /* Wait for all icbi to complete on bus */ | |
| 955 | isync | |
| 956 | ||
| 7d314992 WD |
957 | /* |
| 958 | * Re-point the IVPR at RAM | |
| 959 | */ | |
| 960 | mtspr IVPR,r10 | |
| 99b0d285 | 961 | |
| 42d1f039 WD |
962 | /* |
| 963 | * We are done. Do not return, instead branch to second part of board | |
| 964 | * initialization, now running from RAM. | |
| 965 | */ | |
| 966 | ||
| 61a21e98 | 967 | addi r0,r10,in_ram - _start + _START_OFFSET |
| 42d1f039 WD |
968 | mtlr r0 |
| 969 | blr /* NEVER RETURNS! */ | |
| 61a21e98 | 970 | .globl in_ram |
| 42d1f039 WD |
971 | in_ram: |
| 972 | ||
| 973 | /* | |
| 974 | * Relocation Function, r14 point to got2+0x8000 | |
| 975 | * | |
| 976 | * Adjust got2 pointers, no need to check for 0, this code | |
| 977 | * already puts a few entries in the table. | |
| 978 | */ | |
| 979 | li r0,__got2_entries@sectoff@l | |
| 980 | la r3,GOT(_GOT2_TABLE_) | |
| 981 | lwz r11,GOT(_GOT2_TABLE_) | |
| 982 | mtctr r0 | |
| 983 | sub r11,r3,r11 | |
| 984 | addi r3,r3,-4 | |
| 985 | 1: lwzu r0,4(r3) | |
| afc3ba0f JT |
986 | cmpwi r0,0 |
| 987 | beq- 2f | |
| 42d1f039 WD |
988 | add r0,r0,r11 |
| 989 | stw r0,0(r3) | |
| afc3ba0f | 990 | 2: bdnz 1b |
| 42d1f039 WD |
991 | |
| 992 | /* | |
| 993 | * Now adjust the fixups and the pointers to the fixups | |
| 994 | * in case we need to move ourselves again. | |
| 995 | */ | |
| afc3ba0f | 996 | li r0,__fixup_entries@sectoff@l |
| 42d1f039 WD |
997 | lwz r3,GOT(_FIXUP_TABLE_) |
| 998 | cmpwi r0,0 | |
| 999 | mtctr r0 | |
| 1000 | addi r3,r3,-4 | |
| 1001 | beq 4f | |
| 1002 | 3: lwzu r4,4(r3) | |
| 1003 | lwzux r0,r4,r11 | |
| 1004 | add r0,r0,r11 | |
| 1005 | stw r10,0(r3) | |
| 1006 | stw r0,0(r4) | |
| 1007 | bdnz 3b | |
| 1008 | 4: | |
| 1009 | clear_bss: | |
| 1010 | /* | |
| 1011 | * Now clear BSS segment | |
| 1012 | */ | |
| 1013 | lwz r3,GOT(__bss_start) | |
| 1014 | lwz r4,GOT(_end) | |
| 1015 | ||
| 61a21e98 | 1016 | cmplw 0,r3,r4 |
| 42d1f039 WD |
1017 | beq 6f |
| 1018 | ||
| 61a21e98 | 1019 | li r0,0 |
| 42d1f039 | 1020 | 5: |
| 61a21e98 AF |
1021 | stw r0,0(r3) |
| 1022 | addi r3,r3,4 | |
| 1023 | cmplw 0,r3,r4 | |
| 42d1f039 WD |
1024 | bne 5b |
| 1025 | 6: | |
| 1026 | ||
| 61a21e98 AF |
1027 | mr r3,r9 /* Init Data pointer */ |
| 1028 | mr r4,r10 /* Destination Address */ | |
| 42d1f039 WD |
1029 | bl board_init_r |
| 1030 | ||
| 7da53351 | 1031 | #ifndef CONFIG_NAND_SPL |
| 42d1f039 WD |
1032 | /* |
| 1033 | * Copy exception vector code to low memory | |
| 1034 | * | |
| 1035 | * r3: dest_addr | |
| 1036 | * r7: source address, r8: end address, r9: target address | |
| 1037 | */ | |
| 343117bf | 1038 | .globl trap_init |
| 42d1f039 | 1039 | trap_init: |
| 61a21e98 AF |
1040 | lwz r7,GOT(_start_of_vectors) |
| 1041 | lwz r8,GOT(_end_of_vectors) | |
| 42d1f039 | 1042 | |
| 61a21e98 | 1043 | li r9,0x100 /* reset vector always at 0x100 */ |
| 42d1f039 | 1044 | |
| 61a21e98 | 1045 | cmplw 0,r7,r8 |
| 343117bf | 1046 | bgelr /* return if r7>=r8 - just in case */ |
| 42d1f039 | 1047 | |
| 343117bf | 1048 | mflr r4 /* save link register */ |
| 42d1f039 | 1049 | 1: |
| 61a21e98 AF |
1050 | lwz r0,0(r7) |
| 1051 | stw r0,0(r9) | |
| 1052 | addi r7,r7,4 | |
| 1053 | addi r9,r9,4 | |
| 1054 | cmplw 0,r7,r8 | |
| 343117bf | 1055 | bne 1b |
| 42d1f039 WD |
1056 | |
| 1057 | /* | |
| 1058 | * relocate `hdlr' and `int_return' entries | |
| 1059 | */ | |
| 61a21e98 | 1060 | li r7,.L_CriticalInput - _start + _START_OFFSET |
| 343117bf | 1061 | bl trap_reloc |
| 61a21e98 | 1062 | li r7,.L_MachineCheck - _start + _START_OFFSET |
| 343117bf | 1063 | bl trap_reloc |
| 61a21e98 | 1064 | li r7,.L_DataStorage - _start + _START_OFFSET |
| 343117bf | 1065 | bl trap_reloc |
| 61a21e98 | 1066 | li r7,.L_InstStorage - _start + _START_OFFSET |
| 343117bf | 1067 | bl trap_reloc |
| 61a21e98 | 1068 | li r7,.L_ExtInterrupt - _start + _START_OFFSET |
| 343117bf | 1069 | bl trap_reloc |
| 61a21e98 | 1070 | li r7,.L_Alignment - _start + _START_OFFSET |
| 343117bf | 1071 | bl trap_reloc |
| 61a21e98 | 1072 | li r7,.L_ProgramCheck - _start + _START_OFFSET |
| 343117bf | 1073 | bl trap_reloc |
| 61a21e98 | 1074 | li r7,.L_FPUnavailable - _start + _START_OFFSET |
| 343117bf | 1075 | bl trap_reloc |
| 61a21e98 AF |
1076 | li r7,.L_Decrementer - _start + _START_OFFSET |
| 1077 | bl trap_reloc | |
| 1078 | li r7,.L_IntervalTimer - _start + _START_OFFSET | |
| 1079 | li r8,_end_of_vectors - _start + _START_OFFSET | |
| 42d1f039 | 1080 | 2: |
| 343117bf | 1081 | bl trap_reloc |
| 61a21e98 AF |
1082 | addi r7,r7,0x100 /* next exception vector */ |
| 1083 | cmplw 0,r7,r8 | |
| 343117bf WD |
1084 | blt 2b |
| 1085 | ||
| 1086 | lis r7,0x0 | |
| 61a21e98 | 1087 | mtspr IVPR,r7 |
| 42d1f039 | 1088 | |
| 343117bf | 1089 | mtlr r4 /* restore link register */ |
| 42d1f039 WD |
1090 | blr |
| 1091 | ||
| 1092 | /* | |
| 1093 | * Function: relocate entries for one exception vector | |
| 1094 | */ | |
| 1095 | trap_reloc: | |
| 61a21e98 AF |
1096 | lwz r0,0(r7) /* hdlr ... */ |
| 1097 | add r0,r0,r3 /* ... += dest_addr */ | |
| 1098 | stw r0,0(r7) | |
| 42d1f039 | 1099 | |
| 61a21e98 AF |
1100 | lwz r0,4(r7) /* int_return ... */ |
| 1101 | add r0,r0,r3 /* ... += dest_addr */ | |
| 1102 | stw r0,4(r7) | |
| 42d1f039 WD |
1103 | |
| 1104 | blr | |
| 1105 | ||
| 42d1f039 WD |
1106 | .globl unlock_ram_in_cache |
| 1107 | unlock_ram_in_cache: | |
| 1108 | /* invalidate the INIT_RAM section */ | |
| a38a5b6e KG |
1109 | lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h |
| 1110 | ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l | |
| b009f3ec KG |
1111 | mfspr r4,L1CFG0 |
| 1112 | andi. r4,r4,0x1ff | |
| 1113 | slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) | |
| 61a21e98 | 1114 | mtctr r4 |
| 2b22fa4b | 1115 | 1: dcbi r0,r3 |
| 6d0f6bcf | 1116 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
| 42d1f039 | 1117 | bdnz 1b |
| 2b22fa4b | 1118 | sync |
| 21fae8b2 AF |
1119 | |
| 1120 | /* Invalidate the TLB entries for the cache */ | |
| 6d0f6bcf JCPV |
1121 | lis r3,CONFIG_SYS_INIT_RAM_ADDR@h |
| 1122 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
| 21fae8b2 AF |
1123 | tlbivax 0,r3 |
| 1124 | addi r3,r3,0x1000 | |
| 1125 | tlbivax 0,r3 | |
| 1126 | addi r3,r3,0x1000 | |
| 1127 | tlbivax 0,r3 | |
| 1128 | addi r3,r3,0x1000 | |
| 1129 | tlbivax 0,r3 | |
| 42d1f039 WD |
1130 | isync |
| 1131 | blr | |
| 54e091d3 KG |
1132 | |
| 1133 | .globl flush_dcache | |
| 1134 | flush_dcache: | |
| 1135 | mfspr r3,SPRN_L1CFG0 | |
| 1136 | ||
| 1137 | rlwinm r5,r3,9,3 /* Extract cache block size */ | |
| 1138 | twlgti r5,1 /* Only 32 and 64 byte cache blocks | |
| 1139 | * are currently defined. | |
| 1140 | */ | |
| 1141 | li r4,32 | |
| 1142 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - | |
| 1143 | * log2(number of ways) | |
| 1144 | */ | |
| 1145 | slw r5,r4,r5 /* r5 = cache block size */ | |
| 1146 | ||
| 1147 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ | |
| 1148 | mulli r7,r7,13 /* An 8-way cache will require 13 | |
| 1149 | * loads per set. | |
| 1150 | */ | |
| 1151 | slw r7,r7,r6 | |
| 1152 | ||
| 1153 | /* save off HID0 and set DCFA */ | |
| 1154 | mfspr r8,SPRN_HID0 | |
| 1155 | ori r9,r8,HID0_DCFA@l | |
| 1156 | mtspr SPRN_HID0,r9 | |
| 1157 | isync | |
| 1158 | ||
| 1159 | lis r4,0 | |
| 1160 | mtctr r7 | |
| 1161 | ||
| 1162 | 1: lwz r3,0(r4) /* Load... */ | |
| 1163 | add r4,r4,r5 | |
| 1164 | bdnz 1b | |
| 1165 | ||
| 1166 | msync | |
| 1167 | lis r4,0 | |
| 1168 | mtctr r7 | |
| 1169 | ||
| 1170 | 1: dcbf 0,r4 /* ...and flush. */ | |
| 1171 | add r4,r4,r5 | |
| 1172 | bdnz 1b | |
| 1173 | ||
| 1174 | /* restore HID0 */ | |
| 1175 | mtspr SPRN_HID0,r8 | |
| 1176 | isync | |
| 1177 | ||
| 1178 | blr | |
| 26f4cdba KG |
1179 | |
| 1180 | .globl setup_ivors | |
| 1181 | setup_ivors: | |
| 1182 | ||
| 1183 | #include "fixed_ivor.S" | |
| 1184 | blr | |
| 7da53351 | 1185 | #endif /* !CONFIG_NAND_SPL */ |