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[people/ms/u-boot.git] / cpu / mpc8xx / scc.c
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ed247f48
WD		 1/*
2 * File: scc.c
3 * Description:
4 * Basic ET HW initialization and packet RX/TX routines
5 *
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
8 */
9
10/*
11 * MPC823 <-> MC68160 Connections:
12 *
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
15 *
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
25 *
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
32 *
33 */
34
35#include <common.h>
36#include <malloc.h>
37#include <commproc.h>
38#include <net.h>
39#include <command.h>
40
41#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
42
43/* Ethernet Transmit and Receive Buffers */
44#define DBUF_LENGTH 1520
45
46#define TX_BUF_CNT 2
47
48#define TOUT_LOOP 100
49
50static char txbuf[DBUF_LENGTH];
51
52static uint rxIdx; /* index of the current RX buffer */
53static uint txIdx; /* index of the current TX buffer */
54
55/*
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
59 */
60
61typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
64} RTXBD;
65
66static RTXBD *rtx;
67
68static int scc_send(struct eth_device* dev, volatile void *packet, int length);
69static int scc_recv(struct eth_device* dev);
70static int scc_init (struct eth_device* dev, bd_t * bd);
71static void scc_halt(struct eth_device* dev);
72
73int scc_initialize(bd_t *bis)
74{
75 struct eth_device* dev;
76
77 dev = (struct eth_device*) malloc(sizeof *dev);
7f6c2cbc 78 memset(dev, 0, sizeof *dev);
ed247f48
WD		 79
80 sprintf(dev->name, "SCC ETHERNET");
81 dev->iobase = 0;
82 dev->priv = 0;
83 dev->init = scc_init;
84 dev->halt = scc_halt;
85 dev->send = scc_send;
86 dev->recv = scc_recv;
87
88 eth_register(dev);
89
90 return 1;
91}
92
93static int scc_send(struct eth_device* dev, volatile void *packet, int length)
94{
95 int i, j=0;
96#if 0
97 volatile char *in, *out;
98#endif
99
100 /* section 16.9.23.3
101 * Wait for ready
102 */
103#if 0
104 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
105 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
106 in = packet;
107 for(i = 0; i < length; i++) {
108 *out++ = *in++;
109 }
110 rtx->txbd[txIdx].cbd_datlen = length;
111 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
112 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
113
114#ifdef ET_DEBUG
115 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
116#endif
117 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
118
119 /* wrap around buffer index when necessary */
120 if (txIdx >= TX_BUF_CNT) txIdx = 0;
121#endif
122
123 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
124 udelay (1); /* will also trigger Wd if needed */
125 j++;
126 }
127 if (j>=TOUT_LOOP) printf("TX not ready\n");
128 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
129 rtx->txbd[txIdx].cbd_datlen = length;
130 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
131 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
132 udelay (1); /* will also trigger Wd if needed */
133 j++;
134 }
135 if (j>=TOUT_LOOP) printf("TX timeout\n");
136#ifdef ET_DEBUG
137 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
138#endif
139 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
140 return i;
141}
142
143static int scc_recv(struct eth_device* dev)
144{
145 int length;
146
147 for (;;) {
148 /* section 16.9.23.2 */
149 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
150 length = -1;
151 break; /* nothing received - leave for() loop */
152 }
153
154 length = rtx->rxbd[rxIdx].cbd_datlen;
155
156 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
157#ifdef ET_DEBUG
158 printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
159#endif
160 } else {
161 /* Pass the packet up to the protocol layers. */
162 NetReceive(NetRxPackets[rxIdx], length - 4);
163 }
164
165
166 /* Give the buffer back to the SCC. */
167 rtx->rxbd[rxIdx].cbd_datlen = 0;
168
169 /* wrap around buffer index when necessary */
170 if ((rxIdx + 1) >= PKTBUFSRX) {
8bde7f77 171 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
ed247f48
WD		 172 rxIdx = 0;
173 } else {
8bde7f77 174 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
ed247f48
WD		 175 rxIdx++;
176 }
177 }
178 return length;
179}
180
181/**************************************************************
182 *
183 * SCC Ethernet Initialization Routine
184 *
185 *************************************************************/
186
187static int scc_init(struct eth_device* dev, bd_t *bis)
188{
189
190 int i;
191 scc_enet_t *pram_ptr;
192
193 volatile immap_t *immr = (immap_t *)CFG_IMMR;
194
195#if defined(CONFIG_FADS)
196#if defined(CONFIG_MPC860T)
197 /* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals. */
198 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
199 *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL;
200 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
201#else
202 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP|BCSR4_MODEM_EN);
203 *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL|BCSR4_DATA_VOICE;
204 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
205#endif
206#endif
207
208 pram_ptr = (scc_enet_t *)&(immr->im_cpm.cp_dparam[PROFF_ENET]);
209
210 rxIdx = 0;
211 txIdx = 0;
212
213#ifdef CFG_ALLOC_DPRAM
214 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
8bde7f77 215 dpram_alloc_align(sizeof(RTXBD), 8));
ed247f48
WD		 216#else
217 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
218#endif /* 0 */
219
220#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
221 /* Configure port A pins for Txd and Rxd.
222 */
223 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
224 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
225 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
226#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
227 /* Configure port B pins for Txd and Rxd.
228 */
229 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
230 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
231 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
232#else
233#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
234#endif
235
236#if defined(PC_ENET_LBK)
237 /* Configure port C pins to disable External Loopback
238 */
239 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
240 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
241 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
242 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
243#endif /* PC_ENET_LBK */
244
245 /* Configure port C pins to enable CLSN and RENA.
246 */
247 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
248 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
249 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
250
251 /* Configure port A for TCLK and RCLK.
252 */
253 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
254 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
255
256 /*
257 * Configure Serial Interface clock routing -- see section 16.7.5.3
258 * First, clear all SCC bits to zero, then set the ones we want.
259 */
260
261 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
262 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
263
264
265 /*
266 * Initialize SDCR -- see section 16.9.23.7
267 * SDMA configuration register
268 */
269 immr->im_siu_conf.sc_sdcr = 0x01;
270
271
272 /*
273 * Setup SCC Ethernet Parameter RAM
274 */
275
276 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
277 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
278
279 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
280
281 pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
282 pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
283
284 /*
285 * Setup Receiver Buffer Descriptors (13.14.24.18)
286 * Settings:
287 * Empty, Wrap
288 */
289
290 for (i = 0; i < PKTBUFSRX; i++)
291 {
292 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
293 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
294 rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
295 }
296
297 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
298
299 /*
300 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
301 * Settings:
302 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
303 */
304
305 for (i = 0; i < TX_BUF_CNT; i++)
306 {
307 rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
308 rtx->txbd[i].cbd_datlen = 0; /* Reset */
309 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
310 }
311
312 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
313
314 /*
315 * Enter Command: Initialize Rx Params for SCC
316 */
317
318 do { /* Spin until ready to issue command */
319 __asm__ ("eieio");
320 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
321 /* Issue command */
322 immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
323 do { /* Spin until command processed */
324 __asm__ ("eieio");
325 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
326
327 /*
328 * Ethernet Specific Parameter RAM
329 * see table 13-16, pg. 660,
330 * pg. 681 (example with suggested settings)
331 */
332
333 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
334 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
335 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
336 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
337 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
338 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
339
340 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
341 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
342 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
343
344 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
345 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
346
347 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
348 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
349 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
350 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
351
352#define ea eth_get_dev()->enetaddr
353 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
354 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
355 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
356#undef ea
357
358 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
359 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
360 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
361 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
362 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
363 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
364 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
365 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
366
367 /*
368 * Enter Command: Initialize Tx Params for SCC
369 */
370
371 do { /* Spin until ready to issue command */
372 __asm__ ("eieio");
373 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
374 /* Issue command */
375 immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
376 do { /* Spin until command processed */
377 __asm__ ("eieio");
378 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
379
380 /*
381 * Mask all Events in SCCM - we use polling mode
382 */
383 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
384
385 /*
386 * Clear Events in SCCE -- Clear bits by writing 1's
387 */
388
389 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
390
391
392 /*
393 * Initialize GSMR High 32-Bits
394 * Settings: Normal Mode
395 */
396
397 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
398
399 /*
400 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
401 * Settings:
402 * TCI = Invert
403 * TPL = 48 bits
404 * TPP = Repeating 10's
405 * MODE = Ethernet
406 */
407
408 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \
8bde7f77 409 SCC_GSMRL_TPL_48 | \
ed247f48
WD		 410 SCC_GSMRL_TPP_10 | \
411 SCC_GSMRL_MODE_ENET);
412
413 /*
414 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
415 */
416
417 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
418
419 /*
420 * Initialize the PSMR
421 * Settings:
422 * CRC = 32-Bit CCITT
423 * NIB = Begin searching for SFD 22 bits after RENA
424 * FDE = Full Duplex Enable
425 * LPB = Loopback Enable (Needed when FDE is set)
426 * BRO = Reject broadcast packets
427 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
428 */
429 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
430 SCC_PSMR_NIB22 |
431#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
432 SCC_PSMR_FDE |
433 SCC_PSMR_LPB |
434#endif
435#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
436 SCC_PSMR_BRO |
437#endif
438#if defined(CONFIG_SCC_ENET_PROMISCOUS)
439 SCC_PSMR_PRO |
440#endif
441 0;
442
443 /*
444 * Configure Ethernet TENA Signal
445 */
446
447#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
448 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
449 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
450#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
451 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
452 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
453#else
454#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
455#endif
456
457#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
458 /*
459 * Port C is used to control the PHY,MC68160.
460 */
461 immr->im_ioport.iop_pcdir |=
462 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
463
464 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
465 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
466 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
467#endif /* MPC860ADS */
468
469#if defined(CONFIG_AMX860)
470 /*
471 * Port B is used to control the PHY,MC68160.
472 */
473 immr->im_cpm.cp_pbdir |=
8bde7f77 474 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
ed247f48
WD		 475
476 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
477 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
478
479 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
480 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
481#endif /* AMX860 */
482
483#ifdef CONFIG_RPXCLASSIC
484 *((uchar *)BCSR0) &= ~BCSR0_ETHLPBK;
485 *((uchar *)BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
486#endif
487
488#ifdef CONFIG_RPXLITE
489 *((uchar *)BCSR0) |= BCSR0_ETHEN ;
490#endif
491
492#ifdef CONFIG_MBX
493 board_ether_init();
494#endif
495
496#if defined(CONFIG_NETVIA)
993cad93
WD		 497#if defined(PA_ENET_PDN)
498 immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
499 immr->im_ioport.iop_padir |= PA_ENET_PDN;
500 immr->im_ioport.iop_padat |= PA_ENET_PDN;
501#elif defined(PB_ENET_PDN)
ed247f48
WD		 502 immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
503 immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
504 immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
505#elif defined(PC_ENET_PDN)
993cad93
WD		 506 immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
507 immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
508 immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
509#elif defined(PD_ENET_PDN)
510 immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
511 immr->im_ioport.iop_pddir |= PD_ENET_PDN;
512 immr->im_ioport.iop_pddat |= PD_ENET_PDN;
ed247f48
WD		 513#endif
514#endif
515
516 /*
517 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
518 */
519
520 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
521
522 /*
523 * Work around transmit problem with first eth packet
524 */
525#if defined (CONFIG_FADS)
526 udelay(10000); /* wait 10 ms */
527#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
528 udelay(100000); /* wait 100 ms */
529#endif
530
531 return 1;
532}
533
534
ed247f48
WD		 535static void scc_halt(struct eth_device* dev)
536{
537 volatile immap_t *immr = (immap_t *)CFG_IMMR;
538 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
539}
540
541#if 0
542void restart(void)
543{
544 volatile immap_t *immr = (immap_t *)CFG_IMMR;
545 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
546}
547#endif
548
549#endif /* CFG_CMD_NET, SCC_ENET */
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