[people/ms/u-boot.git] / cpu / mpc8xx / start.S

/*
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*  U-Boot - Startup Code for PowerPC based Embedded Boards
 *
 *
 *  The processor starts at 0x00000100 and the code is executed
 *  from flash. The code is organized to be at an other address
 *  in memory, but as long we don't jump around before relocating.
 *  board_init lies at a quite high address and when the cpu has
 *  jumped there, everything is ok.
 *  This works because the cpu gives the FLASH (CS0) the whole
 *  address space at startup, and board_init lies as a echo of
 *  the flash somewhere up there in the memorymap.
 *
 *  board_init will change CS0 to be positioned at the correct
 *  address and (s)dram will be positioned at address 0
 */
#include <config.h>
#include <mpc8xx.h>
#include <version.h>

#define CONFIG_8xx 1		/* needed for Linux kernel header files */
#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING ""
#endif

/* We don't want the  MMU yet.
*/
#undef	MSR_KERNEL
#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */

/*
 * Set up GOT: Global Offset Table
 *
 * Use r14 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
#if defined(CONFIG_ICU862)
	GOT_ENTRY(environment)
#endif
	END_GOT

/*
 * r3 - 1st arg to board_init(): IMMP pointer
 * r4 - 2nd arg to board_init(): boot flag
 */
	.text
	.long	0x27051956		/* U-Boot Magic Number			*/
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

	. = EXC_OFF_SYS_RESET
	.globl	_start
_start:
	lis	r3, CFG_IMMR@h		/* position IMMR */
	mtspr	638, r3
	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH	*/
	b	boot_cold

	. = EXC_OFF_SYS_RESET + 0x10

	.globl	_start_warm
_start_warm:
	li	r21, BOOTFLAG_WARM	/* Software reboot			*/
	b	boot_warm

boot_cold:
boot_warm:

	/* Initialize machine status; enable machine check interrupt		*/
	/*----------------------------------------------------------------------*/
	li	r3, MSR_KERNEL		/* Set ME, RI flags */
	mtmsr	r3
	mtspr	SRR1, r3		/* Make SRR1 match MSR */

	mfspr	r3, ICR			/* clear Interrupt Cause Register */

	/* Initialize debug port registers					*/
	/*----------------------------------------------------------------------*/
	xor	r0, r0, r0		/* Clear R0 */
	mtspr	LCTRL1, r0		/* Initialize debug port regs */
	mtspr	LCTRL2, r0
	mtspr	COUNTA, r0
	mtspr	COUNTB, r0

	/* Reset the caches							*/
	/*----------------------------------------------------------------------*/

	mfspr	r3, IC_CST		/* Clear error bits */
	mfspr	r3, DC_CST

	lis	r3, IDC_UNALL@h		/* Unlock all */
	mtspr	IC_CST, r3
	mtspr	DC_CST, r3

	lis	r3, IDC_INVALL@h	/* Invalidate all */
	mtspr	IC_CST, r3
	mtspr	DC_CST, r3

	lis	r3, IDC_DISABLE@h	/* Disable data cache */
	mtspr	DC_CST, r3

#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
					/* On IP860 and PCU E,
					 * we cannot enable IC yet
					 */
	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
#endif
	mtspr	IC_CST, r3

	/* invalidate all tlb's							*/
	/*----------------------------------------------------------------------*/

	tlbia
	isync

	/*
	 * Calculate absolute address in FLASH and jump there
	 *----------------------------------------------------------------------*/

	lis	r3, CFG_MONITOR_BASE@h
	ori	r3, r3, CFG_MONITOR_BASE@l
	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r3
	blr

in_flash:

	/* initialize some SPRs that are hard to access from C			*/
	/*----------------------------------------------------------------------*/

	lis	r3, CFG_IMMR@h		/* pass IMMR as arg1 to C routine */
	ori	r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
	/* Note: R0 is still 0 here */
	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/

	/*
	 * Disable serialized ifetch and show cycles
	 * (i.e. set processor to normal mode).
	 * This is also a silicon bug workaround, see errata
	 */

	li	r2, 0x0007
	mtspr	ICTRL, r2

	/* Set up debug mode entry */

	lis	r2, CFG_DER@h
	ori	r2, r2, CFG_DER@l
	mtspr	DER, r2

	/* let the C-code set up the rest					*/
	/*									*/
	/* Be careful to keep code relocatable !				*/
	/*----------------------------------------------------------------------*/

	GET_GOT			/* initialize GOT access			*/

	/* r3: IMMR */
	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/

	mr	r3, r21
	/* r3: BOOTFLAG */
	bl	board_init_f	/* run 1st part of board init code (from Flash) */


	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_Alignment:
	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_ProgramCheck:
	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

	/* No FPU on MPC8xx.  This exception is not supposed to happen.
	*/
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	STD_EXCEPTION(0xd00, SingleStep, UnknownException)

	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)

	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
	 * for all unimplemented and illegal instructions.
	 */
	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)

	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)

	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)

	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)


	.globl	_end_of_vectors
_end_of_vectors:


	. = 0x2000

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRG2,r22		/* r1 is now kernel sp */
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28			/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC				/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)		/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/* Cache functions.
*/
	.globl	icache_enable
icache_enable:
	SYNC
	lis	r3, IDC_INVALL@h
	mtspr	IC_CST, r3
	lis	r3, IDC_ENABLE@h
	mtspr	IC_CST, r3
	blr

	.globl	icache_disable
icache_disable:
	SYNC
	lis	r3, IDC_DISABLE@h
	mtspr	IC_CST, r3
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, IC_CST
	srwi	r3, r3, 31	/* >>31 => select bit 0 */
	blr

	.globl	dcache_enable
dcache_enable:
#if 0
	SYNC
#endif
#if 1
	lis	r3, 0x0400		/* Set cache mode with MMU off */
	mtspr	MD_CTR, r3
#endif

	lis	r3, IDC_INVALL@h
	mtspr	DC_CST, r3
#if 0
	lis	r3, DC_SFWT@h
	mtspr	DC_CST, r3
#endif
	lis	r3, IDC_ENABLE@h
	mtspr	DC_CST, r3
	blr

	.globl	dcache_disable
dcache_disable:
	SYNC
	lis	r3, IDC_DISABLE@h
	mtspr	DC_CST, r3
	lis	r3, IDC_INVALL@h
	mtspr	DC_CST, r3
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, DC_CST
	srwi	r3, r3, 31	/* >>31 => select bit 0 */
	blr

	.globl	dc_read
dc_read:
	mtspr	DC_ADR, r3
	mfspr	r3, DC_DAT
	blr

/*
 * unsigned int get_immr (unsigned int mask)
 *
 * return (mask ? (IMMR & mask) : IMMR);
 */
	.globl	get_immr
get_immr:
	mr	r4,r3		/* save mask */
	mfspr	r3, IMMR	/* IMMR */
	cmpwi	0,r4,0		/* mask != 0 ? */
	beq	4f
	and	r3,r3,r4	/* IMMR & mask */
4:
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr


	.globl wr_ic_cst
wr_ic_cst:
	mtspr	IC_CST, r3
	blr

	.globl rd_ic_cst
rd_ic_cst:
	mfspr	r3, IC_CST
	blr

	.globl wr_ic_adr
wr_ic_adr:
	mtspr	IC_ADR, r3
	blr


	.globl wr_dc_cst
wr_dc_cst:
	mtspr	DC_CST, r3
	blr

	.globl rd_dc_cst
rd_dc_cst:
	mfspr	r3, DC_CST
	blr

	.globl wr_dc_adr
wr_dc_adr:
	mtspr	DC_ADR, r3
	blr

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer		*/
	mr	r9,  r4		/* Save copy of Global Data pointer	*/
	mr	r10, r5		/* Save copy of Destination Address	*/

	mr	r3,  r5				/* Destination Address	*/
	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
	ori	r4, r4, CFG_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4
	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r14, r14, r15
	/* then the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */

	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary	*/
	beq	7f		/* Protect against 0 count		*/
	mtctr	r0
	bge	cr1,2f

	la	r8,-4(r4)
	la	r7,-4(r3)
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b
	b	4f

2:	slwi	r0,r0,2
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	dcbst	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	icbi	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	6b
7:	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */

	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:

	/*
	 * Relocation Function, r14 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	add	r0,r0,r11
	stw	r0,0(r3)
	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
2:	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	add	r0,r0,r11
	stw	r10,0(r3)
	stw	r0,0(r4)
	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
#if defined(CONFIG_ICU862)
	/*
	 * For the FADS - the environment is the very last item in flash.
	 * The real .bss stops just before environment starts, so only
	 * clear up to that point.
	 */
	lwz	r4,GOT(environment)
#else
	lwz	r4,GOT(_end)
#endif

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:

	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100		/* reset vector always at 0x100 */

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */

	mflr	r4			/* save link register		*/
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	4b

	mtlr	r4			/* restore link register	*/
	blr

	/*
	 * Function: relocate entries for one exception vector
	 */
trap_reloc:
	lwz	r0, 0(r7)		/* hdlr ...			*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 0(r7)

	lwz	r0, 4(r7)		/* int_return ...		*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 4(r7)

	sync
	isync

	blr
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	4	* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/* U-Boot - Startup Code for PowerPC based Embedded Boards
	26	*
	27	*
	28	* The processor starts at 0x00000100 and the code is executed
	29	* from flash. The code is organized to be at an other address
	30	* in memory, but as long we don't jump around before relocating.
	31	* board_init lies at a quite high address and when the cpu has
	32	* jumped there, everything is ok.
	33	* This works because the cpu gives the FLASH (CS0) the whole
	34	* address space at startup, and board_init lies as a echo of
	35	* the flash somewhere up there in the memorymap.
	36	*
	37	* board_init will change CS0 to be positioned at the correct
	38	* address and (s)dram will be positioned at address 0
	39	*/
	40	#include <config.h>
	41	#include <mpc8xx.h>
	42	#include <version.h>
	43
	44	#define CONFIG_8xx 1 /* needed for Linux kernel header files */
	45	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	46
	47	#include <ppc_asm.tmpl>
	48	#include <ppc_defs.h>
	49
	50	#include <asm/cache.h>
	51	#include <asm/mmu.h>
	52
	53	#ifndef CONFIG_IDENT_STRING
	54	#define CONFIG_IDENT_STRING ""
	55	#endif
	56
	57	/* We don't want the MMU yet.
	58	*/
	59	#undef MSR_KERNEL
	60	#define MSR_KERNEL ( MSR_ME \| MSR_RI ) /* Machine Check and Recoverable Interr. */
	61
	62	/*
	63	* Set up GOT: Global Offset Table
	64	*
65	* Use r14 to access the GOT
66	*/
67	START_GOT
68	GOT_ENTRY(_GOT2_TABLE_)
69	GOT_ENTRY(_FIXUP_TABLE_)
70
71	GOT_ENTRY(_start)
72	GOT_ENTRY(_start_of_vectors)
73	GOT_ENTRY(_end_of_vectors)
74	GOT_ENTRY(transfer_to_handler)
75
3b57fe0a	76	GOT_ENTRY(__init_end)
5b1d7137	77	GOT_ENTRY(_end)
5d232d0e	78	GOT_ENTRY(__bss_start)
1f4bb37d	79	#if defined(CONFIG_ICU862)
5b1d7137 WD	80	GOT_ENTRY(environment)
	81	#endif
	82	END_GOT
	83
	84	/*
	85	* r3 - 1st arg to board_init(): IMMP pointer
	86	* r4 - 2nd arg to board_init(): boot flag
	87	*/
	88	.text
	89	.long 0x27051956 /* U-Boot Magic Number */
	90	.globl version_string
	91	version_string:
	92	.ascii U_BOOT_VERSION
	93	.ascii " (", __DATE__, " - ", __TIME__, ")"
	94	.ascii CONFIG_IDENT_STRING, "\0"
	95
	96	. = EXC_OFF_SYS_RESET
	97	.globl _start
	98	_start:
	99	lis r3, CFG_IMMR@h /* position IMMR */
	100	mtspr 638, r3
	101	li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
	102	b boot_cold
	103
	104	. = EXC_OFF_SYS_RESET + 0x10
	105
	106	.globl _start_warm
	107	_start_warm:
	108	li r21, BOOTFLAG_WARM /* Software reboot */
	109	b boot_warm
	110
	111	boot_cold:
	112	boot_warm:
	113
	114	/* Initialize machine status; enable machine check interrupt */
	115	/----------------------------------------------------------------------/
	116	li r3, MSR_KERNEL /* Set ME, RI flags */
	117	mtmsr r3
	118	mtspr SRR1, r3 /* Make SRR1 match MSR */
	119
	120	mfspr r3, ICR /* clear Interrupt Cause Register */
	121
	122	/* Initialize debug port registers */
	123	/----------------------------------------------------------------------/
	124	xor r0, r0, r0 /* Clear R0 */
	125	mtspr LCTRL1, r0 /* Initialize debug port regs */
	126	mtspr LCTRL2, r0
	127	mtspr COUNTA, r0
	128	mtspr COUNTB, r0
	129
	130	/* Reset the caches */
	131	/----------------------------------------------------------------------/
	132
	133	mfspr r3, IC_CST /* Clear error bits */
	134	mfspr r3, DC_CST
	135
	136	lis r3, IDC_UNALL@h /* Unlock all */
	137	mtspr IC_CST, r3
	138	mtspr DC_CST, r3
	139
	140	lis r3, IDC_INVALL@h /* Invalidate all */
	141	mtspr IC_CST, r3
	142	mtspr DC_CST, r3
	143
144	lis r3, IDC_DISABLE@h /* Disable data cache */
145	mtspr DC_CST, r3
146
147	#if !(defined(CONFIG_IP860) \|\| defined(CONFIG_PCU_E) \|\| defined (CONFIG_FLAGADM))
148	/* On IP860 and PCU E,
149	* we cannot enable IC yet
150	*/
151	lis r3, IDC_ENABLE@h /* Enable instruction cache */
152	#endif
153	mtspr IC_CST, r3
154
155	/* invalidate all tlb's */
156	/----------------------------------------------------------------------/
157
158	tlbia
159	isync
160
161	/*
162	* Calculate absolute address in FLASH and jump there
163	----------------------------------------------------------------------/
164
165	lis r3, CFG_MONITOR_BASE@h
166	ori r3, r3, CFG_MONITOR_BASE@l
167	addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
168	mtlr r3
169	blr
170
171	in_flash:
172
173	/* initialize some SPRs that are hard to access from C */
174	/----------------------------------------------------------------------/
175
176	lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */
177	ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
178	/* Note: R0 is still 0 here */
179	stwu r0, -4(r1) /* clear final stack frame so that */
180	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
181
182	/*
183	* Disable serialized ifetch and show cycles
184	* (i.e. set processor to normal mode).
185	* This is also a silicon bug workaround, see errata
186	*/
187
188	li r2, 0x0007
189	mtspr ICTRL, r2
190
191	/* Set up debug mode entry */
192
193	lis r2, CFG_DER@h
194	ori r2, r2, CFG_DER@l
195	mtspr DER, r2
196
197	/* let the C-code set up the rest */
198	/* */
199	/* Be careful to keep code relocatable ! */
200	/----------------------------------------------------------------------/
201
202	GET_GOT /* initialize GOT access */
203
204	/* r3: IMMR */
205	bl cpu_init_f /* run low-level CPU init code (from Flash) */
206
207	mr r3, r21
208	/* r3: BOOTFLAG */
209	bl board_init_f /* run 1st part of board init code (from Flash) */
210
211
5b1d7137 WD	212	.globl _start_of_vectors
	213	_start_of_vectors:
	214
	215	/* Machine check */
	216	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	217
	218	/* Data Storage exception. "Never" generated on the 860. */
	219	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	220
	221	/* Instruction Storage exception. "Never" generated on the 860. */
	222	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	223
	224	/* External Interrupt exception. */
	225	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
	226
	227	/* Alignment exception. */
	228	. = 0x600
	229	Alignment:
	230	EXCEPTION_PROLOG
	231	mfspr r4,DAR
	232	stw r4,_DAR(r21)
	233	mfspr r5,DSISR
	234	stw r5,_DSISR(r21)
	235	addi r3,r1,STACK_FRAME_OVERHEAD
	236	li r20,MSR_KERNEL
	237	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
	238	lwz r6,GOT(transfer_to_handler)
	239	mtlr r6
	240	blrl
	241	.L_Alignment:
	242	.long AlignmentException - _start + EXC_OFF_SYS_RESET
	243	.long int_return - _start + EXC_OFF_SYS_RESET
	244
	245	/* Program check exception */
	246	. = 0x700
	247	ProgramCheck:
	248	EXCEPTION_PROLOG
	249	addi r3,r1,STACK_FRAME_OVERHEAD
	250	li r20,MSR_KERNEL
	251	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
	252	lwz r6,GOT(transfer_to_handler)
	253	mtlr r6
	254	blrl
	255	.L_ProgramCheck:
	256	.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
	257	.long int_return - _start + EXC_OFF_SYS_RESET
	258
	259	/* No FPU on MPC8xx. This exception is not supposed to happen.
	260	*/
	261	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	262
	263	/* I guess we could implement decrementer, and may have
	264	* to someday for timekeeping.
	265	*/
	266	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	267	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	268	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
27b207fd	269	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
5b1d7137 WD	270	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
	271
	272	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	273	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
	274
	275	/* On the MPC8xx, this is a software emulation interrupt. It occurs
	276	* for all unimplemented and illegal instructions.
	277	*/
	278	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
	279
	280	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	281	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	282	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	283	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
	284
	285	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	286	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	287	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	288	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	289	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	290	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	291	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
	292
	293	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	294	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	295	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	296	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
	297
	298
	299	.globl _end_of_vectors
	300	_end_of_vectors:
	301
	302
	303	. = 0x2000
	304
	305	/*
	306	* This code finishes saving the registers to the exception frame
	307	* and jumps to the appropriate handler for the exception.
	308	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	309	*/
	310	.globl transfer_to_handler
	311	transfer_to_handler:
	312	stw r22,_NIP(r21)
	313	lis r22,MSR_POW@h
	314	andc r23,r23,r22
	315	stw r23,_MSR(r21)
	316	SAVE_GPR(7, r21)
	317	SAVE_4GPRS(8, r21)
	318	SAVE_8GPRS(12, r21)
	319	SAVE_8GPRS(24, r21)
	320	mflr r23
	321	andi. r24,r23,0x3f00 /* get vector offset */
	322	stw r24,TRAP(r21)
	323	li r22,0
	324	stw r22,RESULT(r21)
	325	mtspr SPRG2,r22 /* r1 is now kernel sp */
	326	lwz r24,0(r23) /* virtual address of handler */
	327	lwz r23,4(r23) /* where to go when done */
	328	mtspr SRR0,r24
	329	mtspr SRR1,r20
	330	mtlr r23
	331	SYNC
	332	rfi /* jump to handler, enable MMU */
	333
334	int_return:
335	mfmsr r28 /* Disable interrupts */
336	li r4,0
337	ori r4,r4,MSR_EE
338	andc r28,r28,r4
339	SYNC /* Some chip revs need this... */
340	mtmsr r28
341	SYNC
342	lwz r2,_CTR(r1)
343	lwz r0,_LINK(r1)
344	mtctr r2
345	mtlr r0
346	lwz r2,_XER(r1)
347	lwz r0,_CCR(r1)
348	mtspr XER,r2
349	mtcrf 0xFF,r0
350	REST_10GPRS(3, r1)
351	REST_10GPRS(13, r1)
352	REST_8GPRS(23, r1)
353	REST_GPR(31, r1)
354	lwz r2,_NIP(r1) /* Restore environment */
355	lwz r0,_MSR(r1)
356	mtspr SRR0,r2
357	mtspr SRR1,r0
358	lwz r0,GPR0(r1)
359	lwz r2,GPR2(r1)
360	lwz r1,GPR1(r1)
361	SYNC
362	rfi
363
364	/* Cache functions.
365	*/
366	.globl icache_enable
367	icache_enable:
368	SYNC
369	lis r3, IDC_INVALL@h
370	mtspr IC_CST, r3
371	lis r3, IDC_ENABLE@h
372	mtspr IC_CST, r3
373	blr
374
375	.globl icache_disable
376	icache_disable:
377	SYNC
378	lis r3, IDC_DISABLE@h
379	mtspr IC_CST, r3
380	blr
381
382	.globl icache_status
383	icache_status:
384	mfspr r3, IC_CST
385	srwi r3, r3, 31 /* >>31 => select bit 0 */
386	blr
387
388	.globl dcache_enable
389	dcache_enable:
390	#if 0
391	SYNC
392	#endif
393	#if 1
394	lis r3, 0x0400 /* Set cache mode with MMU off */
395	mtspr MD_CTR, r3
396	#endif
397
398	lis r3, IDC_INVALL@h
399	mtspr DC_CST, r3
400	#if 0
401	lis r3, DC_SFWT@h
402	mtspr DC_CST, r3
403	#endif
404	lis r3, IDC_ENABLE@h
405	mtspr DC_CST, r3
406	blr
407
408	.globl dcache_disable
409	dcache_disable:
410	SYNC
411	lis r3, IDC_DISABLE@h
412	mtspr DC_CST, r3
413	lis r3, IDC_INVALL@h
414	mtspr DC_CST, r3
415	blr
416
417	.globl dcache_status
418	dcache_status:
419	mfspr r3, DC_CST
420	srwi r3, r3, 31 /* >>31 => select bit 0 */
421	blr
422
423	.globl dc_read
424	dc_read:
425	mtspr DC_ADR, r3
426	mfspr r3, DC_DAT
427	blr
428
429	/*
430	* unsigned int get_immr (unsigned int mask)
431	*
432	* return (mask ? (IMMR & mask) : IMMR);
433	*/
434	.globl get_immr
435	get_immr:
436	mr r4,r3 /* save mask */
437	mfspr r3, IMMR /* IMMR */
438	cmpwi 0,r4,0 /* mask != 0 ? */
439	beq 4f
440	and r3,r3,r4 /* IMMR & mask */
441	4:
442	blr
443
444	.globl get_pvr
445	get_pvr:
446	mfspr r3, PVR
447	blr
448
449
450	.globl wr_ic_cst
451	wr_ic_cst:
452	mtspr IC_CST, r3
453	blr
454
455	.globl rd_ic_cst
456	rd_ic_cst:
457	mfspr r3, IC_CST
458	blr
459
460	.globl wr_ic_adr
461	wr_ic_adr:
462	mtspr IC_ADR, r3
463	blr
464
465
466	.globl wr_dc_cst
467	wr_dc_cst:
468	mtspr DC_CST, r3
469	blr
470
471	.globl rd_dc_cst
472	rd_dc_cst:
473	mfspr r3, DC_CST
474	blr
475
476	.globl wr_dc_adr
477	wr_dc_adr:
478	mtspr DC_ADR, r3
479	blr
480
481	/------------------------------------------------------------------------------/
482
483	/*
484	* void relocate_code (addr_sp, gd, addr_moni)
485	*
486	* This "function" does not return, instead it continues in RAM
487	* after relocating the monitor code.
488	*
489	* r3 = dest
490	* r4 = src
491	* r5 = length in bytes
492	* r6 = cachelinesize
493	*/
494	.globl relocate_code
495	relocate_code:
496	mr r1, r3 /* Set new stack pointer */
497	mr r9, r4 /* Save copy of Global Data pointer */
498	mr r10, r5 /* Save copy of Destination Address */
499
500	mr r3, r5 /* Destination Address */
501	lis r4, CFG_MONITOR_BASE@h /* Source Address */
502	ori r4, r4, CFG_MONITOR_BASE@l
3b57fe0a WD	503	lwz r5, GOT(__init_end)
3b57fe0a WD	504	sub r5, r5, r4
5b1d7137 WD	505	li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
	506
	507	/*
	508	* Fix GOT pointer:
	509	*
	510	* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
	511	*
	512	* Offset:
	513	*/
	514	sub r15, r10, r4
	515
	516	/* First our own GOT */
	517	add r14, r14, r15
d0fb80c3	518	/* then the one used by the C code */
5b1d7137 WD	519	add r30, r30, r15
	520
	521	/*
	522	* Now relocate code
	523	*/
	524
	525	cmplw cr1,r3,r4
	526	addi r0,r5,3
	527	srwi. r0,r0,2
	528	beq cr1,4f /* In place copy is not necessary */
	529	beq 7f /* Protect against 0 count */
	530	mtctr r0
	531	bge cr1,2f
	532
	533	la r8,-4(r4)
	534	la r7,-4(r3)
	535	1: lwzu r0,4(r8)
	536	stwu r0,4(r7)
	537	bdnz 1b
	538	b 4f
	539
	540	2: slwi r0,r0,2
	541	add r8,r4,r0
	542	add r7,r3,r0
	543	3: lwzu r0,-4(r8)
	544	stwu r0,-4(r7)
	545	bdnz 3b
	546
	547	/*
	548	* Now flush the cache: note that we must start from a cache aligned
	549	* address. Otherwise we might miss one cache line.
	550	*/
	551	4: cmpwi r6,0
	552	add r5,r3,r5
	553	beq 7f /* Always flush prefetch queue in any case */
	554	subi r0,r6,1
	555	andc r3,r3,r0
	556	mr r4,r3
	557	5: dcbst 0,r4
	558	add r4,r4,r6
	559	cmplw r4,r5
	560	blt 5b
	561	sync /* Wait for all dcbst to complete on bus */
	562	mr r4,r3
	563	6: icbi 0,r4
	564	add r4,r4,r6
	565	cmplw r4,r5
	566	blt 6b
	567	7: sync /* Wait for all icbi to complete on bus */
	568	isync
	569
	570	/*
	571	* We are done. Do not return, instead branch to second part of board
	572	* initialization, now running from RAM.
	573	*/
	574
	575	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	576	mtlr r0
	577	blr
	578
	579	in_ram:
	580
	581	/*
	582	* Relocation Function, r14 point to got2+0x8000
583	*
8bde7f77 WD	584	* Adjust got2 pointers, no need to check for 0, this code
8bde7f77 WD	585	* already puts a few entries in the table.
5b1d7137 WD	586	*/
	587	li r0,__got2_entries@sectoff@l
	588	la r3,GOT(_GOT2_TABLE_)
	589	lwz r11,GOT(_GOT2_TABLE_)
	590	mtctr r0
	591	sub r11,r3,r11
	592	addi r3,r3,-4
	593	1: lwzu r0,4(r3)
	594	add r0,r0,r11
	595	stw r0,0(r3)
	596	bdnz 1b
	597
	598	/*
8bde7f77	599	* Now adjust the fixups and the pointers to the fixups
5b1d7137 WD	600	* in case we need to move ourselves again.
	601	*/
	602	2: li r0,__fixup_entries@sectoff@l
	603	lwz r3,GOT(_FIXUP_TABLE_)
	604	cmpwi r0,0
	605	mtctr r0
	606	addi r3,r3,-4
	607	beq 4f
	608	3: lwzu r4,4(r3)
	609	lwzux r0,r4,r11
	610	add r0,r0,r11
	611	stw r10,0(r3)
	612	stw r0,0(r4)
	613	bdnz 3b
	614	4:
	615	clear_bss:
	616	/*
	617	* Now clear BSS segment
	618	*/
5d232d0e	619	lwz r3,GOT(__bss_start)
1f4bb37d	620	#if defined(CONFIG_ICU862)
5b1d7137 WD	621	/*
	622	* For the FADS - the environment is the very last item in flash.
	623	* The real .bss stops just before environment starts, so only
	624	* clear up to that point.
	625	*/
	626	lwz r4,GOT(environment)
	627	#else
	628	lwz r4,GOT(_end)
	629	#endif
	630
	631	cmplw 0, r3, r4
	632	beq 6f
	633
	634	li r0, 0
	635	5:
	636	stw r0, 0(r3)
	637	addi r3, r3, 4
	638	cmplw 0, r3, r4
	639	bne 5b
	640	6:
	641
	642	mr r3, r9 /* Global Data pointer */
	643	mr r4, r10 /* Destination Address */
	644	bl board_init_r
	645
5b1d7137 WD	646	/*
	647	* Copy exception vector code to low memory
	648	*
	649	* r3: dest_addr
	650	* r7: source address, r8: end address, r9: target address
	651	*/
	652	.globl trap_init
	653	trap_init:
	654	lwz r7, GOT(_start)
	655	lwz r8, GOT(_end_of_vectors)
	656
682011ff	657	li r9, 0x100 /* reset vector always at 0x100 */
5b1d7137 WD	658
	659	cmplw 0, r7, r8
	660	bgelr /* return if r7>=r8 - just in case */
	661
	662	mflr r4 /* save link register */
	663	1:
	664	lwz r0, 0(r7)
	665	stw r0, 0(r9)
	666	addi r7, r7, 4
	667	addi r9, r9, 4
	668	cmplw 0, r7, r8
	669	bne 1b
	670
	671	/*
	672	* relocate `hdlr' and `int_return' entries
	673	*/
	674	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	675	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	676	2:
	677	bl trap_reloc
	678	addi r7, r7, 0x100 /* next exception vector */
	679	cmplw 0, r7, r8
	680	blt 2b
	681
	682	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	683	bl trap_reloc
	684
	685	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	686	bl trap_reloc
	687
	688	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	689	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	690	3:
	691	bl trap_reloc
	692	addi r7, r7, 0x100 /* next exception vector */
	693	cmplw 0, r7, r8
	694	blt 3b
	695
	696	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	697	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	698	4:
	699	bl trap_reloc
	700	addi r7, r7, 0x100 /* next exception vector */
	701	cmplw 0, r7, r8
	702	blt 4b
	703
	704	mtlr r4 /* restore link register */
	705	blr
	706
	707	/*
	708	* Function: relocate entries for one exception vector
	709	*/
	710	trap_reloc:
	711	lwz r0, 0(r7) /* hdlr ... */
	712	add r0, r0, r3 /* ... += dest_addr */
	713	stw r0, 0(r7)
	714
	715	lwz r0, 4(r7) /* int_return ... */
	716	add r0, r0, r3 /* ... += dest_addr */
	717	stw r0, 4(r7)
	718
	719	sync
	720	isync
	721
722	blr