]> git.ipfire.org Git - people/ms/u-boot.git/blame - cpu/ppc4xx/405gp_enet.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Patch by Travis Sawyer, 30 Dec 2003:
[people/ms/u-boot.git] / cpu / ppc4xx / 405gp_enet.c
CommitLineData
c609719b
WD		 1/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
b4676a25
WD		 70 * 21-Nov-03 pavel.bartusek@sysgo.com
71 * - set ZMII bridge speed on 440
72 *
c609719b
WD		 73 *-----------------------------------------------------------------------------*/
74
75#include <common.h>
76#include <asm/processor.h>
77#include <ppc4xx.h>
78#include <commproc.h>
79#include <405gp_enet.h>
80#include <405_mal.h>
81#include <miiphy.h>
82#include <net.h>
83#include <malloc.h>
84#include "vecnum.h"
85
ba56f625
WD		 86#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
87 ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
c609719b
WD		 88
89#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
149dded2 90#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
c609719b
WD		 91
92#define NUM_TX_BUFF 1
93/* AS.HARNOIS
94 * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
95 * These both variables are used to define the same thing!
96 * #define NUM_RX_BUFF 4
97 */
98#define NUM_RX_BUFF PKTBUFSRX
99
100/* Ethernet Transmit and Receive Buffers */
101/* AS.HARNOIS
102 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
103 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
104 */
105#define ENET_MAX_MTU PKTSIZE
106#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
107
108static char *txbuf_ptr;
109
110/* define the number of channels implemented */
111#define EMAC_RXCHL 1
112#define EMAC_TXCHL 1
113
114/*-----------------------------------------------------------------------------+
115 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
116 * Interrupt Controller).
117 *-----------------------------------------------------------------------------*/
118#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
119#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
120#define EMAC_UIC_DEF UIC_ENET
121
122/*-----------------------------------------------------------------------------+
123 * Global variables. TX and RX descriptors and buffers.
124 *-----------------------------------------------------------------------------*/
125static volatile mal_desc_t *tx;
126static volatile mal_desc_t *rx;
127static mal_desc_t *alloc_tx_buf = NULL;
128static mal_desc_t *alloc_rx_buf = NULL;
129
130/* IER globals */
131static unsigned long emac_ier;
132static unsigned long mal_ier;
133
134
135/* Statistic Areas */
136#define MAX_ERR_LOG 10
137struct emac_stats {
138 int data_len_err;
139 int rx_frames;
140 int rx;
141 int rx_prot_err;
142};
143
144static struct stats { /* Statistic Block */
145 struct emac_stats emac;
146 int int_err;
147 short tx_err_log[MAX_ERR_LOG];
148 short rx_err_log[MAX_ERR_LOG];
149} stats;
150
151static int first_init = 0;
152
153static int tx_err_index = 0; /* Transmit Error Index for tx_err_log */
154static int rx_err_index = 0; /* Receive Error Index for rx_err_log */
155
156static int rx_slot = 0; /* MAL Receive Slot */
157static int rx_i_index = 0; /* Receive Interrupt Queue Index */
158static int rx_u_index = 0; /* Receive User Queue Index */
159static int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
160
161static int tx_slot = 0; /* MAL Transmit Slot */
162static int tx_i_index = 0; /* Transmit Interrupt Queue Index */
163static int tx_u_index = 0; /* Transmit User Queue Index */
164static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
165
a8c7c708 166#undef INFO_405_ENET
c609719b
WD		 167#ifdef INFO_405_ENET
168static int packetSent = 0;
169static int packetReceived = 0;
170static int packetHandled = 0;
171#endif
172
173static char emac_hwd_addr[ENET_ADDR_LENGTH];
174
175static bd_t *bis_save = NULL; /* for eth_init upon mal error */
176
177static int is_receiving = 0; /* sync with eth interrupt */
178static int print_speed = 1; /* print speed message upon start */
179
c609719b
WD		 180/*-----------------------------------------------------------------------------+
181 * Prototypes and externals.
182 *-----------------------------------------------------------------------------*/
a3ed3996
WD		 183static void enet_rcv (unsigned long malisr);
184static int enetInt(void);
185static void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
c609719b 186 unsigned long mal_errr);
a3ed3996 187static void emac_err (unsigned long isr);
c609719b 188
a3ed3996 189static void ppc_4xx_eth_halt (struct eth_device *dev)
c609719b
WD		 190{
191 mtdcr (malier, 0x00000000); /* disable mal interrupts */
192 out32 (EMAC_IER, 0x00000000); /* disable emac interrupts */
193
194 /* 1st reset MAL */
195 mtdcr (malmcr, MAL_CR_MMSR);
196
197 /* wait for reset */
198 while (mfdcr (malmcr) & MAL_CR_MMSR) {
199 };
200
201 /* EMAC RESET */
202 out32 (EMAC_M0, EMAC_M0_SRST);
203
204 print_speed = 1; /* print speed message again next time */
205}
206
207
a3ed3996 208static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
c609719b
WD		 209{
210 int i;
211 unsigned long reg;
212 unsigned long msr;
213 unsigned long speed;
214 unsigned long duplex;
215 unsigned mode_reg;
216 unsigned short reg_short;
217
218 msr = mfmsr ();
219 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
220
221#ifdef INFO_405_ENET
222 /* AS.HARNOIS
223 * We should have :
224 * packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
8bde7f77
WD		 225 * In the most cases packetHandled = packetReceived, but it
226 * is possible that new packets (without relationship with
227 * current transfer) have got the time to arrived before
228 * netloop calls eth_halt
c609719b
WD		 229 */
230 printf ("About preceeding transfer:\n"
231 "- Sent packet number %d\n"
232 "- Received packet number %d\n"
233 "- Handled packet number %d\n",
234 packetSent, packetReceived, packetHandled);
235 packetSent = 0;
236 packetReceived = 0;
237 packetHandled = 0;
238#endif
239
240 /* MAL RESET */
241 mtdcr (malmcr, MAL_CR_MMSR);
242 /* wait for reset */
243 while (mfdcr (malmcr) & MAL_CR_MMSR) {
244 };
245
246 tx_err_index = 0; /* Transmit Error Index for tx_err_log */
247 rx_err_index = 0; /* Receive Error Index for rx_err_log */
248
249 rx_slot = 0; /* MAL Receive Slot */
250 rx_i_index = 0; /* Receive Interrupt Queue Index */
251 rx_u_index = 0; /* Receive User Queue Index */
252
253 tx_slot = 0; /* MAL Transmit Slot */
254 tx_i_index = 0; /* Transmit Interrupt Queue Index */
255 tx_u_index = 0; /* Transmit User Queue Index */
256
257#if defined(CONFIG_440)
8bde7f77
WD		 258 /* set RMII mode */
259 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
c609719b
WD		 260#endif /* CONFIG_440 */
261
262 /* EMAC RESET */
263 out32 (EMAC_M0, EMAC_M0_SRST);
264
265 /* wait for PHY to complete auto negotiation */
266 reg_short = 0;
267#ifndef CONFIG_CS8952_PHY
268 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
269
270 /*
271 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
272 */
273 if ((reg_short & PHY_BMSR_AUTN_ABLE)
274 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
275 puts ("Waiting for PHY auto negotiation to complete");
276 i = 0;
277 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
c609719b
WD		 278 /*
279 * Timeout reached ?
280 */
149dded2 281 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
c609719b
WD		 282 puts (" TIMEOUT !\n");
283 break;
284 }
149dded2
WD		 285
286 if ((i++ % 1000) == 0)
287 putc ('.');
288 udelay (1000); /* 1 ms */
289 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
c609719b
WD		 290 }
291 puts (" done\n");
292 udelay (500000); /* another 500 ms (results in faster booting) */
293 }
294#endif
295 speed = miiphy_speed (CONFIG_PHY_ADDR);
296 duplex = miiphy_duplex (CONFIG_PHY_ADDR);
297 if (print_speed) {
298 print_speed = 0;
299 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
300 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
301 }
302
303 /* set the Mal configuration reg */
304#if defined(CONFIG_440)
305 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
306 if( get_pvr() == PVR_440GP_RB )
307 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
308 else
309#else
310 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
311#endif
312
313 /* Free "old" buffers */
314 if (alloc_tx_buf) free(alloc_tx_buf);
315 if (alloc_rx_buf) free(alloc_rx_buf);
316
317 /*
318 * Malloc MAL buffer desciptors, make sure they are
319 * aligned on cache line boundary size
320 * (401/403/IOP480 = 16, 405 = 32)
321 * and doesn't cross cache block boundaries.
322 */
323 alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
324 ((2 * CFG_CACHELINE_SIZE) - 2));
325 if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
326 tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
327 ((int)alloc_tx_buf & CACHELINE_MASK));
328 } else {
329 tx = alloc_tx_buf;
330 }
331
332 alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
333 ((2 * CFG_CACHELINE_SIZE) - 2));
334 if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
335 rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
336 ((int)alloc_rx_buf & CACHELINE_MASK));
337 } else {
338 rx = alloc_rx_buf;
339 }
340
341 for (i = 0; i < NUM_TX_BUFF; i++) {
342 tx[i].ctrl = 0;
343 tx[i].data_len = 0;
344 if (first_init == 0)
345 txbuf_ptr = (char *) malloc (ENET_MAX_MTU_ALIGNED);
346 tx[i].data_ptr = txbuf_ptr;
347 if ((NUM_TX_BUFF - 1) == i)
348 tx[i].ctrl |= MAL_TX_CTRL_WRAP;
349 tx_run[i] = -1;
350#if 0
351 printf ("TX_BUFF %d @ 0x%08lx\n", i, (ulong) tx[i].data_ptr);
352#endif
353 }
354
355 for (i = 0; i < NUM_RX_BUFF; i++) {
356 rx[i].ctrl = 0;
357 rx[i].data_len = 0;
358 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
359 rx[i].data_ptr = (char *) NetRxPackets[i];
360 if ((NUM_RX_BUFF - 1) == i)
361 rx[i].ctrl |= MAL_RX_CTRL_WRAP;
362 rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
363 rx_ready[i] = -1;
364#if 0
365 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
366#endif
367 }
368
369 memcpy (emac_hwd_addr, bis->bi_enetaddr, ENET_ADDR_LENGTH);
370
371 reg = 0x00000000;
372
373 reg |= emac_hwd_addr[0]; /* set high address */
374 reg = reg << 8;
375 reg |= emac_hwd_addr[1];
376
377 out32 (EMAC_IAH, reg);
378
379 reg = 0x00000000;
380 reg |= emac_hwd_addr[2]; /* set low address */
381 reg = reg << 8;
382 reg |= emac_hwd_addr[3];
383 reg = reg << 8;
384 reg |= emac_hwd_addr[4];
385 reg = reg << 8;
386 reg |= emac_hwd_addr[5];
387
388 out32 (EMAC_IAL, reg);
389
390 /* setup MAL tx & rx channel pointers */
391 mtdcr (maltxctp0r, tx);
392 mtdcr (malrxctp0r, rx);
393
394 /* Reset transmit and receive channels */
395 mtdcr (malrxcarr, 0x80000000); /* 2 channels */
396 mtdcr (maltxcarr, 0x80000000); /* 2 channels */
397
398 /* Enable MAL transmit and receive channels */
399 mtdcr (maltxcasr, 0x80000000); /* 1 channel */
400 mtdcr (malrxcasr, 0x80000000); /* 1 channel */
401
402 /* set RX buffer size */
403 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
404
405 /* set transmit enable & receive enable */
406 out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
407
408 /* set receive fifo to 4k and tx fifo to 2k */
409 mode_reg = EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
410
411 /* set speed */
412 if (speed == _100BASET)
413 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
414 else
415 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
416 if (duplex == FULL)
417 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
418
419 out32 (EMAC_M1, mode_reg);
420
b4676a25
WD		 421#if defined(CONFIG_440)
422 /* set speed in the ZMII bridge */
423 if (speed == _100BASET)
424 out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
425 else
426 out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
427#endif
428
c609719b
WD		 429 /* Enable broadcast and indvidual address */
430 out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
431 /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
432
433 /* we probably need to set the tx mode1 reg? maybe at tx time */
434
435 /* set transmit request threshold register */
436 out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
437
438 /* set receive low/high water mark register */
439#if defined(CONFIG_440)
440 /* 440GP has a 64 byte burst length */
8bde7f77
WD		 441 out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
442 out32 (EMAC_TXM1, 0xf8640000);
c609719b
WD		 443#else /* CONFIG_440 */
444 /* 405s have a 16 byte burst length */
445 out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
446#endif /* CONFIG_440 */
447
448 /* Frame gap set */
449 out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
450
451 if (first_init == 0) {
452 /*
453 * Connect interrupt service routines
454 */
455 irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
456 irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
457 irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
458 irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
459 irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
460 irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
461 irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
462 }
463
464 /* set up interrupt handler */
465 /* setup interrupt controler to take interrupts from the MAL &
466 EMAC */
467 mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
468 mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
469
470 /* set the MAL IER ??? names may change with new spec ??? */
471 mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
472 MAL_IER_PLBE;
473 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
474 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
475 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
476 mtdcr (malier, mal_ier);
477
478 /* Set EMAC IER */
479 emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
480 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
481 if (speed == _100BASET)
482 emac_ier = emac_ier | EMAC_ISR_SYE;
483
484 out32 (EMAC_ISR, 0xffffffff); /* clear pending interrupts */
485 out32 (EMAC_IER, emac_ier);
486
487 mtmsr (msr); /* enable interrupts again */
488
489 bis_save = bis;
490 first_init = 1;
491
a3ed3996 492 return (1);
c609719b
WD		 493}
494
495
a3ed3996 496static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
c609719b
WD		 497{
498 struct enet_frame *ef_ptr;
499 ulong time_start, time_now;
500 unsigned long temp_txm0;
501
502 ef_ptr = (struct enet_frame *) ptr;
503
504 /*-----------------------------------------------------------------------+
505 * Copy in our address into the frame.
506 *-----------------------------------------------------------------------*/
507 (void) memcpy (ef_ptr->source_addr, emac_hwd_addr, ENET_ADDR_LENGTH);
508
509 /*-----------------------------------------------------------------------+
510 * If frame is too long or too short, modify length.
511 *-----------------------------------------------------------------------*/
512 if (len > ENET_MAX_MTU)
513 len = ENET_MAX_MTU;
514
515 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
516 memcpy ((void *) txbuf_ptr, (const void *) ptr, len);
517
518 /*-----------------------------------------------------------------------+
519 * set TX Buffer busy, and send it
520 *-----------------------------------------------------------------------*/
521 tx[tx_slot].ctrl = (MAL_TX_CTRL_LAST |
522 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
523 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
524 if ((NUM_TX_BUFF - 1) == tx_slot)
525 tx[tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
526
527 tx[tx_slot].data_len = (short) len;
528 tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
529
530 __asm__ volatile ("eieio");
531 out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
532#ifdef INFO_405_ENET
533 packetSent++;
534#endif
535
536 /*-----------------------------------------------------------------------+
537 * poll unitl the packet is sent and then make sure it is OK
538 *-----------------------------------------------------------------------*/
539 time_start = get_timer (0);
540 while (1) {
541 temp_txm0 = in32 (EMAC_TXM0);
542 /* loop until either TINT turns on or 3 seconds elapse */
543 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
544 /* transmit is done, so now check for errors
8bde7f77
WD		 545 * If there is an error, an interrupt should
546 * happen when we return
c609719b
WD		 547 */
548 time_now = get_timer (0);
549 if ((time_now - time_start) > 3000) {
550 return (-1);
551 }
552 } else {
a3ed3996 553 return (len);
c609719b
WD		 554 }
555 }
556}
557
558
559#if defined(CONFIG_440)
560/*-----------------------------------------------------------------------------+
561| EnetInt.
562| EnetInt is the interrupt handler. It will determine the
563| cause of the interrupt and call the apporpriate servive
564| routine.
565+-----------------------------------------------------------------------------*/
566int enetInt ()
567{
568 int serviced;
569 int rc = -1; /* default to not us */
570 unsigned long mal_isr;
571 unsigned long emac_isr = 0;
572 unsigned long mal_rx_eob;
573 unsigned long my_uic0msr, my_uic1msr;
574
575 /* enter loop that stays in interrupt code until nothing to service */
576 do {
577 serviced = 0;
578
579 my_uic0msr = mfdcr (uic0msr);
580 my_uic1msr = mfdcr (uic1msr);
581
582 if (!(my_uic0msr & UIC_MRE)
8bde7f77
WD		 583 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
584 /* not for us */
c609719b
WD		 585 return (rc);
586 }
587
588 /* get and clear controller status interrupts */
589 /* look at Mal and EMAC interrupts */
590 if ((my_uic0msr & UIC_MRE)
8bde7f77
WD		 591 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
592 /* we have a MAL interrupt */
c609719b
WD		 593 mal_isr = mfdcr (malesr);
594 /* look for mal error */
595 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
596 mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
597 serviced = 1;
598 rc = 0;
599 }
600 }
601 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
602 emac_isr = in32 (EMAC_ISR);
603 if ((emac_ier & emac_isr) != 0) {
604 emac_err (emac_isr);
605 serviced = 1;
606 rc = 0;
607 }
608 }
609 if ((emac_ier & emac_isr)
8bde7f77 610 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
c609719b
WD		 611 mtdcr (uic0sr, UIC_MRE); /* Clear */
612 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
613 return (rc); /* we had errors so get out */
614 }
615
616 /* handle MAL RX EOB interupt from a receive */
617 /* check for EOB on valid channels */
618 if (my_uic0msr & UIC_MRE) {
619 mal_rx_eob = mfdcr (malrxeobisr);
620 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
621 /* clear EOB
622 mtdcr(malrxeobisr, mal_rx_eob); */
623 enet_rcv (emac_isr);
624 /* indicate that we serviced an interrupt */
625 serviced = 1;
626 rc = 0;
627 }
628 }
8bde7f77
WD		 629 mtdcr (uic0sr, UIC_MRE); /* Clear */
630 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
c609719b
WD		 631 } while (serviced);
632
633 return (rc);
634}
635#else /* CONFIG_440 */
636/*-----------------------------------------------------------------------------+
637 * EnetInt.
638 * EnetInt is the interrupt handler. It will determine the
639 * cause of the interrupt and call the apporpriate servive
640 * routine.
641 *-----------------------------------------------------------------------------*/
642int enetInt ()
643{
644 int serviced;
645 int rc = -1; /* default to not us */
646 unsigned long mal_isr;
647 unsigned long emac_isr = 0;
648 unsigned long mal_rx_eob;
649 unsigned long my_uicmsr;
650
651 /* enter loop that stays in interrupt code until nothing to service */
652 do {
653 serviced = 0;
654
655 my_uicmsr = mfdcr (uicmsr);
656 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
657 return (rc);
658 }
659
660
661 /* get and clear controller status interrupts */
662 /* look at Mal and EMAC interrupts */
663 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
664 mal_isr = mfdcr (malesr);
665 /* look for mal error */
666 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
667 mal_err (mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
668 serviced = 1;
669 rc = 0;
670 }
671 }
672 if ((EMAC_UIC_DEF & my_uicmsr) != 0) { /* look for EMAC errors */
673 emac_isr = in32 (EMAC_ISR);
674 if ((emac_ier & emac_isr) != 0) {
675 emac_err (emac_isr);
676 serviced = 1;
677 rc = 0;
678 }
679 }
680 if (((emac_ier & emac_isr) != 0) | ((MAL_UIC_ERR & my_uicmsr) != 0)) {
681 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
682 return (rc); /* we had errors so get out */
683 }
684
685
686 /* handle MAL RX EOB interupt from a receive */
687 /* check for EOB on valid channels */
688 if ((my_uicmsr & UIC_MAL_RXEOB) != 0) {
689 mal_rx_eob = mfdcr (malrxeobisr);
690 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
691 /* clear EOB
692 mtdcr(malrxeobisr, mal_rx_eob); */
693 enet_rcv (emac_isr);
694 /* indicate that we serviced an interrupt */
695 serviced = 1;
696 rc = 0;
697 }
698 }
699 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
700 }
701 while (serviced);
702
703 return (rc);
704}
705#endif /* CONFIG_440 */
706
707/*-----------------------------------------------------------------------------+
708 * MAL Error Routine
709 *-----------------------------------------------------------------------------*/
a3ed3996 710static void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
c609719b
WD		 711 unsigned long mal_errr)
712{
713 mtdcr (malesr, isr); /* clear interrupt */
714
715 /* clear DE interrupt */
716 mtdcr (maltxdeir, 0xC0000000);
717 mtdcr (malrxdeir, 0x80000000);
718
b867d705 719#ifdef INFO_405_ENET
c609719b
WD		 720 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
721 isr, uic, maldef, mal_errr);
722#else
723#if 0
724 /*
725 * MAL error is RX DE error (out of rx buffers)! This is OK here, upon
726 * many incoming packets with only 4 rx buffers.
727 */
728 printf ("M"); /* just to see something upon mal error */
729#endif
b867d705 730#endif
c609719b
WD		 731
732 eth_init (bis_save); /* start again... */
733}
734
735/*-----------------------------------------------------------------------------+
736 * EMAC Error Routine
737 *-----------------------------------------------------------------------------*/
a3ed3996 738static void emac_err (unsigned long isr)
c609719b
WD		 739{
740 printf ("EMAC error occured.... ISR = %lx\n", isr);
741 out32 (EMAC_ISR, isr);
742}
743
744/*-----------------------------------------------------------------------------+
745 * enet_rcv() handles the ethernet receive data
746 *-----------------------------------------------------------------------------*/
747static void enet_rcv (unsigned long malisr)
748{
749 struct enet_frame *ef_ptr;
750 unsigned long data_len;
751 unsigned long rx_eob_isr;
752
753 int handled = 0;
754 int i;
755 int loop_count = 0;
756
757 rx_eob_isr = mfdcr (malrxeobisr);
758 if ((0x80000000 >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
759 /* clear EOB */
760 mtdcr (malrxeobisr, rx_eob_isr);
761
762 /* EMAC RX done */
763 while (1) { /* do all */
764 i = rx_slot;
765
766 if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl)
767 || (loop_count >= NUM_RX_BUFF))
768 break;
769 loop_count++;
770 rx_slot++;
771 if (NUM_RX_BUFF == rx_slot)
772 rx_slot = 0;
773 handled++;
774 data_len = (unsigned long) rx[i].data_len; /* Get len */
775 if (data_len) {
776 if (data_len > ENET_MAX_MTU) /* Check len */
777 data_len = 0;
778 else {
779 if (EMAC_RX_ERRORS & rx[i].ctrl) { /* Check Errors */
780 data_len = 0;
781 stats.rx_err_log[rx_err_index] = rx[i].ctrl;
782 rx_err_index++;
783 if (rx_err_index == MAX_ERR_LOG)
784 rx_err_index = 0;
785 } /* emac_erros */
786 } /* data_len < max mtu */
787 } /* if data_len */
788 if (!data_len) { /* no data */
789 rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
790
791 stats.emac.data_len_err++; /* Error at Rx */
792 }
793
794 /* !data_len */
795 /* AS.HARNOIS */
796 /* Check if user has already eaten buffer */
797 /* if not => ERROR */
798 else if (rx_ready[rx_i_index] != -1) {
799 if (is_receiving)
800 printf ("ERROR : Receive buffers are full!\n");
801 break;
802 } else {
803 stats.emac.rx_frames++;
804 stats.emac.rx += data_len;
805 ef_ptr = (struct enet_frame *) rx[i].data_ptr;
806#ifdef INFO_405_ENET
807 packetReceived++;
808#endif
809 /* AS.HARNOIS
810 * use ring buffer
811 */
812 rx_ready[rx_i_index] = i;
813 rx_i_index++;
814 if (NUM_RX_BUFF == rx_i_index)
815 rx_i_index = 0;
816
817 /* printf("X"); /|* test-only *|/ */
818
819 /* AS.HARNOIS
820 * free receive buffer only when
821 * buffer has been handled (eth_rx)
822 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
823 */
824 } /* if data_len */
825 } /* while */
826 } /* if EMACK_RXCHL */
827}
828
829
a3ed3996 830static int ppc_4xx_eth_rx (struct eth_device *dev)
c609719b
WD		 831{
832 int length;
833 int user_index;
834 unsigned long msr;
835
836 is_receiving = 1; /* tell driver */
837
838 for (;;) {
839 /* AS.HARNOIS
840 * use ring buffer and
841 * get index from rx buffer desciptor queue
842 */
843 user_index = rx_ready[rx_u_index];
844 if (user_index == -1) {
845 length = -1;
846 break; /* nothing received - leave for() loop */
847 }
848
849 msr = mfmsr ();
850 mtmsr (msr & ~(MSR_EE));
851
852 length = rx[user_index].data_len;
853
854 /* Pass the packet up to the protocol layers. */
855 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
856 /* NetReceive(NetRxPackets[i], length); */
857 NetReceive (NetRxPackets[user_index], length - 4);
858 /* Free Recv Buffer */
859 rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
860 /* Free rx buffer descriptor queue */
861 rx_ready[rx_u_index] = -1;
862 rx_u_index++;
863 if (NUM_RX_BUFF == rx_u_index)
864 rx_u_index = 0;
865
866#ifdef INFO_405_ENET
867 packetHandled++;
868#endif
869
870 mtmsr (msr); /* Enable IRQ's */
871 }
872
873 is_receiving = 0; /* tell driver */
874
875 return length;
876}
877
a3ed3996
WD		 878#if defined(CONFIG_NET_MULTI)
879int ppc_4xx_eth_initialize(bd_t *bis)
880{
8bde7f77
WD		 881 struct eth_device *dev;
882 int eth_num = 0;
883
884 dev = malloc (sizeof *dev);
885 if (dev == NULL) {
886 printf(__FUNCTION__ ": Cannot allocate eth_device\n");
887 return (-1);
888 }
889
890 sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
891 dev->priv = (void *) eth_num;
892 dev->init = ppc_4xx_eth_init;
893 dev->halt = ppc_4xx_eth_halt;
894 dev->send = ppc_4xx_eth_send;
895 dev->recv = ppc_4xx_eth_rx;
896
897 eth_register (dev);
a3ed3996
WD		 898}
899#else /* !defined(CONFIG_NET_MULTI) */
900void eth_halt (void)
901{
8bde7f77 902 ppc_4xx_eth_halt(NULL);
a3ed3996
WD		 903}
904
905int eth_init (bd_t *bis)
906{
8bde7f77 907 return (ppc_4xx_eth_init(NULL, bis));
a3ed3996
WD		 908}
909int eth_send(volatile void *packet, int length)
910{
8bde7f77 911 return (ppc_4xx_eth_send(NULL, packet, length));
a3ed3996
WD		 912}
913
914int eth_rx(void)
915{
8bde7f77 916 return (ppc_4xx_eth_rx(NULL));
a3ed3996
WD		 917}
918#endif /* !defined(CONFIG_NET_MULTI) */
919
c609719b 920#endif /* CONFIG_405GP */
"Das U-Boot" Source Tree