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c609719b WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
3 | * This source code has been made available to you by IBM on an AS-IS | |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
9 | * | |
10 | * Any user of this software should understand that IBM cannot provide | |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
13 | * | |
14 | * Any person who transfers this source code or any derivative work | |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
17 | * | |
18 | * COPYRIGHT I B M CORPORATION 1995 | |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
20 | *-----------------------------------------------------------------------------*/ | |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
23 | * File Name: enetemac.c | |
24 | * | |
25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. | |
26 | * | |
27 | * Author: Mark Wisner | |
28 | * | |
29 | * Change Activity- | |
30 | * | |
31 | * Date Description of Change BY | |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
b4676a25 WD |
70 | * 21-Nov-03 pavel.bartusek@sysgo.com |
71 | * - set ZMII bridge speed on 440 | |
72 | * | |
c609719b WD |
73 | *-----------------------------------------------------------------------------*/ |
74 | ||
75 | #include <common.h> | |
76 | #include <asm/processor.h> | |
77 | #include <ppc4xx.h> | |
78 | #include <commproc.h> | |
79 | #include <405gp_enet.h> | |
80 | #include <405_mal.h> | |
81 | #include <miiphy.h> | |
82 | #include <net.h> | |
83 | #include <malloc.h> | |
84 | #include "vecnum.h" | |
85 | ||
ba56f625 WD |
86 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ |
87 | ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI)) | |
c609719b | 88 | |
cea655a2 WD |
89 | #if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP) |
90 | /* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */ | |
91 | #define EMAC_NUM_DEV 1 | |
92 | #else | |
93 | /* 440EP && CONFIG_NET_MULTI */ | |
94 | #define EMAC_NUM_DEV 2 | |
95 | #endif | |
96 | ||
c609719b | 97 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
149dded2 | 98 | #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ |
c609719b | 99 | |
c609719b WD |
100 | /* Ethernet Transmit and Receive Buffers */ |
101 | /* AS.HARNOIS | |
102 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
103 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
104 | */ | |
105 | #define ENET_MAX_MTU PKTSIZE | |
106 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN | |
107 | ||
c609719b | 108 | /* define the number of channels implemented */ |
cea655a2 WD |
109 | #define EMAC_RXCHL EMAC_NUM_DEV |
110 | #define EMAC_TXCHL EMAC_NUM_DEV | |
c609719b WD |
111 | |
112 | /*-----------------------------------------------------------------------------+ | |
113 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
114 | * Interrupt Controller). | |
115 | *-----------------------------------------------------------------------------*/ | |
116 | #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
117 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
118 | #define EMAC_UIC_DEF UIC_ENET | |
cea655a2 WD |
119 | #define EMAC_UIC_DEF1 UIC_ENET1 |
120 | #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) | |
121 | ||
c609719b WD |
122 | |
123 | /*-----------------------------------------------------------------------------+ | |
124 | * Global variables. TX and RX descriptors and buffers. | |
125 | *-----------------------------------------------------------------------------*/ | |
c609719b | 126 | /* IER globals */ |
cea655a2 | 127 | static uint32_t mal_ier; |
c609719b | 128 | |
cea655a2 WD |
129 | #if !defined(CONFIG_NET_MULTI) |
130 | struct eth_device *emac0_dev; | |
131 | #endif | |
c609719b | 132 | |
c609719b WD |
133 | /*-----------------------------------------------------------------------------+ |
134 | * Prototypes and externals. | |
135 | *-----------------------------------------------------------------------------*/ | |
cea655a2 WD |
136 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); |
137 | ||
138 | int enetInt (struct eth_device *dev); | |
139 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
140 | unsigned long uic, unsigned long maldef, | |
141 | unsigned long mal_errr); | |
142 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
c609719b | 143 | |
cea655a2 WD |
144 | /*-----------------------------------------------------------------------------+ |
145 | | ppc_405x_eth_halt | |
146 | | Disable MAL channel, and EMACn | |
147 | | | |
148 | | | |
149 | +-----------------------------------------------------------------------------*/ | |
a3ed3996 | 150 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
c609719b | 151 | { |
cea655a2 WD |
152 | EMAC_405_HW_PST hw_p = dev->priv; |
153 | uint32_t failsafe = 10000; | |
c609719b | 154 | |
cea655a2 WD |
155 | mtdcr (malier, 0x00000000); /* disable mal interrupts */ |
156 | out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ | |
157 | ||
158 | /* 1st reset MAL channel */ | |
159 | /* Note: writing a 0 to a channel has no effect */ | |
160 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
161 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); | |
c609719b WD |
162 | |
163 | /* wait for reset */ | |
cea655a2 WD |
164 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
165 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ | |
166 | failsafe--; | |
167 | if (failsafe == 0) | |
168 | break; | |
169 | ||
170 | } | |
c609719b WD |
171 | |
172 | /* EMAC RESET */ | |
cea655a2 | 173 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
c609719b | 174 | |
cea655a2 | 175 | hw_p->print_speed = 1; /* print speed message again next time */ |
c609719b | 176 | |
cea655a2 WD |
177 | return; |
178 | } | |
c609719b | 179 | |
a3ed3996 | 180 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
c609719b WD |
181 | { |
182 | int i; | |
183 | unsigned long reg; | |
184 | unsigned long msr; | |
185 | unsigned long speed; | |
186 | unsigned long duplex; | |
cea655a2 | 187 | unsigned long failsafe; |
c609719b | 188 | unsigned mode_reg; |
cea655a2 | 189 | unsigned short devnum; |
c609719b WD |
190 | unsigned short reg_short; |
191 | ||
cea655a2 WD |
192 | EMAC_405_HW_PST hw_p = dev->priv; |
193 | /* before doing anything, figure out if we have a MAC address */ | |
194 | /* if not, bail */ | |
195 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) | |
196 | return -1; | |
197 | ||
c609719b WD |
198 | msr = mfmsr (); |
199 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
200 | ||
cea655a2 WD |
201 | devnum = hw_p->devnum; |
202 | ||
c609719b WD |
203 | #ifdef INFO_405_ENET |
204 | /* AS.HARNOIS | |
205 | * We should have : | |
cea655a2 WD |
206 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
207 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it | |
8bde7f77 WD |
208 | * is possible that new packets (without relationship with |
209 | * current transfer) have got the time to arrived before | |
210 | * netloop calls eth_halt | |
c609719b | 211 | */ |
cea655a2 | 212 | printf ("About preceeding transfer (eth%d):\n" |
c609719b WD |
213 | "- Sent packet number %d\n" |
214 | "- Received packet number %d\n" | |
215 | "- Handled packet number %d\n", | |
cea655a2 WD |
216 | hw_p->devnum, |
217 | hw_p->stats.pkts_tx, | |
218 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
219 | ||
220 | hw_p->stats.pkts_tx = 0; | |
221 | hw_p->stats.pkts_rx = 0; | |
222 | hw_p->stats.pkts_handled = 0; | |
c609719b WD |
223 | #endif |
224 | ||
225 | /* MAL RESET */ | |
cea655a2 WD |
226 | mtdcr (malmcr, MAL_CR_MMSR); |
227 | /* wait for reset */ | |
228 | while (mfdcr (malmcr) & MAL_CR_MMSR) { | |
229 | }; | |
230 | #if defined(CONFIG_440) | |
231 | /* set RMII mode */ | |
232 | out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); | |
233 | #endif /* CONFIG_440 */ | |
234 | ||
235 | /* MAL Channel RESET */ | |
236 | /* 1st reset MAL channel */ | |
237 | /* Note: writing a 0 to a channel has no effect */ | |
238 | mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2))); | |
239 | mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum)); | |
240 | ||
241 | /* wait for reset */ | |
242 | /* TBS: should have udelay and failsafe here */ | |
243 | failsafe = 10000; | |
c609719b | 244 | /* wait for reset */ |
cea655a2 WD |
245 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
246 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ | |
247 | failsafe--; | |
248 | if (failsafe == 0) | |
249 | break; | |
c609719b | 250 | |
cea655a2 | 251 | } |
c609719b | 252 | |
cea655a2 WD |
253 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
254 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
c609719b | 255 | |
cea655a2 WD |
256 | hw_p->rx_slot = 0; /* MAL Receive Slot */ |
257 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
258 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
c609719b | 259 | |
cea655a2 WD |
260 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ |
261 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
262 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
c609719b | 263 | |
cea655a2 | 264 | __asm__ volatile ("eieio"); |
c609719b | 265 | |
cea655a2 WD |
266 | /* reset emac so we have access to the phy */ |
267 | ||
268 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); | |
269 | __asm__ volatile ("eieio"); | |
270 | ||
271 | failsafe = 1000; | |
272 | while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { | |
273 | udelay (1000); | |
274 | failsafe--; | |
275 | } | |
276 | ||
277 | #if defined(CONFIG_NET_MULTI) | |
278 | reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR; | |
279 | #else | |
280 | reg = CONFIG_PHY_ADDR; | |
281 | #endif | |
c609719b WD |
282 | /* wait for PHY to complete auto negotiation */ |
283 | reg_short = 0; | |
284 | #ifndef CONFIG_CS8952_PHY | |
cea655a2 | 285 | miiphy_read (reg, PHY_BMSR, ®_short); |
c609719b WD |
286 | |
287 | /* | |
cea655a2 | 288 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
c609719b WD |
289 | */ |
290 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
291 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
292 | puts ("Waiting for PHY auto negotiation to complete"); | |
293 | i = 0; | |
294 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
c609719b WD |
295 | /* |
296 | * Timeout reached ? | |
297 | */ | |
149dded2 | 298 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { |
c609719b WD |
299 | puts (" TIMEOUT !\n"); |
300 | break; | |
301 | } | |
149dded2 | 302 | |
cea655a2 | 303 | if ((i++ % 1000) == 0) { |
149dded2 | 304 | putc ('.'); |
cea655a2 | 305 | } |
149dded2 | 306 | udelay (1000); /* 1 ms */ |
cea655a2 | 307 | miiphy_read (reg, PHY_BMSR, ®_short); |
c609719b WD |
308 | } |
309 | puts (" done\n"); | |
310 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
311 | } | |
312 | #endif | |
cea655a2 WD |
313 | speed = miiphy_speed (reg); |
314 | duplex = miiphy_duplex (reg); | |
315 | ||
316 | if (hw_p->print_speed) { | |
317 | hw_p->print_speed = 0; | |
c609719b WD |
318 | printf ("ENET Speed is %d Mbps - %s duplex connection\n", |
319 | (int) speed, (duplex == HALF) ? "HALF" : "FULL"); | |
320 | } | |
321 | ||
c609719b WD |
322 | #if defined(CONFIG_440) |
323 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ | |
cea655a2 WD |
324 | if( get_pvr() == PVR_440GP_RB) |
325 | mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
c609719b WD |
326 | else |
327 | #else | |
328 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
329 | #endif | |
330 | ||
331 | /* Free "old" buffers */ | |
cea655a2 WD |
332 | if (hw_p->alloc_tx_buf) |
333 | free (hw_p->alloc_tx_buf); | |
334 | if (hw_p->alloc_rx_buf) | |
335 | free (hw_p->alloc_rx_buf); | |
c609719b WD |
336 | |
337 | /* | |
338 | * Malloc MAL buffer desciptors, make sure they are | |
339 | * aligned on cache line boundary size | |
340 | * (401/403/IOP480 = 16, 405 = 32) | |
341 | * and doesn't cross cache block boundaries. | |
342 | */ | |
cea655a2 WD |
343 | hw_p->alloc_tx_buf = |
344 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + | |
345 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
346 | if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { | |
347 | hw_p->tx = | |
348 | (mal_desc_t *) ((int) hw_p->alloc_tx_buf + | |
349 | CFG_CACHELINE_SIZE - | |
350 | ((int) hw_p-> | |
351 | alloc_tx_buf & CACHELINE_MASK)); | |
c609719b | 352 | } else { |
cea655a2 | 353 | hw_p->tx = hw_p->alloc_tx_buf; |
c609719b WD |
354 | } |
355 | ||
cea655a2 WD |
356 | hw_p->alloc_rx_buf = |
357 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + | |
358 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
359 | if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { | |
360 | hw_p->rx = | |
361 | (mal_desc_t *) ((int) hw_p->alloc_rx_buf + | |
362 | CFG_CACHELINE_SIZE - | |
363 | ((int) hw_p-> | |
364 | alloc_rx_buf & CACHELINE_MASK)); | |
c609719b | 365 | } else { |
cea655a2 | 366 | hw_p->rx = hw_p->alloc_rx_buf; |
c609719b WD |
367 | } |
368 | ||
369 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
cea655a2 WD |
370 | hw_p->tx[i].ctrl = 0; |
371 | hw_p->tx[i].data_len = 0; | |
372 | if (hw_p->first_init == 0) | |
373 | hw_p->txbuf_ptr = | |
374 | (char *) malloc (ENET_MAX_MTU_ALIGNED); | |
375 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; | |
c609719b | 376 | if ((NUM_TX_BUFF - 1) == i) |
cea655a2 WD |
377 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; |
378 | hw_p->tx_run[i] = -1; | |
c609719b | 379 | #if 0 |
cea655a2 WD |
380 | printf ("TX_BUFF %d @ 0x%08lx\n", i, |
381 | (ulong) hw_p->tx[i].data_ptr); | |
c609719b WD |
382 | #endif |
383 | } | |
384 | ||
385 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
cea655a2 WD |
386 | hw_p->rx[i].ctrl = 0; |
387 | hw_p->rx[i].data_len = 0; | |
c609719b | 388 | /* rx[i].data_ptr = (char *) &rx_buff[i]; */ |
cea655a2 | 389 | hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; |
c609719b | 390 | if ((NUM_RX_BUFF - 1) == i) |
cea655a2 WD |
391 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; |
392 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
393 | hw_p->rx_ready[i] = -1; | |
c609719b WD |
394 | #if 0 |
395 | printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); | |
396 | #endif | |
397 | } | |
398 | ||
c609719b | 399 | reg = 0x00000000; |
cea655a2 | 400 | reg |= dev->enetaddr[0]; /* set high address */ |
c609719b | 401 | reg = reg << 8; |
cea655a2 | 402 | reg |= dev->enetaddr[1]; |
c609719b | 403 | |
cea655a2 | 404 | out32 (EMAC_IAH + hw_p->hw_addr, reg); |
c609719b WD |
405 | |
406 | reg = 0x00000000; | |
cea655a2 | 407 | reg |= dev->enetaddr[2]; /* set low address */ |
c609719b | 408 | reg = reg << 8; |
cea655a2 | 409 | reg |= dev->enetaddr[3]; |
c609719b | 410 | reg = reg << 8; |
cea655a2 | 411 | reg |= dev->enetaddr[4]; |
c609719b | 412 | reg = reg << 8; |
cea655a2 WD |
413 | reg |= dev->enetaddr[5]; |
414 | ||
415 | out32 (EMAC_IAL + hw_p->hw_addr, reg); | |
416 | switch (devnum) { | |
417 | case 1: | |
418 | /* setup MAL tx & rx channel pointers */ | |
419 | /* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */ | |
420 | mtdcr (maltxctp2r, hw_p->tx); | |
421 | mtdcr (malrxctp1r, hw_p->rx); | |
422 | /* set RX buffer size */ | |
423 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
424 | break; | |
425 | case 0: | |
426 | default: | |
427 | /* setup MAL tx & rx channel pointers */ | |
428 | mtdcr (maltxctp0r, hw_p->tx); | |
429 | mtdcr (malrxctp0r, hw_p->rx); | |
430 | /* set RX buffer size */ | |
431 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
432 | break; | |
433 | } | |
c609719b WD |
434 | |
435 | /* Enable MAL transmit and receive channels */ | |
cea655a2 WD |
436 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2))); |
437 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); | |
c609719b WD |
438 | |
439 | /* set transmit enable & receive enable */ | |
cea655a2 | 440 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
c609719b WD |
441 | |
442 | /* set receive fifo to 4k and tx fifo to 2k */ | |
cea655a2 WD |
443 | mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); |
444 | mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; | |
c609719b WD |
445 | |
446 | /* set speed */ | |
447 | if (speed == _100BASET) | |
448 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; | |
449 | else | |
450 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
451 | if (duplex == FULL) | |
452 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
453 | ||
cea655a2 | 454 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); |
c609719b | 455 | |
b4676a25 WD |
456 | #if defined(CONFIG_440) |
457 | /* set speed in the ZMII bridge */ | |
458 | if (speed == _100BASET) | |
459 | out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000); | |
460 | else | |
461 | out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000); | |
462 | #endif | |
463 | ||
c609719b | 464 | /* Enable broadcast and indvidual address */ |
cea655a2 WD |
465 | /* TBS: enabling runts as some misbehaved nics will send runts */ |
466 | out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); | |
c609719b WD |
467 | |
468 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
469 | ||
470 | /* set transmit request threshold register */ | |
cea655a2 | 471 | out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
c609719b | 472 | |
c609719b WD |
473 | #if defined(CONFIG_440) |
474 | /* 440GP has a 64 byte burst length */ | |
cea655a2 WD |
475 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
476 | out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); | |
477 | #else | |
c609719b | 478 | /* 405s have a 16 byte burst length */ |
cea655a2 WD |
479 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
480 | #endif | |
481 | ||
c609719b WD |
482 | |
483 | /* Frame gap set */ | |
cea655a2 WD |
484 | out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
485 | ||
486 | /* Set EMAC IER */ | |
487 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | | |
488 | EMAC_ISR_ORE | EMAC_ISR_IRE; | |
489 | if (speed == _100BASET) | |
490 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
491 | ||
492 | out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ | |
493 | out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
c609719b | 494 | |
cea655a2 | 495 | if (hw_p->first_init == 0) { |
c609719b WD |
496 | /* |
497 | * Connect interrupt service routines | |
498 | */ | |
cea655a2 WD |
499 | #if !defined(CONFIG_405EP) |
500 | /* 405EP has one EWU interrupt */ | |
501 | irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2), | |
502 | (interrupt_handler_t *) enetInt, dev); | |
503 | #endif | |
504 | irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), | |
505 | (interrupt_handler_t *) enetInt, dev); | |
c609719b WD |
506 | } |
507 | ||
cea655a2 | 508 | mtmsr (msr); /* enable interrupts again */ |
c609719b | 509 | |
cea655a2 WD |
510 | hw_p->bis = bis; |
511 | hw_p->first_init = 1; | |
c609719b | 512 | |
a3ed3996 | 513 | return (1); |
c609719b WD |
514 | } |
515 | ||
516 | ||
a3ed3996 | 517 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len) |
c609719b WD |
518 | { |
519 | struct enet_frame *ef_ptr; | |
520 | ulong time_start, time_now; | |
521 | unsigned long temp_txm0; | |
cea655a2 | 522 | EMAC_405_HW_PST hw_p = dev->priv; |
c609719b WD |
523 | |
524 | ef_ptr = (struct enet_frame *) ptr; | |
525 | ||
526 | /*-----------------------------------------------------------------------+ | |
527 | * Copy in our address into the frame. | |
528 | *-----------------------------------------------------------------------*/ | |
cea655a2 | 529 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); |
c609719b WD |
530 | |
531 | /*-----------------------------------------------------------------------+ | |
532 | * If frame is too long or too short, modify length. | |
533 | *-----------------------------------------------------------------------*/ | |
cea655a2 | 534 | /* TBS: where does the fragment go???? */ |
c609719b WD |
535 | if (len > ENET_MAX_MTU) |
536 | len = ENET_MAX_MTU; | |
537 | ||
538 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
cea655a2 | 539 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); |
c609719b WD |
540 | |
541 | /*-----------------------------------------------------------------------+ | |
542 | * set TX Buffer busy, and send it | |
543 | *-----------------------------------------------------------------------*/ | |
cea655a2 WD |
544 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | |
545 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
c609719b | 546 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); |
cea655a2 WD |
547 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) |
548 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
549 | ||
550 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
551 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
c609719b | 552 | |
cea655a2 | 553 | __asm__ volatile ("eieio"); |
c609719b | 554 | |
cea655a2 WD |
555 | out32 (EMAC_TXM0 + hw_p->hw_addr, |
556 | in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
c609719b | 557 | #ifdef INFO_405_ENET |
cea655a2 | 558 | hw_p->stats.pkts_tx++; |
c609719b WD |
559 | #endif |
560 | ||
561 | /*-----------------------------------------------------------------------+ | |
562 | * poll unitl the packet is sent and then make sure it is OK | |
563 | *-----------------------------------------------------------------------*/ | |
564 | time_start = get_timer (0); | |
565 | while (1) { | |
cea655a2 | 566 | temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); |
c609719b WD |
567 | /* loop until either TINT turns on or 3 seconds elapse */ |
568 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
569 | /* transmit is done, so now check for errors | |
8bde7f77 WD |
570 | * If there is an error, an interrupt should |
571 | * happen when we return | |
c609719b WD |
572 | */ |
573 | time_now = get_timer (0); | |
574 | if ((time_now - time_start) > 3000) { | |
575 | return (-1); | |
576 | } | |
577 | } else { | |
a3ed3996 | 578 | return (len); |
c609719b WD |
579 | } |
580 | } | |
581 | } | |
582 | ||
c609719b | 583 | #if defined(CONFIG_440) |
cea655a2 | 584 | int enetInt (struct eth_device *dev) |
c609719b WD |
585 | { |
586 | int serviced; | |
587 | int rc = -1; /* default to not us */ | |
588 | unsigned long mal_isr; | |
589 | unsigned long emac_isr = 0; | |
590 | unsigned long mal_rx_eob; | |
591 | unsigned long my_uic0msr, my_uic1msr; | |
cea655a2 WD |
592 | EMAC_405_HW_PST hw_p; |
593 | ||
594 | /* | |
595 | * Because the mal is generic, we need to get the current | |
596 | * eth device | |
597 | */ | |
598 | #if defined(CONFIG_NET_MULTI) | |
599 | dev = eth_get_dev(); | |
600 | #else | |
601 | dev = emac0_dev; | |
602 | #endif | |
603 | hw_p = dev->priv; | |
c609719b WD |
604 | |
605 | /* enter loop that stays in interrupt code until nothing to service */ | |
606 | do { | |
607 | serviced = 0; | |
608 | ||
609 | my_uic0msr = mfdcr (uic0msr); | |
610 | my_uic1msr = mfdcr (uic1msr); | |
611 | ||
612 | if (!(my_uic0msr & UIC_MRE) | |
8bde7f77 WD |
613 | && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) { |
614 | /* not for us */ | |
c609719b WD |
615 | return (rc); |
616 | } | |
617 | ||
618 | /* get and clear controller status interrupts */ | |
619 | /* look at Mal and EMAC interrupts */ | |
620 | if ((my_uic0msr & UIC_MRE) | |
8bde7f77 WD |
621 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { |
622 | /* we have a MAL interrupt */ | |
c609719b WD |
623 | mal_isr = mfdcr (malesr); |
624 | /* look for mal error */ | |
625 | if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { | |
cea655a2 | 626 | mal_err (dev, mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR); |
c609719b WD |
627 | serviced = 1; |
628 | rc = 0; | |
629 | } | |
630 | } | |
631 | if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */ | |
cea655a2 WD |
632 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
633 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
634 | emac_err (dev, emac_isr); | |
c609719b WD |
635 | serviced = 1; |
636 | rc = 0; | |
637 | } | |
638 | } | |
cea655a2 | 639 | if ((hw_p->emac_ier & emac_isr) |
8bde7f77 | 640 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { |
c609719b WD |
641 | mtdcr (uic0sr, UIC_MRE); /* Clear */ |
642 | mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
643 | return (rc); /* we had errors so get out */ | |
644 | } | |
645 | ||
646 | /* handle MAL RX EOB interupt from a receive */ | |
647 | /* check for EOB on valid channels */ | |
648 | if (my_uic0msr & UIC_MRE) { | |
649 | mal_rx_eob = mfdcr (malrxeobisr); | |
cea655a2 | 650 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel 0 */ |
c609719b WD |
651 | /* clear EOB |
652 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
cea655a2 | 653 | enet_rcv (dev, emac_isr); |
c609719b WD |
654 | /* indicate that we serviced an interrupt */ |
655 | serviced = 1; | |
656 | rc = 0; | |
657 | } | |
658 | } | |
8bde7f77 WD |
659 | mtdcr (uic0sr, UIC_MRE); /* Clear */ |
660 | mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ | |
c609719b WD |
661 | } while (serviced); |
662 | ||
663 | return (rc); | |
664 | } | |
cea655a2 | 665 | |
c609719b | 666 | #else /* CONFIG_440 */ |
cea655a2 WD |
667 | |
668 | int enetInt (struct eth_device *dev) | |
c609719b WD |
669 | { |
670 | int serviced; | |
cea655a2 | 671 | int rc = -1; /* default to not us */ |
c609719b WD |
672 | unsigned long mal_isr; |
673 | unsigned long emac_isr = 0; | |
674 | unsigned long mal_rx_eob; | |
675 | unsigned long my_uicmsr; | |
676 | ||
cea655a2 WD |
677 | EMAC_405_HW_PST hw_p; |
678 | ||
679 | /* | |
680 | * Because the mal is generic, we need to get the current | |
681 | * eth device | |
682 | */ | |
683 | #if defined(CONFIG_NET_MULTI) | |
684 | dev = eth_get_dev(); | |
685 | #else | |
686 | dev = emac0_dev; | |
687 | #endif | |
688 | ||
689 | hw_p = dev->priv; | |
690 | ||
c609719b WD |
691 | /* enter loop that stays in interrupt code until nothing to service */ |
692 | do { | |
693 | serviced = 0; | |
694 | ||
695 | my_uicmsr = mfdcr (uicmsr); | |
cea655a2 | 696 | |
c609719b WD |
697 | if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ |
698 | return (rc); | |
699 | } | |
c609719b WD |
700 | /* get and clear controller status interrupts */ |
701 | /* look at Mal and EMAC interrupts */ | |
702 | if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ | |
703 | mal_isr = mfdcr (malesr); | |
704 | /* look for mal error */ | |
705 | if ((my_uicmsr & MAL_UIC_ERR) != 0) { | |
cea655a2 | 706 | mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); |
c609719b WD |
707 | serviced = 1; |
708 | rc = 0; | |
709 | } | |
710 | } | |
cea655a2 WD |
711 | |
712 | /* port by port dispatch of emac interrupts */ | |
713 | ||
714 | if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ | |
715 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
716 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
717 | emac_err (dev, emac_isr); | |
c609719b WD |
718 | serviced = 1; |
719 | rc = 0; | |
720 | } | |
721 | } | |
cea655a2 WD |
722 | if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { |
723 | mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ | |
c609719b WD |
724 | return (rc); /* we had errors so get out */ |
725 | } | |
726 | ||
cea655a2 WD |
727 | /* handle MAX TX EOB interrupt from a tx */ |
728 | if (my_uicmsr & UIC_MAL_TXEOB) { | |
729 | mal_rx_eob = mfdcr (maltxeobisr); | |
730 | mtdcr (maltxeobisr, mal_rx_eob); | |
731 | mtdcr (uicsr, UIC_MAL_TXEOB); | |
732 | } | |
c609719b | 733 | /* handle MAL RX EOB interupt from a receive */ |
cea655a2 WD |
734 | /* check for EOB on valid channels */ |
735 | if (my_uicmsr & UIC_MAL_RXEOB) | |
736 | { | |
c609719b | 737 | mal_rx_eob = mfdcr (malrxeobisr); |
cea655a2 | 738 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
c609719b | 739 | /* clear EOB |
cea655a2 WD |
740 | mtdcr(malrxeobisr, mal_rx_eob); */ |
741 | enet_rcv (dev, emac_isr); | |
c609719b WD |
742 | /* indicate that we serviced an interrupt */ |
743 | serviced = 1; | |
744 | rc = 0; | |
745 | } | |
746 | } | |
cea655a2 | 747 | mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ |
c609719b WD |
748 | } |
749 | while (serviced); | |
750 | ||
751 | return (rc); | |
752 | } | |
cea655a2 | 753 | #endif |
c609719b WD |
754 | /*-----------------------------------------------------------------------------+ |
755 | * MAL Error Routine | |
756 | *-----------------------------------------------------------------------------*/ | |
cea655a2 WD |
757 | static void mal_err (struct eth_device *dev, unsigned long isr, |
758 | unsigned long uic, unsigned long maldef, | |
759 | unsigned long mal_errr) | |
c609719b | 760 | { |
cea655a2 WD |
761 | EMAC_405_HW_PST hw_p = dev->priv; |
762 | ||
763 | mtdcr (malesr, isr); /* clear interrupt */ | |
c609719b WD |
764 | |
765 | /* clear DE interrupt */ | |
766 | mtdcr (maltxdeir, 0xC0000000); | |
767 | mtdcr (malrxdeir, 0x80000000); | |
768 | ||
b867d705 | 769 | #ifdef INFO_405_ENET |
cea655a2 | 770 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
b867d705 | 771 | #endif |
c609719b | 772 | |
cea655a2 | 773 | eth_init (hw_p->bis); /* start again... */ |
c609719b WD |
774 | } |
775 | ||
776 | /*-----------------------------------------------------------------------------+ | |
777 | * EMAC Error Routine | |
778 | *-----------------------------------------------------------------------------*/ | |
cea655a2 | 779 | static void emac_err (struct eth_device *dev, unsigned long isr) |
c609719b | 780 | { |
cea655a2 WD |
781 | EMAC_405_HW_PST hw_p = dev->priv; |
782 | ||
783 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
784 | out32 (EMAC_ISR + hw_p->hw_addr, isr); | |
c609719b WD |
785 | } |
786 | ||
787 | /*-----------------------------------------------------------------------------+ | |
788 | * enet_rcv() handles the ethernet receive data | |
789 | *-----------------------------------------------------------------------------*/ | |
cea655a2 | 790 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) |
c609719b WD |
791 | { |
792 | struct enet_frame *ef_ptr; | |
793 | unsigned long data_len; | |
794 | unsigned long rx_eob_isr; | |
cea655a2 | 795 | EMAC_405_HW_PST hw_p = dev->priv; |
c609719b WD |
796 | |
797 | int handled = 0; | |
798 | int i; | |
799 | int loop_count = 0; | |
800 | ||
801 | rx_eob_isr = mfdcr (malrxeobisr); | |
cea655a2 | 802 | if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { |
c609719b WD |
803 | /* clear EOB */ |
804 | mtdcr (malrxeobisr, rx_eob_isr); | |
805 | ||
806 | /* EMAC RX done */ | |
cea655a2 WD |
807 | while (1) { /* do all */ |
808 | i = hw_p->rx_slot; | |
c609719b | 809 | |
cea655a2 | 810 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) |
c609719b WD |
811 | || (loop_count >= NUM_RX_BUFF)) |
812 | break; | |
813 | loop_count++; | |
cea655a2 WD |
814 | hw_p->rx_slot++; |
815 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
816 | hw_p->rx_slot = 0; | |
c609719b | 817 | handled++; |
cea655a2 | 818 | data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ |
c609719b WD |
819 | if (data_len) { |
820 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
821 | data_len = 0; | |
822 | else { | |
cea655a2 | 823 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ |
c609719b | 824 | data_len = 0; |
cea655a2 WD |
825 | hw_p->stats.rx_err_log[hw_p-> |
826 | rx_err_index] | |
827 | = hw_p->rx[i].ctrl; | |
828 | hw_p->rx_err_index++; | |
829 | if (hw_p->rx_err_index == | |
830 | MAX_ERR_LOG) | |
831 | hw_p->rx_err_index = | |
832 | 0; | |
833 | } /* emac_erros */ | |
834 | } /* data_len < max mtu */ | |
835 | } /* if data_len */ | |
c609719b | 836 | if (!data_len) { /* no data */ |
cea655a2 | 837 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ |
c609719b | 838 | |
cea655a2 | 839 | hw_p->stats.data_len_err++; /* Error at Rx */ |
c609719b WD |
840 | } |
841 | ||
842 | /* !data_len */ | |
843 | /* AS.HARNOIS */ | |
844 | /* Check if user has already eaten buffer */ | |
845 | /* if not => ERROR */ | |
cea655a2 WD |
846 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { |
847 | if (hw_p->is_receiving) | |
c609719b WD |
848 | printf ("ERROR : Receive buffers are full!\n"); |
849 | break; | |
850 | } else { | |
cea655a2 WD |
851 | hw_p->stats.rx_frames++; |
852 | hw_p->stats.rx += data_len; | |
853 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
854 | data_ptr; | |
c609719b | 855 | #ifdef INFO_405_ENET |
cea655a2 | 856 | hw_p->stats.pkts_rx++; |
c609719b WD |
857 | #endif |
858 | /* AS.HARNOIS | |
859 | * use ring buffer | |
860 | */ | |
cea655a2 WD |
861 | hw_p->rx_ready[hw_p->rx_i_index] = i; |
862 | hw_p->rx_i_index++; | |
863 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
864 | hw_p->rx_i_index = 0; | |
c609719b WD |
865 | |
866 | /* printf("X"); /|* test-only *|/ */ | |
867 | ||
868 | /* AS.HARNOIS | |
869 | * free receive buffer only when | |
870 | * buffer has been handled (eth_rx) | |
871 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
cea655a2 WD |
872 | */ |
873 | } /* if data_len */ | |
874 | } /* while */ | |
875 | } /* if EMACK_RXCHL */ | |
c609719b WD |
876 | } |
877 | ||
878 | ||
a3ed3996 | 879 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
c609719b WD |
880 | { |
881 | int length; | |
882 | int user_index; | |
883 | unsigned long msr; | |
cea655a2 | 884 | EMAC_405_HW_PST hw_p = dev->priv; |
c609719b | 885 | |
cea655a2 | 886 | hw_p->is_receiving = 1; /* tell driver */ |
c609719b WD |
887 | |
888 | for (;;) { | |
889 | /* AS.HARNOIS | |
890 | * use ring buffer and | |
891 | * get index from rx buffer desciptor queue | |
892 | */ | |
cea655a2 | 893 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; |
c609719b WD |
894 | if (user_index == -1) { |
895 | length = -1; | |
896 | break; /* nothing received - leave for() loop */ | |
897 | } | |
898 | ||
899 | msr = mfmsr (); | |
900 | mtmsr (msr & ~(MSR_EE)); | |
901 | ||
cea655a2 | 902 | length = hw_p->rx[user_index].data_len; |
c609719b WD |
903 | |
904 | /* Pass the packet up to the protocol layers. */ | |
905 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ | |
906 | /* NetReceive(NetRxPackets[i], length); */ | |
907 | NetReceive (NetRxPackets[user_index], length - 4); | |
908 | /* Free Recv Buffer */ | |
cea655a2 | 909 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; |
c609719b | 910 | /* Free rx buffer descriptor queue */ |
cea655a2 WD |
911 | hw_p->rx_ready[hw_p->rx_u_index] = -1; |
912 | hw_p->rx_u_index++; | |
913 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
914 | hw_p->rx_u_index = 0; | |
c609719b WD |
915 | |
916 | #ifdef INFO_405_ENET | |
cea655a2 | 917 | hw_p->stats.pkts_handled++; |
c609719b WD |
918 | #endif |
919 | ||
cea655a2 | 920 | mtmsr (msr); /* Enable IRQ's */ |
c609719b WD |
921 | } |
922 | ||
cea655a2 | 923 | hw_p->is_receiving = 0; /* tell driver */ |
c609719b WD |
924 | |
925 | return length; | |
926 | } | |
927 | ||
cea655a2 WD |
928 | static int virgin = 0; |
929 | int ppc_4xx_eth_initialize (bd_t * bis) | |
a3ed3996 | 930 | { |
8bde7f77 | 931 | struct eth_device *dev; |
cea655a2 | 932 | int eth_num = 0; |
8bde7f77 | 933 | |
cea655a2 | 934 | EMAC_405_HW_PST hw = NULL; |
8bde7f77 | 935 | |
cea655a2 WD |
936 | for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) { |
937 | ||
938 | /* Allocate device structure */ | |
939 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
940 | if (dev == NULL) { | |
941 | printf ("ppc_405x_eth_initialize: " | |
942 | "Cannot allocate eth_device %d\n", eth_num); | |
943 | return (-1); | |
944 | } | |
945 | /* Allocate our private use data */ | |
946 | hw = (EMAC_405_HW_PST) malloc (sizeof (*hw)); | |
947 | if (hw == NULL) { | |
948 | printf ("ppc_405x_eth_initialize: " | |
949 | "Cannot allocate private hw data for eth_device %d", | |
950 | eth_num); | |
951 | free (dev); | |
952 | return (-1); | |
953 | } | |
8bde7f77 | 954 | |
cea655a2 WD |
955 | switch (eth_num) { |
956 | case 0: | |
957 | hw->hw_addr = 0; | |
958 | memcpy (dev->enetaddr, bis->bi_enetaddr, 6); | |
959 | break; | |
960 | #if defined(CONFIG_NET_MULTI) | |
961 | case 1: | |
962 | hw->hw_addr = 0x100; | |
963 | memcpy (dev->enetaddr, bis->bi_enet1addr, 6); | |
964 | break; | |
965 | #endif | |
966 | default: | |
967 | hw->hw_addr = 0; | |
968 | memcpy (dev->enetaddr, bis->bi_enetaddr, 6); | |
969 | break; | |
970 | } | |
971 | ||
972 | hw->devnum = eth_num; | |
973 | hw->print_speed = 1; | |
974 | ||
975 | sprintf (dev->name, "ppc_405x_eth%d", eth_num); | |
976 | dev->priv = (void *) hw; | |
977 | dev->init = ppc_4xx_eth_init; | |
978 | dev->halt = ppc_4xx_eth_halt; | |
979 | dev->send = ppc_4xx_eth_send; | |
980 | dev->recv = ppc_4xx_eth_rx; | |
981 | ||
982 | if (0 == virgin) { | |
983 | /* set the MAL IER ??? names may change with new spec ??? */ | |
984 | mal_ier = | |
985 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
986 | MAL_IER_OPBE | MAL_IER_PLBE; | |
987 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ | |
988 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
989 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
990 | mtdcr (malier, mal_ier); | |
991 | ||
992 | #if defined(CONFIG_405EP) | |
993 | /* 405EP has one EWU interrupt */ | |
994 | irq_install_handler (VECNUM_EWU0, | |
995 | (interrupt_handler_t *) enetInt, | |
996 | dev); | |
997 | #endif | |
998 | /* install MAL interrupt handler */ | |
999 | irq_install_handler (VECNUM_MS, | |
1000 | (interrupt_handler_t *) enetInt, | |
1001 | dev); | |
1002 | irq_install_handler (VECNUM_MTE, | |
1003 | (interrupt_handler_t *) enetInt, | |
1004 | dev); | |
1005 | irq_install_handler (VECNUM_MRE, | |
1006 | (interrupt_handler_t *) enetInt, | |
1007 | dev); | |
1008 | irq_install_handler (VECNUM_TXDE, | |
1009 | (interrupt_handler_t *) enetInt, | |
1010 | dev); | |
1011 | irq_install_handler (VECNUM_RXDE, | |
1012 | (interrupt_handler_t *) enetInt, | |
1013 | dev); | |
1014 | virgin = 1; | |
1015 | } | |
1016 | ||
1017 | #if defined(CONFIG_NET_MULTI) | |
1018 | eth_register (dev); | |
1019 | #else | |
1020 | emac0_dev = dev; | |
1021 | #endif | |
1022 | ||
1023 | } /* end for each supported device */ | |
1024 | ||
1025 | return (1); | |
a3ed3996 | 1026 | } |
cea655a2 WD |
1027 | |
1028 | #if !defined(CONFIG_NET_MULTI) | |
1029 | void eth_halt (void) { | |
1030 | if (emac0_dev) { | |
1031 | ppc_4xx_eth_halt(emac0_dev); | |
1032 | free(emac0_dev); | |
1033 | emac0_dev = NULL; | |
1034 | } | |
a3ed3996 WD |
1035 | } |
1036 | ||
1037 | int eth_init (bd_t *bis) | |
1038 | { | |
cea655a2 WD |
1039 | ppc_4xx_eth_initialize(bis); |
1040 | return(ppc_4xx_eth_init(emac0_dev, bis)); | |
a3ed3996 | 1041 | } |
cea655a2 | 1042 | |
a3ed3996 WD |
1043 | int eth_send(volatile void *packet, int length) |
1044 | { | |
cea655a2 WD |
1045 | |
1046 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); | |
a3ed3996 WD |
1047 | } |
1048 | ||
1049 | int eth_rx(void) | |
1050 | { | |
cea655a2 | 1051 | return (ppc_4xx_eth_rx(emac0_dev)); |
a3ed3996 | 1052 | } |
cea655a2 | 1053 | #endif |
a3ed3996 | 1054 | |
cea655a2 | 1055 | #endif /* CONFIG_405 */ |