[people/ms/u-boot.git] / cpu / ppc4xx / 405gp_pci.c

/*-----------------------------------------------------------------------------+
 *
 *       This source code has been made available to you by IBM on an AS-IS
 *       basis.  Anyone receiving this source is licensed under IBM
 *       copyrights to use it in any way he or she deems fit, including
 *       copying it, modifying it, compiling it, and redistributing it either
 *       with or without modifications.  No license under IBM patents or
 *       patent applications is to be implied by the copyright license.
 *
 *       Any user of this software should understand that IBM cannot provide
 *       technical support for this software and will not be responsible for
 *       any consequences resulting from the use of this software.
 *
 *       Any person who transfers this source code or any derivative work
 *       must include the IBM copyright notice, this paragraph, and the
 *       preceding two paragraphs in the transferred software.
 *
 *       COPYRIGHT   I B M   CORPORATION 1995
 *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
 *
 *  File Name:   405gp_pci.c
 *
 *  Function:    Initialization code for the 405GP PCI Configuration regs.
 *
 *  Author:      Mark Game
 *
 *  Change Activity-
 *
 *  Date        Description of Change                                       BY
 *  ---------   ---------------------                                       ---
 *  09-Sep-98   Created                                                     MCG
 *  02-Nov-98   Removed External arbiter selected message                   JWB
 *  27-Nov-98   Zero out PTMBAR2 and disable in PTM2MS                      JWB
 *  04-Jan-99   Zero out other unused PMM and PTM regs. Change bus scan     MCG
 *              from (0 to n) to (1 to n).
 *  17-May-99   Port to Walnut                                              JWB
 *  17-Jun-99   Updated for VGA support                                     JWB
 *  21-Jun-99   Updated to allow SRAM region to be a target from PCI bus    JWB
 *  19-Jul-99   Updated for 405GP pass 1 errata #26 (Low PCI subsequent     MCG
 *              target latency timer values are not supported).
 *              Should be fixed in pass 2.
 *  09-Sep-99   Removed use of PTM2 since the SRAM region no longer needs   JWB
 *              to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
 *  10-Dec-99   Updated PCI_Write_CFG_Reg for pass2 errata #6               JWB
 *  11-Jan-00   Ensure PMMxMAs disabled before setting PMMxLAs. This is not
 *              really required after a reset since PMMxMAs are already
 * 	        disabled but is a good practice nonetheless.                JWB
 *  12-Jun-01   stefan.roese@esd-electronics.com
 *              - PCI host/adapter handling reworked
 *  09-Jul-01   stefan.roese@esd-electronics.com
 *              - PCI host now configures from device 0 (not 1) to max_dev,
 *                (host configures itself)
 *              - On CPCI-405 pci base address and size is generated from
 *                SDRAM and FLASH size (CFG regs not used anymore)
 *              - Some minor changes for CPCI-405-A (adapter version)
 *  14-Sep-01   stefan.roese@esd-electronics.com
 *              - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
 *  28-Sep-01   stefan.roese@esd-electronics.com
 *              - Changed pci master configuration for linux compatibility
 *                (no need for bios_fixup() anymore)
 *  26-Feb-02   stefan.roese@esd-electronics.com
 *              - Bug fixed in pci configuration (Andrew May)
 *              - Removed pci class code init for CPCI405 board
 *  15-May-02   stefan.roese@esd-electronics.com
 *              - New vga device handling
 *  29-May-02   stefan.roese@esd-electronics.com
 *              - PCI class code init added (if defined)
 *----------------------------------------------------------------------------*/

#include <common.h>
#include <command.h>
#include <cmd_boot.h>
#if !defined(CONFIG_440)
#include <405gp_pci.h>
#endif
#include <asm/processor.h>
#include <pci.h>

#if defined(CONFIG_405GP) || defined(CONFIG_405EP)

#ifdef CONFIG_PCI

/*#define DEBUG*/

/*-----------------------------------------------------------------------------+
 * pci_init.  Initializes the 405GP PCI Configuration regs.
 *-----------------------------------------------------------------------------*/
void pci_405gp_init(struct pci_controller *hose)
{
	DECLARE_GLOBAL_DATA_PTR;

	int i, reg_num = 0;
	bd_t *bd = gd->bd;

	unsigned short temp_short;
	unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405)
	unsigned long ptmla[2]    = {bd->bi_memstart, bd->bi_flashstart};
	unsigned long ptmms[2]    = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
#else
	unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
	unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
	unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
	unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
	unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
	unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
#else
	unsigned long pmmla[3]    = {0x80000000, 0,0};
	unsigned long pmmma[3]    = {0xC0000001, 0,0};
	unsigned long pmmpcila[3] = {0x80000000, 0,0};
	unsigned long pmmpciha[3] = {0x00000000, 0,0};
#endif

	/*
	 * Register the hose
	 */
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* ISA/PCI I/O space */
	pci_set_region(hose->regions + reg_num++,
		       MIN_PCI_PCI_IOADDR,
		       MIN_PLB_PCI_IOADDR,
		       0x10000,
		       PCI_REGION_IO);

	/* PCI I/O space */
	pci_set_region(hose->regions + reg_num++,
		       0x00800000,
		       0xe8800000,
		       0x03800000,
		       PCI_REGION_IO);

	reg_num = 2;

	/* Memory spaces */
	for (i=0; i<2; i++)
		if (ptmms[i] & 1)
		{
			if (!i) hose->pci_fb = hose->regions + reg_num;

			pci_set_region(hose->regions + reg_num++,
				       ptmpcila[i], ptmla[i],
				       ~(ptmms[i] & 0xfffff000) + 1,
				       PCI_REGION_MEM |
				       PCI_REGION_MEMORY);
		}

	/* PCI memory spaces */
	for (i=0; i<3; i++)
		if (pmmma[i] & 1)
		{
			pci_set_region(hose->regions + reg_num++,
				       pmmpcila[i], pmmla[i],
				       ~(pmmma[i] & 0xfffff000) + 1,
				       PCI_REGION_MEM);
		}

	hose->region_count = reg_num;

	pci_setup_indirect(hose,
			   PCICFGADR,
			   PCICFGDATA);

	if (hose->pci_fb)
		pciauto_region_init(hose->pci_fb);

	pci_register_hose(hose);

	/*--------------------------------------------------------------------------+
	 * 405GP PCI Master configuration.
	 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
	 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
	 * Use byte reversed out routines to handle endianess.
	 *--------------------------------------------------------------------------*/
	out32r(PMM0MA,    (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
	out32r(PMM0LA,    pmmla[0]);
	out32r(PMM0PCILA, pmmpcila[0]);
	out32r(PMM0PCIHA, pmmpciha[0]);
	out32r(PMM0MA,    pmmma[0]);

	/*--------------------------------------------------------------------------+
	 * PMM1 is not used.  Initialize them to zero.
	 *--------------------------------------------------------------------------*/
	out32r(PMM1MA,    (pmmma[1]&~0x1));
	out32r(PMM1LA,    pmmla[1]);
	out32r(PMM1PCILA, pmmpcila[1]);
	out32r(PMM1PCIHA, pmmpciha[1]);
	out32r(PMM1MA,    pmmma[1]);

	/*--------------------------------------------------------------------------+
	 * PMM2 is not used.  Initialize them to zero.
	 *--------------------------------------------------------------------------*/
	out32r(PMM2MA,    (pmmma[2]&~0x1)); 
	out32r(PMM2LA,    pmmla[2]);
	out32r(PMM2PCILA, pmmpcila[2]);
	out32r(PMM2PCIHA, pmmpciha[2]);
	out32r(PMM2MA,    pmmma[2]);

	/*--------------------------------------------------------------------------+
	 * 405GP PCI Target configuration.  (PTM1)
	 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
	 *--------------------------------------------------------------------------*/
	out32r(PTM1LA,    ptmla[0]);         /* insert address                     */
	out32r(PTM1MS,    ptmms[0]);         /* insert size, enable bit is 1       */

	/*--------------------------------------------------------------------------+
	 * 405GP PCI Target configuration.  (PTM2)
	 *--------------------------------------------------------------------------*/
	out32r(PTM2LA, ptmla[1]);            /* insert address                     */
	if (ptmms[1] == 0)
	{
		out32r(PTM2MS,    0x00000001);   /* set enable bit                     */
		pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
		out32r(PTM2MS,    0x00000000);   /* disable                            */
	}
	else
	{
		out32r(PTM2MS, ptmms[1]);        /* insert size, enable bit is 1       */
	}

	/*
	 * Insert Subsystem Vendor and Device ID
	 */
	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
#ifdef CONFIG_CPCI405
	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
	else
		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
#else
	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
#endif

	/*
	 * Insert Class-code
	 */
#ifdef CFG_PCI_CLASSCODE
	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
#endif /* CFG_PCI_CLASSCODE */

	/*--------------------------------------------------------------------------+
	 * If PCI speed = 66Mhz, set 66Mhz capable bit.
	 *--------------------------------------------------------------------------*/
	if (bd->bi_pci_busfreq >= 66000000) {
		pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
		pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
	}

#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
#if (CONFIG_PCI_HOSE == PCI_HOST_AUTO)
	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
#endif
	{
		/*--------------------------------------------------------------------------+
		 * Write the 405GP PCI Configuration regs.
		 * Enable 405GP to be a master on the PCI bus (PMM).
		 * Enable 405GP to act as a PCI memory target (PTM).
		 *--------------------------------------------------------------------------*/
		pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
		pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
				      PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
	}
#endif

	/*
	 * Set HCE bit (Host Configuration Enabled)
	 */
	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));

#ifdef CONFIG_PCI_PNP
	/*--------------------------------------------------------------------------+
	 * Scan the PCI bus and configure devices found.
	 *--------------------------------------------------------------------------*/
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
#endif
	{
#ifdef CONFIG_PCI_SCAN_SHOW
		printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif

		hose->last_busno = pci_hose_scan(hose);
	}
#endif  /* CONFIG_PCI_PNP */

}

/*
 * drivers/pci.c skips every host bridge but the 405GP since it could
 * be set as an Adapter.
 *
 * I (Andrew May) don't know what we should do here, but I don't want
 * the auto setup of a PCI device disabling what is done pci_405gp_init
 * as has happened before.
 */
void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
			    struct pci_config_table *entry)
{
#ifdef DEBUG
        printf("405gp_setup_bridge\n");
#endif
}

/*
 *
 */

void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned char int_line = 0xff;

	/*
	 * Write pci interrupt line register (cpci405 specific)
	 */
	switch (PCI_DEV(dev) & 0x03)
	{
	case 0:
		int_line = 27 + 2;
		break;
	case 1:
		int_line = 27 + 3;
		break;
	case 2:
		int_line = 27 + 0;
		break;
	case 3:
		int_line = 27 + 1;
		break;
	}

	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}

void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
			 struct pci_config_table *entry)
{
	unsigned int cmdstat = 0;

	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);

	/* always enable io space on vga boards */
	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat |= PCI_COMMAND_IO;
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}

#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))

/*
 *As is these functs get called out of flash Not a horrible
 *thing, but something to keep in mind. (no statics?)
 */
static struct pci_config_table pci_405gp_config_table[] = {
/*if VendID is 0 it terminates the table search (ie Walnut)*/
#if CFG_PCI_SUBSYS_VENDORID
	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
#endif
	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},

	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},

	{ }
};

static struct pci_controller hose = {
	fixup_irq: pci_405gp_fixup_irq,
	config_table: pci_405gp_config_table,
};

void pci_init_board(void)
{
	/*we want the ptrs to RAM not flash (ie don't use init list)*/
	hose.fixup_irq    = pci_405gp_fixup_irq;
	hose.config_table = pci_405gp_config_table;
	pci_405gp_init(&hose);
}

#endif

#endif /* CONFIG_PCI */

#endif /* CONFIG_405GP */

/*-----------------------------------------------------------------------------+
 * CONFIG_440
 *-----------------------------------------------------------------------------*/
#if defined(CONFIG_440) && defined(CONFIG_PCI)

static struct pci_controller ppc440_hose = {0};


void pci_440_init (struct pci_controller *hose)
{
	int reg_num = 0;
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 * The PCI initialization sequence enable bit must be set ... if not abort
     * pci setup since updating the bit requires chip reset.
	 *--------------------------------------------------------------------------*/
    strap = mfdcr(cpc0_strp1);
    if( (strap & 0x00040000) == 0 ){
        printf("PCI: CPC0_STRP1[PISE] not set.\n");
        printf("PCI: Configuration aborted.\n");
        return;
    }

	/*--------------------------------------------------------------------------+
	 * PCI controller init
	 *--------------------------------------------------------------------------*/
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + reg_num++,
		       0x00000000,
			   PCIX0_IOBASE,
			   0x10000,
			   PCI_REGION_IO);

	pci_set_region(hose->regions + reg_num++,
		       CFG_PCI_TARGBASE,
			   CFG_PCI_MEMBASE,
			   0x10000000,
			   PCI_REGION_MEM );
	hose->region_count = reg_num;

	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);

#if defined(CFG_PCI_PRE_INIT)
    /* Let board change/modify hose & do initial checks */
    if( pci_pre_init (hose) == 0 ){
        printf("PCI: Board-specific initialization failed.\n");
        printf("PCI: Configuration aborted.\n");
        return;
    }
#endif

	pci_register_hose( hose );

	/*--------------------------------------------------------------------------+
	 * PCI target init
	 *--------------------------------------------------------------------------*/
#if defined(CFG_PCI_TARGET_INIT)
	pci_target_init(hose);                /* Let board setup pci target */
#else
    out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
    out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
    out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif

    out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
    out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */

	/*--------------------------------------------------------------------------+
	 * PCI master init: default is one 256MB region for PCI memory:
	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
	 *--------------------------------------------------------------------------*/
#if defined(CFG_PCI_MASTER_INIT)
	pci_master_init(hose);          /* Let board setup pci master */
#else
	out32r( PCIX0_POM0SA, 0 ); /* disable */
	out32r( PCIX0_POM1SA, 0 ); /* disable */
	out32r( PCIX0_POM2SA, 0 ); /* disable */
	out32r( PCIX0_POM0LAL, 0x00000000 );
	out32r( PCIX0_POM0LAH, 0x00000003 );
	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
	out32r( PCIX0_POM0PCIAH, 0x00000000 );
	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
    out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif

	/*--------------------------------------------------------------------------+
	 * PCI host configuration -- we don't make any assumptions here ... the
     * _board_must_indicate_ what to do -- there's just too many runtime
     * scenarios in environments like cPCI, PPMC, etc. to make a determination
     * based on hard-coded values or state of arbiter enable.
	 *--------------------------------------------------------------------------*/
    if( is_pci_host(hose) ){
#ifdef CONFIG_PCI_SCAN_SHOW
        printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
        out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
        hose->last_busno = pci_hose_scan(hose);
    }
}


void pci_init_board(void)
{
	pci_440_init (&ppc440_hose);
}

#endif /* CONFIG_440 & CONFIG_PCI */
Commit	Line	Data
c609719b WD	1	/*-----------------------------------------------------------------------------+
	2	*
	3	* This source code has been made available to you by IBM on an AS-IS
	4	* basis. Anyone receiving this source is licensed under IBM
	5	* copyrights to use it in any way he or she deems fit, including
	6	* copying it, modifying it, compiling it, and redistributing it either
	7	* with or without modifications. No license under IBM patents or
	8	* patent applications is to be implied by the copyright license.
	9	*
	10	* Any user of this software should understand that IBM cannot provide
	11	* technical support for this software and will not be responsible for
	12	* any consequences resulting from the use of this software.
	13	*
	14	* Any person who transfers this source code or any derivative work
	15	* must include the IBM copyright notice, this paragraph, and the
	16	* preceding two paragraphs in the transferred software.
	17	*
	18	* COPYRIGHT I B M CORPORATION 1995
	19	* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
	20	-----------------------------------------------------------------------------/
	21	/*----------------------------------------------------------------------------+
	22	*
	23	* File Name: 405gp_pci.c
	24	*
	25	* Function: Initialization code for the 405GP PCI Configuration regs.
	26	*
	27	* Author: Mark Game
	28	*
	29	* Change Activity-
	30	*
	31	* Date Description of Change BY
	32	* --------- --------------------- ---
	33	* 09-Sep-98 Created MCG
	34	* 02-Nov-98 Removed External arbiter selected message JWB
	35	* 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
	36	* 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
	37	* from (0 to n) to (1 to n).
	38	* 17-May-99 Port to Walnut JWB
	39	* 17-Jun-99 Updated for VGA support JWB
	40	* 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
	41	* 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
	42	* target latency timer values are not supported).
	43	* Should be fixed in pass 2.
	44	* 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
	45	* to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
	46	* 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
	47	* 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
	48	* really required after a reset since PMMxMAs are already
	49	* disabled but is a good practice nonetheless. JWB
	50	* 12-Jun-01 stefan.roese@esd-electronics.com
	51	* - PCI host/adapter handling reworked
	52	* 09-Jul-01 stefan.roese@esd-electronics.com
	53	* - PCI host now configures from device 0 (not 1) to max_dev,
	54	* (host configures itself)
	55	* - On CPCI-405 pci base address and size is generated from
	56	* SDRAM and FLASH size (CFG regs not used anymore)
	57	* - Some minor changes for CPCI-405-A (adapter version)
	58	* 14-Sep-01 stefan.roese@esd-electronics.com
	59	* - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
	60	* 28-Sep-01 stefan.roese@esd-electronics.com
	61	* - Changed pci master configuration for linux compatibility
	62	* (no need for bios_fixup() anymore)
	63	* 26-Feb-02 stefan.roese@esd-electronics.com
	64	* - Bug fixed in pci configuration (Andrew May)
65	* - Removed pci class code init for CPCI405 board
66	* 15-May-02 stefan.roese@esd-electronics.com
67	* - New vga device handling
68	* 29-May-02 stefan.roese@esd-electronics.com
69	* - PCI class code init added (if defined)
70	----------------------------------------------------------------------------/
71
72	#include <common.h>
73	#include <command.h>
74	#include <cmd_boot.h>
75	#if !defined(CONFIG_440)
76	#include <405gp_pci.h>
77	#endif
78	#include <asm/processor.h>
79	#include <pci.h>
80
b867d705	81	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
c609719b WD	82
	83	#ifdef CONFIG_PCI
	84
	85	/#define DEBUG/
	86
	87	/*-----------------------------------------------------------------------------+
	88	* pci_init. Initializes the 405GP PCI Configuration regs.
	89	-----------------------------------------------------------------------------/
	90	void pci_405gp_init(struct pci_controller *hose)
	91	{
	92	DECLARE_GLOBAL_DATA_PTR;
	93
	94	int i, reg_num = 0;
	95	bd_t *bd = gd->bd;
	96
	97	unsigned short temp_short;
	98	unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
	99	#if defined(CONFIG_CPCI405)
	100	unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
	101	unsigned long ptmms[2] = {~(bd->bi_memsize - 1) \| 1, ~(bd->bi_flashsize - 1) \| 1};
	102	#else
	103	unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
	104	unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
	105	#endif
	106	#if defined(CONFIG_PIP405) \|\| defined (CONFIG_MIP405)
	107	unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
	108	unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
	109	unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
	110	unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
	111	#else
	112	unsigned long pmmla[3] = {0x80000000, 0,0};
	113	unsigned long pmmma[3] = {0xC0000001, 0,0};
	114	unsigned long pmmpcila[3] = {0x80000000, 0,0};
	115	unsigned long pmmpciha[3] = {0x00000000, 0,0};
	116	#endif
	117
	118	/*
	119	* Register the hose
	120	*/
	121	hose->first_busno = 0;
	122	hose->last_busno = 0xff;
	123
	124	/* ISA/PCI I/O space */
	125	pci_set_region(hose->regions + reg_num++,
	126	MIN_PCI_PCI_IOADDR,
	127	MIN_PLB_PCI_IOADDR,
	128	0x10000,
	129	PCI_REGION_IO);
	130
	131	/* PCI I/O space */
	132	pci_set_region(hose->regions + reg_num++,
	133	0x00800000,
	134	0xe8800000,
	135	0x03800000,
	136	PCI_REGION_IO);
	137
	138	reg_num = 2;
	139
	140	/* Memory spaces */
	141	for (i=0; i<2; i++)
	142	if (ptmms[i] & 1)
	143	{
	144	if (!i) hose->pci_fb = hose->regions + reg_num;
	145
146	pci_set_region(hose->regions + reg_num++,
147	ptmpcila[i], ptmla[i],
148	~(ptmms[i] & 0xfffff000) + 1,
149	PCI_REGION_MEM \|
150	PCI_REGION_MEMORY);
151	}
152
153	/* PCI memory spaces */
154	for (i=0; i<3; i++)
155	if (pmmma[i] & 1)
156	{
157	pci_set_region(hose->regions + reg_num++,
158	pmmpcila[i], pmmla[i],
159	~(pmmma[i] & 0xfffff000) + 1,
160	PCI_REGION_MEM);
161	}
162
163	hose->region_count = reg_num;
164
165	pci_setup_indirect(hose,
166	PCICFGADR,
167	PCICFGDATA);
168
169	if (hose->pci_fb)
170	pciauto_region_init(hose->pci_fb);
171
172	pci_register_hose(hose);
173
174	/*--------------------------------------------------------------------------+
175	* 405GP PCI Master configuration.
176	* Map one 512 MB range of PLB/processor addresses to PCI memory space.
177	* PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
178	* Use byte reversed out routines to handle endianess.
179	--------------------------------------------------------------------------/
f3e0de60	180	out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
c609719b WD	181	out32r(PMM0LA, pmmla[0]);
	182	out32r(PMM0PCILA, pmmpcila[0]);
	183	out32r(PMM0PCIHA, pmmpciha[0]);
	184	out32r(PMM0MA, pmmma[0]);
	185
	186	/*--------------------------------------------------------------------------+
	187	* PMM1 is not used. Initialize them to zero.
	188	--------------------------------------------------------------------------/
f3e0de60	189	out32r(PMM1MA, (pmmma[1]&~0x1));
c609719b WD	190	out32r(PMM1LA, pmmla[1]);
	191	out32r(PMM1PCILA, pmmpcila[1]);
	192	out32r(PMM1PCIHA, pmmpciha[1]);
	193	out32r(PMM1MA, pmmma[1]);
	194
	195	/*--------------------------------------------------------------------------+
	196	* PMM2 is not used. Initialize them to zero.
	197	--------------------------------------------------------------------------/
f3e0de60	198	out32r(PMM2MA, (pmmma[2]&~0x1));
c609719b WD	199	out32r(PMM2LA, pmmla[2]);
	200	out32r(PMM2PCILA, pmmpcila[2]);
	201	out32r(PMM2PCIHA, pmmpciha[2]);
	202	out32r(PMM2MA, pmmma[2]);
	203
	204	/*--------------------------------------------------------------------------+
	205	* 405GP PCI Target configuration. (PTM1)
	206	* Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
	207	--------------------------------------------------------------------------/
	208	out32r(PTM1LA, ptmla[0]); /* insert address */
	209	out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
	210
	211	/*--------------------------------------------------------------------------+
	212	* 405GP PCI Target configuration. (PTM2)
	213	--------------------------------------------------------------------------/
	214	out32r(PTM2LA, ptmla[1]); /* insert address */
	215	if (ptmms[1] == 0)
	216	{
	217	out32r(PTM2MS, 0x00000001); /* set enable bit */
	218	pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
	219	out32r(PTM2MS, 0x00000000); /* disable */
	220	}
	221	else
	222	{
	223	out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
	224	}
	225
	226	/*
	227	* Insert Subsystem Vendor and Device ID
	228	*/
	229	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
	230	#ifdef CONFIG_CPCI405
	231	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
	232	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
	233	else
	234	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
	235	#else
	236	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
	237	#endif
	238
	239	/*
	240	* Insert Class-code
	241	*/
	242	#ifdef CFG_PCI_CLASSCODE
	243	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
	244	#endif /* CFG_PCI_CLASSCODE */
	245
	246	/*--------------------------------------------------------------------------+
	247	* If PCI speed = 66Mhz, set 66Mhz capable bit.
	248	--------------------------------------------------------------------------/
	249	if (bd->bi_pci_busfreq >= 66000000) {
	250	pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
	251	pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short\|PCI_STATUS_66MHZ));
	252	}
	253
	254	#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
	255	#if (CONFIG_PCI_HOSE == PCI_HOST_AUTO)
	256	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
	257	#endif
	258	{
	259	/*--------------------------------------------------------------------------+
	260	* Write the 405GP PCI Configuration regs.
	261	* Enable 405GP to be a master on the PCI bus (PMM).
	262	* Enable 405GP to act as a PCI memory target (PTM).
263	--------------------------------------------------------------------------/
264	pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
265	pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short \|
266	PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY);
267	}
268	#endif
269
270	/*
271	* Set HCE bit (Host Configuration Enabled)
272	*/
273	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
274	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short \| 0x0001));
275
276	#ifdef CONFIG_PCI_PNP
277	/*--------------------------------------------------------------------------+
278	* Scan the PCI bus and configure devices found.
279	--------------------------------------------------------------------------/
280	#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
281	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
282	#endif
283	{
284	#ifdef CONFIG_PCI_SCAN_SHOW
285	printf("PCI: Bus Dev VenId DevId Class Int\n");
286	#endif
287
288	hose->last_busno = pci_hose_scan(hose);
289	}
290	#endif /* CONFIG_PCI_PNP */
291
292	}
293
294	/*
295	* drivers/pci.c skips every host bridge but the 405GP since it could
296	* be set as an Adapter.
297	*
298	* I (Andrew May) don't know what we should do here, but I don't want
299	* the auto setup of a PCI device disabling what is done pci_405gp_init
300	* as has happened before.
301	*/
302	void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
303	struct pci_config_table *entry)
304	{
305	#ifdef DEBUG
306	printf("405gp_setup_bridge\n");
307	#endif
308	}
309
310	/*
311	*
312	*/
313
314	void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
315	{
316	unsigned char int_line = 0xff;
317
318	/*
319	* Write pci interrupt line register (cpci405 specific)
320	*/
321	switch (PCI_DEV(dev) & 0x03)
322	{
323	case 0:
324	int_line = 27 + 2;
325	break;
326	case 1:
327	int_line = 27 + 3;
328	break;
329	case 2:
330	int_line = 27 + 0;
331	break;
332	case 3:
333	int_line = 27 + 1;
334	break;
335	}
336
337	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
338	}
339
340	void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
341	struct pci_config_table *entry)
342	{
343	unsigned int cmdstat = 0;
344
345	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
346
347	/* always enable io space on vga boards */
348	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
349	cmdstat \|= PCI_COMMAND_IO;
350	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
351	}
352
353	#if !(defined(CONFIG_PIP405) \|\| defined (CONFIG_MIP405))
354
355	/*
356	*As is these functs get called out of flash Not a horrible
357	*thing, but something to keep in mind. (no statics?)
358	*/
359	static struct pci_config_table pci_405gp_config_table[] = {
360	/if VendID is 0 it terminates the table search (ie Walnut)/
361	#if CFG_PCI_SUBSYS_VENDORID
362	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
363	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
364	#endif
365	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
366	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
367
368	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
369	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
370
371	{ }
372	};
373
374	static struct pci_controller hose = {
375	fixup_irq: pci_405gp_fixup_irq,
376	config_table: pci_405gp_config_table,
377	};
378
ad10dd9a	379	void pci_init_board(void)
c609719b WD	380	{
	381	/we want the ptrs to RAM not flash (ie don't use init list)/
	382	hose.fixup_irq = pci_405gp_fixup_irq;
	383	hose.config_table = pci_405gp_config_table;
	384	pci_405gp_init(&hose);
	385	}
	386
	387	#endif
	388
	389	#endif /* CONFIG_PCI */
	390
	391	#endif /* CONFIG_405GP */
	392
	393	/*-----------------------------------------------------------------------------+
	394	* CONFIG_440
	395	-----------------------------------------------------------------------------/
	396	#if defined(CONFIG_440) && defined(CONFIG_PCI)
	397
	398	static struct pci_controller ppc440_hose = {0};
	399
	400
	401	void pci_440_init (struct pci_controller *hose)
	402	{
	403	int reg_num = 0;
	404	unsigned long strap;
	405
	406	/*--------------------------------------------------------------------------+
	407	* The PCI initialization sequence enable bit must be set ... if not abort
	408	* pci setup since updating the bit requires chip reset.
	409	--------------------------------------------------------------------------/
	410	strap = mfdcr(cpc0_strp1);
	411	if( (strap & 0x00040000) == 0 ){
	412	printf("PCI: CPC0_STRP1[PISE] not set.\n");
	413	printf("PCI: Configuration aborted.\n");
	414	return;
	415	}
	416
	417	/*--------------------------------------------------------------------------+
	418	* PCI controller init
	419	--------------------------------------------------------------------------/
	420	hose->first_busno = 0;
	421	hose->last_busno = 0xff;
	422
	423	pci_set_region(hose->regions + reg_num++,
	424	0x00000000,
	425	PCIX0_IOBASE,
	426	0x10000,
	427	PCI_REGION_IO);
	428
	429	pci_set_region(hose->regions + reg_num++,
	430	CFG_PCI_TARGBASE,
	431	CFG_PCI_MEMBASE,
	432	0x10000000,
	433	PCI_REGION_MEM );
	434	hose->region_count = reg_num;
	435
	436	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
	437
	438	#if defined(CFG_PCI_PRE_INIT)
	439	/* Let board change/modify hose & do initial checks */
	440	if( pci_pre_init (hose) == 0 ){
	441	printf("PCI: Board-specific initialization failed.\n");
	442	printf("PCI: Configuration aborted.\n");
	443	return;
444	}
445	#endif
446
447	pci_register_hose( hose );
448
449	/*--------------------------------------------------------------------------+
450	* PCI target init
451	--------------------------------------------------------------------------/
452	#if defined(CFG_PCI_TARGET_INIT)
453	pci_target_init(hose); /* Let board setup pci target */
454	#else
455	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
456	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
457	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
458	#endif
459
460	out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
461	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) \| 1 ); /* Enable host config */
462
463	/*--------------------------------------------------------------------------+
464	* PCI master init: default is one 256MB region for PCI memory:
465	* 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
466	--------------------------------------------------------------------------/
467	#if defined(CFG_PCI_MASTER_INIT)
468	pci_master_init(hose); /* Let board setup pci master */
469	#else
470	out32r( PCIX0_POM0SA, 0 ); /* disable */
471	out32r( PCIX0_POM1SA, 0 ); /* disable */
472	out32r( PCIX0_POM2SA, 0 ); /* disable */
473	out32r( PCIX0_POM0LAL, 0x00000000 );
474	out32r( PCIX0_POM0LAH, 0x00000003 );
475	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
476	out32r( PCIX0_POM0PCIAH, 0x00000000 );
477	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
478	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
479	#endif
480
481	/*--------------------------------------------------------------------------+
482	* PCI host configuration -- we don't make any assumptions here ... the
483	* _board_must_indicate_ what to do -- there's just too many runtime
484	* scenarios in environments like cPCI, PPMC, etc. to make a determination
485	* based on hard-coded values or state of arbiter enable.
486	--------------------------------------------------------------------------/
487	if( is_pci_host(hose) ){
488	#ifdef CONFIG_PCI_SCAN_SHOW
489	printf("PCI: Bus Dev VenId DevId Class Int\n");
490	#endif
491	out16r( PCIX0_CMD, in16r( PCIX0_CMD ) \| PCI_COMMAND_MASTER);
492	hose->last_busno = pci_hose_scan(hose);
493	}
494	}
495
496
ad10dd9a	497	void pci_init_board(void)
c609719b WD	498	{
	499	pci_440_init (&ppc440_hose);
	500	}
	501
	502	#endif /* CONFIG_440 & CONFIG_PCI */