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Fix problems with CMC_PU2 flash driver.
[people/ms/u-boot.git] / cpu / ppc4xx / 440gx_enet.c
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ba56f625
WD		 1/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 *-----------------------------------------------------------------------------*/
76
77#include <config.h>
78#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
79
80#include <common.h>
81#include <net.h>
82#include <asm/processor.h>
83#include <ppc440.h>
84#include <commproc.h>
85#include <440gx_enet.h>
86#include <405_mal.h>
87#include <miiphy.h>
88#include <malloc.h>
89#include "vecnum.h"
90
91
92#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
93#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
94
95
96/* Ethernet Transmit and Receive Buffers */
97/* AS.HARNOIS
98 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
99 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
100 */
101#define ENET_MAX_MTU PKTSIZE
102#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
103
104
105/* define the number of channels implemented */
106#define EMAC_RXCHL EMAC_NUM_DEV
107#define EMAC_TXCHL EMAC_NUM_DEV
108
109/*-----------------------------------------------------------------------------+
110 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
111 * Interrupt Controller).
112 *-----------------------------------------------------------------------------*/
113#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
114#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
115#define EMAC_UIC_DEF UIC_ENET
116
117#undef INFO_440_ENET
118
3c74e32a
WD		 119#define BI_PHYMODE_NONE 0
120#define BI_PHYMODE_ZMII 1
121#define BI_PHYMODE_RGMII 2
122
ba56f625
WD		 123/*-----------------------------------------------------------------------------+
124 * Global variables. TX and RX descriptors and buffers.
125 *-----------------------------------------------------------------------------*/
126/* IER globals */
127static uint32_t mal_ier;
128
129/*-----------------------------------------------------------------------------+
130 * Prototypes and externals.
131 *-----------------------------------------------------------------------------*/
132static void enet_rcv (struct eth_device *dev, unsigned long malisr);
133
134int enetInt (struct eth_device *dev);
135static void mal_err (struct eth_device *dev, unsigned long isr,
136 unsigned long uic, unsigned long maldef,
137 unsigned long mal_errr);
138static void emac_err (struct eth_device *dev, unsigned long isr);
139
140/*-----------------------------------------------------------------------------+
141| ppc_440x_eth_halt
142| Disable MAL channel, and EMACn
143|
144|
145+-----------------------------------------------------------------------------*/
146static void ppc_440x_eth_halt (struct eth_device *dev)
147{
148 EMAC_440GX_HW_PST hw_p = dev->priv;
149 uint32_t failsafe = 10000;
150
151 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
152
153 /* 1st reset MAL channel */
154 /* Note: writing a 0 to a channel has no effect */
155 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
156 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
157
158 /* wait for reset */
159 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
160 udelay (1000); /* Delay 1 MS so as not to hammer the register */
161 failsafe--;
162 if (failsafe == 0)
163 break;
164
165 }
166
167 /* EMAC RESET */
168 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
169
ba56f625
WD		 170 return;
171}
172
173extern int phy_setup_aneg (unsigned char addr);
174extern int miiphy_reset (unsigned char addr);
175
855a496f
WD		 176#if defined (CONFIG_440_GX)
177int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
178{
179 unsigned long pfc1;
180 unsigned long zmiifer;
181 unsigned long rmiifer;
182
183 mfsdr(sdr_pfc1, pfc1);
184 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
185
186 zmiifer = 0;
187 rmiifer = 0;
188
189 switch (pfc1) {
190 case 1:
191 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
192 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
193 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
194 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
195 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
196 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
197 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
198 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
199 break;
200 case 2:
201 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
202 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
203 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
204 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
205 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
206 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
207 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
208 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
209 break;
210 case 3:
211 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
212 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
213 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
214 bis->bi_phymode[1] = BI_PHYMODE_NONE;
215 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
216 bis->bi_phymode[3] = BI_PHYMODE_NONE;
217 break;
218 case 4:
219 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
220 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
221 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
222 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
223 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
224 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
225 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
226 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
227 break;
228 case 5:
229 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
230 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
231 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
232 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
233 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
234 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
235 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
236 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
237 break;
238 case 6:
239 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
240 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
241 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
855a496f
WD		 242 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
243 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
244 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
855a496f
WD		 245 break;
246 case 0:
247 default:
248 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
249 rmiifer = 0x0;
250 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
251 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
252 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
253 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
254 break;
255 }
256
257 /* Ensure we setup mdio for this devnum and ONLY this devnum */
258 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
259
260 out32 (ZMII_FER, zmiifer);
261 out32 (RGMII_FER, rmiifer);
262
263 return ((int)pfc1);
264
265}
266#endif
267
ba56f625
WD		 268static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
269{
270 int i;
271 unsigned long reg;
272 unsigned long msr;
273 unsigned long speed;
274 unsigned long duplex;
275 unsigned long failsafe;
276 unsigned mode_reg;
277 unsigned short devnum;
278 unsigned short reg_short;
279 sys_info_t sysinfo;
855a496f 280 int ethgroup;
ba56f625
WD		 281
282 EMAC_440GX_HW_PST hw_p = dev->priv;
283
284 /* before doing anything, figure out if we have a MAC address */
285 /* if not, bail */
286 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
287 return -1;
288
289 /* Need to get the OPB frequency so we can access the PHY */
290 get_sys_info (&sysinfo);
291
292
293 msr = mfmsr ();
294 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
295
296 devnum = hw_p->devnum;
297
298#ifdef INFO_440_ENET
299 /* AS.HARNOIS
300 * We should have :
301 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
302 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
303 * is possible that new packets (without relationship with
304 * current transfer) have got the time to arrived before
305 * netloop calls eth_halt
306 */
307 printf ("About preceeding transfer (eth%d):\n"
308 "- Sent packet number %d\n"
309 "- Received packet number %d\n"
310 "- Handled packet number %d\n",
311 hw_p->devnum,
312 hw_p->stats.pkts_tx,
313 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
314
315 hw_p->stats.pkts_tx = 0;
316 hw_p->stats.pkts_rx = 0;
317 hw_p->stats.pkts_handled = 0;
318#endif
319
320 /* MAL Channel RESET */
321 /* 1st reset MAL channel */
322 /* Note: writing a 0 to a channel has no effect */
323 mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
324 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
325
326 /* wait for reset */
327 /* TBS: should have udelay and failsafe here */
328 failsafe = 10000;
329 /* wait for reset */
330 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
331 udelay (1000); /* Delay 1 MS so as not to hammer the register */
332 failsafe--;
333 if (failsafe == 0)
334 break;
335
336 }
337
338 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
339 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
340
341 hw_p->rx_slot = 0; /* MAL Receive Slot */
342 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
343 hw_p->rx_u_index = 0; /* Receive User Queue Index */
344
345 hw_p->tx_slot = 0; /* MAL Transmit Slot */
346 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
347 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
348
349 /* set RMII mode */
350 /* NOTE: 440GX spec states that mode is mutually exclusive */
351 /* NOTE: Therefore, disable all other EMACS, since we handle */
352 /* NOTE: only one emac at a time */
353 reg = 0;
354 out32 (ZMII_FER, 0);
355 udelay (100);
ba56f625 356
0e6d798c 357#if defined(CONFIG_440_GX)
855a496f 358 ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
0e6d798c
WD		 359#else
360 if ((devnum == 0) || (devnum == 1)) {
361 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
362 }
363 else { /* ((devnum == 2) || (devnum == 3)) */
364 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
ba56f625
WD		 365 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
366 (RGMII_FER_RGMII << RGMII_FER_V (3))));
0e6d798c 367 }
855a496f 368
0e6d798c
WD		 369#endif
370 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
371 __asm__ volatile ("eieio");
372
373 /* reset emac so we have access to the phy */
374
375 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
ba56f625
WD		 376 __asm__ volatile ("eieio");
377
378 failsafe = 1000;
379 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
380 udelay (1000);
381 failsafe--;
382 }
383
384 /* Whack the M1 register */
385 mode_reg = 0x0;
386 mode_reg &= ~0x00000038;
387 if (sysinfo.freqOPB <= 50000000);
388 else if (sysinfo.freqOPB <= 66666667)
389 mode_reg |= EMAC_M1_OBCI_66;
390 else if (sysinfo.freqOPB <= 83333333)
391 mode_reg |= EMAC_M1_OBCI_83;
392 else if (sysinfo.freqOPB <= 100000000)
393 mode_reg |= EMAC_M1_OBCI_100;
394 else
395 mode_reg |= EMAC_M1_OBCI_GT100;
396
397 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
398
399
400 /* wait for PHY to complete auto negotiation */
401 reg_short = 0;
402#ifndef CONFIG_CS8952_PHY
403 switch (devnum) {
404 case 0:
405 reg = CONFIG_PHY_ADDR;
406 break;
407 case 1:
408 reg = CONFIG_PHY1_ADDR;
409 break;
410#if defined (CONFIG_440_GX)
411 case 2:
412 reg = CONFIG_PHY2_ADDR;
413 break;
414 case 3:
415 reg = CONFIG_PHY3_ADDR;
416 break;
417#endif
418 default:
419 reg = CONFIG_PHY_ADDR;
420 break;
421 }
422
3c74e32a
WD		 423 bis->bi_phynum[devnum] = reg;
424
a06752e3
WD		 425 /*
426 * Reset the phy, only if its the first time through
427 * otherwise, just check the speeds & feeds
428 */
429 if (hw_p->first_init == 0) {
430 miiphy_reset (reg);
ba56f625 431
855a496f 432#if defined(CONFIG_440_GX)
0e6d798c
WD		 433#if defined(CONFIG_CIS8201_PHY)
434 /*
435 * Cicada 8201 PHY needs to have an extended register whacked
436 * for RGMII mode.
437 */
855a496f 438 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
0e6d798c 439 miiphy_write (reg, 23, 0x1200);
fc1cfcdb
WD		 440 /*
441 * Vitesse VSC8201/Cicada CIS8201 errata:
442 * Interoperability problem with Intel 82547EI phys
443 * This work around (provided by Vitesse) changes
444 * the default timer convergence from 8ms to 12ms
445 */
446 miiphy_write (reg, 0x1f, 0x2a30);
447 miiphy_write (reg, 0x08, 0x0200);
448 miiphy_write (reg, 0x1f, 0x52b5);
449 miiphy_write (reg, 0x02, 0x0004);
450 miiphy_write (reg, 0x01, 0x0671);
451 miiphy_write (reg, 0x00, 0x8fae);
452 miiphy_write (reg, 0x1f, 0x2a30);
453 miiphy_write (reg, 0x08, 0x0000);
454 miiphy_write (reg, 0x1f, 0x0000);
455 /* end Vitesse/Cicada errata */
0e6d798c
WD		 456 }
457#endif
855a496f 458#endif
a06752e3
WD		 459 /* Start/Restart autonegotiation */
460 phy_setup_aneg (reg);
461 udelay (1000);
462 }
ba56f625
WD		 463
464 miiphy_read (reg, PHY_BMSR, &reg_short);
465
466 /*
0e6d798c 467 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
ba56f625
WD		 468 */
469 if ((reg_short & PHY_BMSR_AUTN_ABLE)
470 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
471 puts ("Waiting for PHY auto negotiation to complete");
472 i = 0;
473 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
474 /*
475 * Timeout reached ?
476 */
477 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
478 puts (" TIMEOUT !\n");
479 break;
480 }
481
482 if ((i++ % 1000) == 0) {
483 putc ('.');
484 }
485 udelay (1000); /* 1 ms */
486 miiphy_read (reg, PHY_BMSR, &reg_short);
487
488 }
489 puts (" done\n");
490 udelay (500000); /* another 500 ms (results in faster booting) */
491 }
492#endif
493 speed = miiphy_speed (reg);
494 duplex = miiphy_duplex (reg);
495
496 if (hw_p->print_speed) {
497 hw_p->print_speed = 0;
498 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
499 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
500 }
501
502 /* Set ZMII/RGMII speed according to the phy link speed */
503 reg = in32 (ZMII_SSR);
855a496f 504 if ( (speed == 100) || (speed == 1000) )
ba56f625
WD		 505 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
506 else
507 out32 (ZMII_SSR,
508 reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
509
510 if ((devnum == 2) || (devnum == 3)) {
511 if (speed == 1000)
512 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
513 else if (speed == 100)
514 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
515 else
516 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
517
518 out32 (RGMII_SSR, reg);
519 }
520
521 /* set the Mal configuration reg */
522 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
523 if (get_pvr () == PVR_440GP_RB)
524 mtdcr (malmcr,
525 MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
526 else
527 mtdcr (malmcr,
528 MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
529 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
530
531 /* Free "old" buffers */
532 if (hw_p->alloc_tx_buf)
533 free (hw_p->alloc_tx_buf);
534 if (hw_p->alloc_rx_buf)
535 free (hw_p->alloc_rx_buf);
536
537 /*
538 * Malloc MAL buffer desciptors, make sure they are
539 * aligned on cache line boundary size
540 * (401/403/IOP480 = 16, 405 = 32)
541 * and doesn't cross cache block boundaries.
542 */
543 hw_p->alloc_tx_buf =
544 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
545 ((2 * CFG_CACHELINE_SIZE) - 2));
546 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
547 hw_p->tx =
548 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
549 CFG_CACHELINE_SIZE -
550 ((int) hw_p->
551 alloc_tx_buf & CACHELINE_MASK));
552 } else {
553 hw_p->tx = hw_p->alloc_tx_buf;
554 }
555
556 hw_p->alloc_rx_buf =
557 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
558 ((2 * CFG_CACHELINE_SIZE) - 2));
559 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
560 hw_p->rx =
561 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
562 CFG_CACHELINE_SIZE -
563 ((int) hw_p->
564 alloc_rx_buf & CACHELINE_MASK));
565 } else {
566 hw_p->rx = hw_p->alloc_rx_buf;
567 }
568
569 for (i = 0; i < NUM_TX_BUFF; i++) {
570 hw_p->tx[i].ctrl = 0;
571 hw_p->tx[i].data_len = 0;
572 if (hw_p->first_init == 0)
573 hw_p->txbuf_ptr =
574 (char *) malloc (ENET_MAX_MTU_ALIGNED);
575 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
576 if ((NUM_TX_BUFF - 1) == i)
577 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
578 hw_p->tx_run[i] = -1;
579#if 0
580 printf ("TX_BUFF %d @ 0x%08lx\n", i,
581 (ulong) hw_p->tx[i].data_ptr);
582#endif
583 }
584
585 for (i = 0; i < NUM_RX_BUFF; i++) {
586 hw_p->rx[i].ctrl = 0;
587 hw_p->rx[i].data_len = 0;
588 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
589 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
590 if ((NUM_RX_BUFF - 1) == i)
591 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
592 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
593 hw_p->rx_ready[i] = -1;
594#if 0
595 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
596#endif
597 }
598
599 reg = 0x00000000;
600
601 reg |= dev->enetaddr[0]; /* set high address */
602 reg = reg << 8;
603 reg |= dev->enetaddr[1];
604
605 out32 (EMAC_IAH + hw_p->hw_addr, reg);
606
607 reg = 0x00000000;
608 reg |= dev->enetaddr[2]; /* set low address */
609 reg = reg << 8;
610 reg |= dev->enetaddr[3];
611 reg = reg << 8;
612 reg |= dev->enetaddr[4];
613 reg = reg << 8;
614 reg |= dev->enetaddr[5];
615
616 out32 (EMAC_IAL + hw_p->hw_addr, reg);
617
618 switch (devnum) {
619 case 1:
620 /* setup MAL tx & rx channel pointers */
621 mtdcr (maltxbattr, 0x0);
622 mtdcr (maltxctp1r, hw_p->tx);
623 mtdcr (malrxbattr, 0x0);
624 mtdcr (malrxctp1r, hw_p->rx);
625 /* set RX buffer size */
626 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
627 break;
628#if defined (CONFIG_440_GX)
629 case 2:
630 /* setup MAL tx & rx channel pointers */
631 mtdcr (maltxbattr, 0x0);
632 mtdcr (maltxctp2r, hw_p->tx);
633 mtdcr (malrxbattr, 0x0);
634 mtdcr (malrxctp2r, hw_p->rx);
635 /* set RX buffer size */
636 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
637 break;
638 case 3:
639 /* setup MAL tx & rx channel pointers */
640 mtdcr (maltxbattr, 0x0);
641 mtdcr (maltxctp3r, hw_p->tx);
642 mtdcr (malrxbattr, 0x0);
643 mtdcr (malrxctp3r, hw_p->rx);
644 /* set RX buffer size */
645 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
646 break;
647#endif /*CONFIG_440_GX */
648 case 0:
649 default:
650 /* setup MAL tx & rx channel pointers */
651 mtdcr (maltxbattr, 0x0);
652 mtdcr (maltxctp0r, hw_p->tx);
653 mtdcr (malrxbattr, 0x0);
654 mtdcr (malrxctp0r, hw_p->rx);
655 /* set RX buffer size */
656 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
657 break;
658 }
659
660 /* Enable MAL transmit and receive channels */
661 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
662 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
663
664 /* set transmit enable & receive enable */
665 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
666
667 /* set receive fifo to 4k and tx fifo to 2k */
668 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
669 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
670
671 /* set speed */
855a496f
WD		 672 if (speed == _1000BASET)
673 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
674 else if (speed == _100BASET)
ba56f625
WD		 675 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
676 else
677 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
678 if (duplex == FULL)
679 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
680
681 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
682
683 /* Enable broadcast and indvidual address */
684 /* TBS: enabling runts as some misbehaved nics will send runts */
685 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
686
687 /* we probably need to set the tx mode1 reg? maybe at tx time */
688
689 /* set transmit request threshold register */
690 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
691
692 /* set receive low/high water mark register */
693 /* 440GP has a 64 byte burst length */
694 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
695 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
696
697 /* Set fifo limit entry in tx mode 0 */
698 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
699 /* Frame gap set */
700 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
701
702 /* Set EMAC IER */
703 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
704 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
705 if (speed == _100BASET)
706 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
707
708 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
709 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
710
711 if (hw_p->first_init == 0) {
712 /*
713 * Connect interrupt service routines
714 */
715 irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
716 (interrupt_handler_t *) enetInt, dev);
717 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
718 (interrupt_handler_t *) enetInt, dev);
719 }
ba56f625
WD		 720
721 mtmsr (msr); /* enable interrupts again */
722
723 hw_p->bis = bis;
724 hw_p->first_init = 1;
725
726 return (1);
727}
728
729
730static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
731 int len)
732{
733 struct enet_frame *ef_ptr;
734 ulong time_start, time_now;
735 unsigned long temp_txm0;
736 EMAC_440GX_HW_PST hw_p = dev->priv;
737
738 ef_ptr = (struct enet_frame *) ptr;
739
740 /*-----------------------------------------------------------------------+
741 * Copy in our address into the frame.
742 *-----------------------------------------------------------------------*/
743 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
744
745 /*-----------------------------------------------------------------------+
746 * If frame is too long or too short, modify length.
747 *-----------------------------------------------------------------------*/
748 /* TBS: where does the fragment go???? */
749 if (len > ENET_MAX_MTU)
750 len = ENET_MAX_MTU;
751
752 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
753 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
754
755 /*-----------------------------------------------------------------------+
756 * set TX Buffer busy, and send it
757 *-----------------------------------------------------------------------*/
758 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
759 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
760 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
761 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
762 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
763
764 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
765 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
766
767 __asm__ volatile ("eieio");
768
769 out32 (EMAC_TXM0 + hw_p->hw_addr,
770 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
771#ifdef INFO_440_ENET
772 hw_p->stats.pkts_tx++;
773#endif
774
775 /*-----------------------------------------------------------------------+
776 * poll unitl the packet is sent and then make sure it is OK
777 *-----------------------------------------------------------------------*/
778 time_start = get_timer (0);
779 while (1) {
780 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
781 /* loop until either TINT turns on or 3 seconds elapse */
782 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
783 /* transmit is done, so now check for errors
784 * If there is an error, an interrupt should
785 * happen when we return
786 */
787 time_now = get_timer (0);
788 if ((time_now - time_start) > 3000) {
789 return (-1);
790 }
791 } else {
792 return (len);
793 }
794 }
795}
796
797
798int enetInt (struct eth_device *dev)
799{
800 int serviced;
801 int rc = -1; /* default to not us */
802 unsigned long mal_isr;
803 unsigned long emac_isr = 0;
804 unsigned long mal_rx_eob;
805 unsigned long my_uic0msr, my_uic1msr;
806
807#if defined(CONFIG_440_GX)
808 unsigned long my_uic2msr;
809#endif
810 EMAC_440GX_HW_PST hw_p;
811
812 /*
813 * Because the mal is generic, we need to get the current
814 * eth device
815 */
816 dev = eth_get_dev ();
817
818 hw_p = dev->priv;
819
820
821 /* enter loop that stays in interrupt code until nothing to service */
822 do {
823 serviced = 0;
824
825 my_uic0msr = mfdcr (uic0msr);
826 my_uic1msr = mfdcr (uic1msr);
827#if defined(CONFIG_440_GX)
828 my_uic2msr = mfdcr (uic2msr);
829#endif
830 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
831 && !(my_uic1msr &
832 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
833 UIC_MRDE))) {
834 /* not for us */
835 return (rc);
836 }
837#if defined (CONFIG_440_GX)
838 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
839 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
840 /* not for us */
841 return (rc);
842 }
843#endif
844 /* get and clear controller status interrupts */
845 /* look at Mal and EMAC interrupts */
846 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
847 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
848 /* we have a MAL interrupt */
849 mal_isr = mfdcr (malesr);
850 /* look for mal error */
851 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
852 mal_err (dev, mal_isr, my_uic0msr,
853 MAL_UIC_DEF, MAL_UIC_ERR);
854 serviced = 1;
855 rc = 0;
856 }
857 }
858
859 /* port by port dispatch of emac interrupts */
860 if (hw_p->devnum == 0) {
861 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
862 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
863 if ((hw_p->emac_ier & emac_isr) != 0) {
864 emac_err (dev, emac_isr);
865 serviced = 1;
866 rc = 0;
867 }
868 }
869 if ((hw_p->emac_ier & emac_isr)
870 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
871 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
872 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
873 return (rc); /* we had errors so get out */
874 }
875 }
876
877 if (hw_p->devnum == 1) {
878 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
879 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
880 if ((hw_p->emac_ier & emac_isr) != 0) {
881 emac_err (dev, emac_isr);
882 serviced = 1;
883 rc = 0;
884 }
885 }
886 if ((hw_p->emac_ier & emac_isr)
887 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
888 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
889 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
890 return (rc); /* we had errors so get out */
891 }
892 }
893#if defined (CONFIG_440_GX)
894 if (hw_p->devnum == 2) {
895 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
896 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
897 if ((hw_p->emac_ier & emac_isr) != 0) {
898 emac_err (dev, emac_isr);
899 serviced = 1;
900 rc = 0;
901 }
902 }
903 if ((hw_p->emac_ier & emac_isr)
904 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
905 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
906 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
907 mtdcr (uic2sr, UIC_ETH2);
908 return (rc); /* we had errors so get out */
909 }
910 }
911
912 if (hw_p->devnum == 3) {
913 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
914 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
915 if ((hw_p->emac_ier & emac_isr) != 0) {
916 emac_err (dev, emac_isr);
917 serviced = 1;
918 rc = 0;
919 }
920 }
921 if ((hw_p->emac_ier & emac_isr)
922 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
923 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
924 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
925 mtdcr (uic2sr, UIC_ETH3);
926 return (rc); /* we had errors so get out */
927 }
928 }
929#endif /* CONFIG_440_GX */
930 /* handle MAX TX EOB interrupt from a tx */
931 if (my_uic0msr & UIC_MTE) {
932 mal_rx_eob = mfdcr (maltxeobisr);
933 mtdcr (maltxeobisr, mal_rx_eob);
934 mtdcr (uic0sr, UIC_MTE);
935 }
936 /* handle MAL RX EOB interupt from a receive */
fc1cfcdb 937 /* check for EOB on valid channels */
ba56f625
WD		 938 if (my_uic0msr & UIC_MRE) {
939 mal_rx_eob = mfdcr (malrxeobisr);
940 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
941 /* clear EOB
942 mtdcr(malrxeobisr, mal_rx_eob); */
943 enet_rcv (dev, emac_isr);
944 /* indicate that we serviced an interrupt */
945 serviced = 1;
946 rc = 0;
947 }
948 }
949 mtdcr (uic0sr, UIC_MRE); /* Clear */
950 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
951 switch (hw_p->devnum) {
952 case 0:
953 mtdcr (uic1sr, UIC_ETH0);
954 break;
955 case 1:
956 mtdcr (uic1sr, UIC_ETH1);
957 break;
958#if defined (CONFIG_440_GX)
959 case 2:
960 mtdcr (uic2sr, UIC_ETH2);
961 break;
962 case 3:
963 mtdcr (uic2sr, UIC_ETH3);
964 break;
965#endif /* CONFIG_440_GX */
966 default:
967 break;
968 }
969 } while (serviced);
970
971 return (rc);
972}
973
974/*-----------------------------------------------------------------------------+
975 * MAL Error Routine
976 *-----------------------------------------------------------------------------*/
977static void mal_err (struct eth_device *dev, unsigned long isr,
978 unsigned long uic, unsigned long maldef,
979 unsigned long mal_errr)
980{
981 EMAC_440GX_HW_PST hw_p = dev->priv;
982
983 mtdcr (malesr, isr); /* clear interrupt */
984
985 /* clear DE interrupt */
986 mtdcr (maltxdeir, 0xC0000000);
987 mtdcr (malrxdeir, 0x80000000);
988
989#ifdef INFO_440_ENET
990 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
991#endif
992
993 eth_init (hw_p->bis); /* start again... */
994}
995
996/*-----------------------------------------------------------------------------+
997 * EMAC Error Routine
998 *-----------------------------------------------------------------------------*/
999static void emac_err (struct eth_device *dev, unsigned long isr)
1000{
1001 EMAC_440GX_HW_PST hw_p = dev->priv;
1002
1003 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1004 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1005}
1006
1007/*-----------------------------------------------------------------------------+
1008 * enet_rcv() handles the ethernet receive data
1009 *-----------------------------------------------------------------------------*/
1010static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1011{
1012 struct enet_frame *ef_ptr;
1013 unsigned long data_len;
1014 unsigned long rx_eob_isr;
1015 EMAC_440GX_HW_PST hw_p = dev->priv;
1016
1017 int handled = 0;
1018 int i;
1019 int loop_count = 0;
1020
1021 rx_eob_isr = mfdcr (malrxeobisr);
1022 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1023 /* clear EOB */
1024 mtdcr (malrxeobisr, rx_eob_isr);
1025
1026 /* EMAC RX done */
1027 while (1) { /* do all */
1028 i = hw_p->rx_slot;
1029
1030 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1031 || (loop_count >= NUM_RX_BUFF))
1032 break;
1033 loop_count++;
1034 hw_p->rx_slot++;
1035 if (NUM_RX_BUFF == hw_p->rx_slot)
1036 hw_p->rx_slot = 0;
1037 handled++;
1038 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1039 if (data_len) {
1040 if (data_len > ENET_MAX_MTU) /* Check len */
1041 data_len = 0;
1042 else {
1043 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1044 data_len = 0;
1045 hw_p->stats.rx_err_log[hw_p->
1046 rx_err_index]
1047 = hw_p->rx[i].ctrl;
1048 hw_p->rx_err_index++;
1049 if (hw_p->rx_err_index ==
1050 MAX_ERR_LOG)
1051 hw_p->rx_err_index =
1052 0;
fc1cfcdb 1053 } /* emac_erros */
ba56f625 1054 } /* data_len < max mtu */
fc1cfcdb 1055 } /* if data_len */
ba56f625
WD		 1056 if (!data_len) { /* no data */
1057 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1058
1059 hw_p->stats.data_len_err++; /* Error at Rx */
1060 }
1061
1062 /* !data_len */
1063 /* AS.HARNOIS */
1064 /* Check if user has already eaten buffer */
1065 /* if not => ERROR */
1066 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1067 if (hw_p->is_receiving)
1068 printf ("ERROR : Receive buffers are full!\n");
1069 break;
1070 } else {
1071 hw_p->stats.rx_frames++;
1072 hw_p->stats.rx += data_len;
1073 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1074 data_ptr;
1075#ifdef INFO_440_ENET
1076 hw_p->stats.pkts_rx++;
1077#endif
1078 /* AS.HARNOIS
1079 * use ring buffer
1080 */
1081 hw_p->rx_ready[hw_p->rx_i_index] = i;
1082 hw_p->rx_i_index++;
1083 if (NUM_RX_BUFF == hw_p->rx_i_index)
1084 hw_p->rx_i_index = 0;
1085
1086 /* printf("X"); /|* test-only *|/ */
1087
1088 /* AS.HARNOIS
1089 * free receive buffer only when
1090 * buffer has been handled (eth_rx)
1091 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1092 */
1093 } /* if data_len */
1094 } /* while */
1095 } /* if EMACK_RXCHL */
1096}
1097
1098
1099static int ppc_440x_eth_rx (struct eth_device *dev)
1100{
1101 int length;
1102 int user_index;
1103 unsigned long msr;
1104 EMAC_440GX_HW_PST hw_p = dev->priv;
1105
1106 hw_p->is_receiving = 1; /* tell driver */
1107
1108 for (;;) {
1109 /* AS.HARNOIS
1110 * use ring buffer and
1111 * get index from rx buffer desciptor queue
1112 */
1113 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1114 if (user_index == -1) {
1115 length = -1;
1116 break; /* nothing received - leave for() loop */
1117 }
1118
1119 msr = mfmsr ();
1120 mtmsr (msr & ~(MSR_EE));
1121
1122 length = hw_p->rx[user_index].data_len;
1123
1124 /* Pass the packet up to the protocol layers. */
1125 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1126 /* NetReceive(NetRxPackets[i], length); */
1127 NetReceive (NetRxPackets[user_index], length - 4);
1128 /* Free Recv Buffer */
1129 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1130 /* Free rx buffer descriptor queue */
1131 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1132 hw_p->rx_u_index++;
1133 if (NUM_RX_BUFF == hw_p->rx_u_index)
1134 hw_p->rx_u_index = 0;
1135
1136#ifdef INFO_440_ENET
1137 hw_p->stats.pkts_handled++;
1138#endif
1139
1140 mtmsr (msr); /* Enable IRQ's */
1141 }
1142
1143 hw_p->is_receiving = 0; /* tell driver */
1144
1145 return length;
1146}
1147
1148int ppc_440x_eth_initialize (bd_t * bis)
1149{
1150 static int virgin = 0;
1151 unsigned long pfc1;
1152 struct eth_device *dev;
1153 int eth_num = 0;
1154
1155 EMAC_440GX_HW_PST hw = NULL;
1156
1157 mfsdr (sdr_pfc1, pfc1);
1158 pfc1 &= ~(0x01e00000);
1159 pfc1 |= 0x01200000;
1160 mtsdr (sdr_pfc1, pfc1);
3c74e32a
WD		 1161 /* set phy num and mode */
1162 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1163 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1164 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1165 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1166 bis->bi_phymode[0] = 0;
1167 bis->bi_phymode[1] = 0;
1168 bis->bi_phymode[2] = 2;
1169 bis->bi_phymode[3] = 2;
ba56f625 1170
a06752e3
WD		 1171#if defined (CONFIG_440_GX)
1172 ppc_440x_eth_setup_bridge(0, bis);
1173#endif
1174
ba56f625
WD		 1175 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1176
1177 /* See if we can actually bring up the interface, otherwise, skip it */
1178 switch (eth_num) {
1179 case 0:
3c74e32a
WD		 1180 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1181 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
ba56f625 1182 continue;
3c74e32a 1183 }
ba56f625
WD		 1184 break;
1185 case 1:
3c74e32a
WD		 1186 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1187 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
ba56f625 1188 continue;
3c74e32a 1189 }
ba56f625
WD		 1190 break;
1191 case 2:
3c74e32a
WD		 1192 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1193 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
ba56f625 1194 continue;
3c74e32a 1195 }
ba56f625
WD		 1196 break;
1197 case 3:
3c74e32a
WD		 1198 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1199 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
ba56f625 1200 continue;
3c74e32a 1201 }
ba56f625
WD		 1202 break;
1203 default:
3c74e32a
WD		 1204 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1205 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
ba56f625 1206 continue;
3c74e32a 1207 }
ba56f625
WD		 1208 break;
1209 }
1210
1211 /* Allocate device structure */
1212 dev = (struct eth_device *) malloc (sizeof (*dev));
1213 if (dev == NULL) {
3f85ce27
WD		 1214 printf ("ppc_440x_eth_initialize: "
1215 "Cannot allocate eth_device %d\n", eth_num);
ba56f625
WD		 1216 return (-1);
1217 }
1218
1219 /* Allocate our private use data */
1220 hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
1221 if (hw == NULL) {
3f85ce27
WD		 1222 printf ("ppc_440x_eth_initialize: "
1223 "Cannot allocate private hw data for eth_device %d",
ba56f625
WD		 1224 eth_num);
1225 free (dev);
1226 return (-1);
1227 }
1228
1229 switch (eth_num) {
1230 case 0:
1231 hw->hw_addr = 0;
1232 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1233 break;
1234 case 1:
1235 hw->hw_addr = 0x100;
1236 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1237 break;
1238 case 2:
1239 hw->hw_addr = 0x400;
1240 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1241 break;
1242 case 3:
1243 hw->hw_addr = 0x600;
1244 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1245 break;
1246 default:
1247 hw->hw_addr = 0;
1248 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1249 break;
1250 }
1251
1252 hw->devnum = eth_num;
1253
1254 sprintf (dev->name, "ppc_440x_eth%d", eth_num);
1255 dev->priv = (void *) hw;
1256 dev->init = ppc_440x_eth_init;
1257 dev->halt = ppc_440x_eth_halt;
1258 dev->send = ppc_440x_eth_send;
1259 dev->recv = ppc_440x_eth_rx;
1260
1261 if (0 == virgin) {
1262 /* set the MAL IER ??? names may change with new spec ??? */
1263 mal_ier =
1264 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1265 MAL_IER_OPBE | MAL_IER_PLBE;
1266 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1267 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1268 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1269 mtdcr (malier, mal_ier);
1270
1271 /* install MAL interrupt handler */
1272 irq_install_handler (VECNUM_MS,
1273 (interrupt_handler_t *) enetInt,
1274 dev);
1275 irq_install_handler (VECNUM_MTE,
1276 (interrupt_handler_t *) enetInt,
1277 dev);
1278 irq_install_handler (VECNUM_MRE,
1279 (interrupt_handler_t *) enetInt,
1280 dev);
1281 irq_install_handler (VECNUM_TXDE,
1282 (interrupt_handler_t *) enetInt,
1283 dev);
1284 irq_install_handler (VECNUM_RXDE,
1285 (interrupt_handler_t *) enetInt,
1286 dev);
1287 virgin = 1;
1288 }
1289
1290 eth_register (dev);
1291
1292 } /* end for each supported device */
1293 return (1);
1294}
1295#endif /* CONFIG_440 && CONFIG_NET_MULTI */
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