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Commit | Line | Data |
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fe8c2806 | 1 | /* |
36d830c9 SR |
2 | * cpu/ppc4xx/44x_spd_ddr.c |
3 | * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a | |
4 | * DDR controller. Those are 440GP/GX/EP/GR. | |
5 | * | |
fe8c2806 WD |
6 | * (C) Copyright 2001 |
7 | * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com | |
8 | * | |
9 | * Based on code by: | |
10 | * | |
db2f721f WD |
11 | * Kenneth Johansson ,Ericsson AB. |
12 | * kenneth.johansson@etx.ericsson.se | |
fe8c2806 WD |
13 | * |
14 | * hacked up by bill hunter. fixed so we could run before | |
15 | * serial_init and console_init. previous version avoided this by | |
16 | * running out of cache memory during serial/console init, then running | |
17 | * this code later. | |
18 | * | |
19 | * (C) Copyright 2002 | |
20 | * Jun Gu, Artesyn Technology, jung@artesyncp.com | |
0c8721a4 | 21 | * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. |
fe8c2806 | 22 | * |
d2d43276 | 23 | * (C) Copyright 2005-2007 |
c157d8e2 SR |
24 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
25 | * | |
fe8c2806 WD |
26 | * See file CREDITS for list of people who contributed to this |
27 | * project. | |
28 | * | |
29 | * This program is free software; you can redistribute it and/or | |
30 | * modify it under the terms of the GNU General Public License as | |
31 | * published by the Free Software Foundation; either version 2 of | |
32 | * the License, or (at your option) any later version. | |
33 | * | |
34 | * This program is distributed in the hope that it will be useful, | |
35 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
36 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
37 | * GNU General Public License for more details. | |
38 | * | |
39 | * You should have received a copy of the GNU General Public License | |
40 | * along with this program; if not, write to the Free Software | |
41 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
42 | * MA 02111-1307 USA | |
43 | */ | |
44 | ||
d2d43276 SR |
45 | /* define DEBUG for debugging output (obviously ;-)) */ |
46 | #if 0 | |
47 | #define DEBUG | |
48 | #endif | |
49 | ||
fe8c2806 WD |
50 | #include <common.h> |
51 | #include <asm/processor.h> | |
52 | #include <i2c.h> | |
53 | #include <ppc4xx.h> | |
e2ebe696 | 54 | #include <asm/mmu.h> |
fe8c2806 | 55 | |
36d830c9 SR |
56 | #if defined(CONFIG_SPD_EEPROM) && \ |
57 | (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ | |
58 | defined(CONFIG_440EP) || defined(CONFIG_440GR)) | |
fe8c2806 WD |
59 | |
60 | /* | |
61 | * Set default values | |
62 | */ | |
f013dacf WD |
63 | #ifndef CFG_I2C_SPEED |
64 | #define CFG_I2C_SPEED 50000 | |
fe8c2806 WD |
65 | #endif |
66 | ||
f013dacf WD |
67 | #ifndef CFG_I2C_SLAVE |
68 | #define CFG_I2C_SLAVE 0xFE | |
fe8c2806 WD |
69 | #endif |
70 | ||
f013dacf | 71 | #define ONE_BILLION 1000000000 |
c157d8e2 | 72 | |
fe8c2806 | 73 | /*----------------------------------------------------------------------------- |
c157d8e2 SR |
74 | | Memory Controller Options 0 |
75 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
76 | #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ |
77 | #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ | |
78 | #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ | |
79 | #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ | |
80 | #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ | |
81 | #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ | |
82 | #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ | |
83 | #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ | |
84 | #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ | |
85 | #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ | |
86 | #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ | |
87 | #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ | |
fe8c2806 WD |
88 | |
89 | /*----------------------------------------------------------------------------- | |
c157d8e2 SR |
90 | | Memory Controller Options 1 |
91 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
92 | #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ |
93 | #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ | |
fe8c2806 WD |
94 | |
95 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
96 | | SDRAM DEVPOT Options |
97 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
98 | #define SDRAM_DEVOPT_DLL 0x80000000 |
99 | #define SDRAM_DEVOPT_DS 0x40000000 | |
fe8c2806 WD |
100 | |
101 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
102 | | SDRAM MCSTS Options |
103 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
104 | #define SDRAM_MCSTS_MRSC 0x80000000 |
105 | #define SDRAM_MCSTS_SRMS 0x40000000 | |
106 | #define SDRAM_MCSTS_CIS 0x20000000 | |
fe8c2806 WD |
107 | |
108 | /*----------------------------------------------------------------------------- | |
c157d8e2 SR |
109 | | SDRAM Refresh Timer Register |
110 | +-----------------------------------------------------------------------------*/ | |
f013dacf | 111 | #define SDRAM_RTR_RINT_MASK 0xFFFF0000 |
fe8c2806 | 112 | #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) |
f013dacf | 113 | #define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) |
fe8c2806 WD |
114 | |
115 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
116 | | SDRAM UABus Base Address Reg |
117 | +-----------------------------------------------------------------------------*/ | |
f013dacf | 118 | #define SDRAM_UABBA_UBBA_MASK 0x0000000F |
fe8c2806 WD |
119 | |
120 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
121 | | Memory Bank 0-7 configuration |
122 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
123 | #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ |
124 | #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ | |
125 | #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ | |
126 | #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ | |
127 | #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ | |
128 | #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ | |
129 | #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ | |
130 | #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ | |
131 | #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ | |
132 | #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ | |
133 | #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ | |
134 | #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ | |
135 | #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ | |
136 | #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ | |
137 | #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ | |
fe8c2806 WD |
138 | |
139 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
140 | | SDRAM TR0 Options |
141 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
142 | #define SDRAM_TR0_SDWR_MASK 0x80000000 |
143 | #define SDRAM_TR0_SDWR_2_CLK 0x00000000 | |
144 | #define SDRAM_TR0_SDWR_3_CLK 0x80000000 | |
145 | #define SDRAM_TR0_SDWD_MASK 0x40000000 | |
146 | #define SDRAM_TR0_SDWD_0_CLK 0x00000000 | |
147 | #define SDRAM_TR0_SDWD_1_CLK 0x40000000 | |
148 | #define SDRAM_TR0_SDCL_MASK 0x01800000 | |
149 | #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 | |
150 | #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 | |
151 | #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 | |
152 | #define SDRAM_TR0_SDPA_MASK 0x000C0000 | |
153 | #define SDRAM_TR0_SDPA_2_CLK 0x00040000 | |
154 | #define SDRAM_TR0_SDPA_3_CLK 0x00080000 | |
155 | #define SDRAM_TR0_SDPA_4_CLK 0x000C0000 | |
156 | #define SDRAM_TR0_SDCP_MASK 0x00030000 | |
157 | #define SDRAM_TR0_SDCP_2_CLK 0x00000000 | |
158 | #define SDRAM_TR0_SDCP_3_CLK 0x00010000 | |
159 | #define SDRAM_TR0_SDCP_4_CLK 0x00020000 | |
160 | #define SDRAM_TR0_SDCP_5_CLK 0x00030000 | |
161 | #define SDRAM_TR0_SDLD_MASK 0x0000C000 | |
162 | #define SDRAM_TR0_SDLD_1_CLK 0x00000000 | |
163 | #define SDRAM_TR0_SDLD_2_CLK 0x00004000 | |
164 | #define SDRAM_TR0_SDRA_MASK 0x0000001C | |
165 | #define SDRAM_TR0_SDRA_6_CLK 0x00000000 | |
166 | #define SDRAM_TR0_SDRA_7_CLK 0x00000004 | |
167 | #define SDRAM_TR0_SDRA_8_CLK 0x00000008 | |
168 | #define SDRAM_TR0_SDRA_9_CLK 0x0000000C | |
169 | #define SDRAM_TR0_SDRA_10_CLK 0x00000010 | |
170 | #define SDRAM_TR0_SDRA_11_CLK 0x00000014 | |
171 | #define SDRAM_TR0_SDRA_12_CLK 0x00000018 | |
172 | #define SDRAM_TR0_SDRA_13_CLK 0x0000001C | |
173 | #define SDRAM_TR0_SDRD_MASK 0x00000003 | |
174 | #define SDRAM_TR0_SDRD_2_CLK 0x00000001 | |
175 | #define SDRAM_TR0_SDRD_3_CLK 0x00000002 | |
176 | #define SDRAM_TR0_SDRD_4_CLK 0x00000003 | |
fe8c2806 WD |
177 | |
178 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
179 | | SDRAM TR1 Options |
180 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
181 | #define SDRAM_TR1_RDSS_MASK 0xC0000000 |
182 | #define SDRAM_TR1_RDSS_TR0 0x00000000 | |
183 | #define SDRAM_TR1_RDSS_TR1 0x40000000 | |
184 | #define SDRAM_TR1_RDSS_TR2 0x80000000 | |
185 | #define SDRAM_TR1_RDSS_TR3 0xC0000000 | |
186 | #define SDRAM_TR1_RDSL_MASK 0x00C00000 | |
187 | #define SDRAM_TR1_RDSL_STAGE1 0x00000000 | |
188 | #define SDRAM_TR1_RDSL_STAGE2 0x00400000 | |
189 | #define SDRAM_TR1_RDSL_STAGE3 0x00800000 | |
190 | #define SDRAM_TR1_RDCD_MASK 0x00000800 | |
191 | #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 | |
192 | #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 | |
193 | #define SDRAM_TR1_RDCT_MASK 0x000001FF | |
194 | #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) | |
195 | #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) | |
196 | #define SDRAM_TR1_RDCT_MIN 0x00000000 | |
197 | #define SDRAM_TR1_RDCT_MAX 0x000001FF | |
fe8c2806 WD |
198 | |
199 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
200 | | SDRAM WDDCTR Options |
201 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
202 | #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 |
203 | #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 | |
204 | #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 | |
205 | #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 | |
206 | #define SDRAM_WDDCTR_DCD_MASK 0x000001FF | |
fe8c2806 WD |
207 | |
208 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
209 | | SDRAM CLKTR Options |
210 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
211 | #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 |
212 | #define SDRAM_CLKTR_CLKP_0DEG 0x00000000 | |
213 | #define SDRAM_CLKTR_CLKP_90DEG 0x40000000 | |
214 | #define SDRAM_CLKTR_CLKP_180DEG 0x80000000 | |
215 | #define SDRAM_CLKTR_DCDT_MASK 0x000001FF | |
fe8c2806 WD |
216 | |
217 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
218 | | SDRAM DLYCAL Options |
219 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
220 | #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC |
221 | #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) | |
222 | #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) | |
fe8c2806 WD |
223 | |
224 | /*-----------------------------------------------------------------------------+ | |
c157d8e2 SR |
225 | | General Definition |
226 | +-----------------------------------------------------------------------------*/ | |
f013dacf WD |
227 | #define DEFAULT_SPD_ADDR1 0x53 |
228 | #define DEFAULT_SPD_ADDR2 0x52 | |
229 | #define MAXBANKS 4 /* at most 4 dimm banks */ | |
230 | #define MAX_SPD_BYTES 256 | |
231 | #define NUMHALFCYCLES 4 | |
232 | #define NUMMEMTESTS 8 | |
233 | #define NUMMEMWORDS 8 | |
234 | #define MAXBXCR 4 | |
235 | #define TRUE 1 | |
236 | #define FALSE 0 | |
fe8c2806 | 237 | |
e2ebe696 SR |
238 | /* |
239 | * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory | |
240 | * region. Right now the cache should still be disabled in U-Boot because of the | |
241 | * EMAC driver, that need it's buffer descriptor to be located in non cached | |
242 | * memory. | |
243 | * | |
244 | * If at some time this restriction doesn't apply anymore, just define | |
245 | * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup | |
246 | * everything correctly. | |
247 | */ | |
248 | #ifdef CFG_ENABLE_SDRAM_CACHE | |
249 | #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ | |
250 | #else | |
251 | #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ | |
252 | #endif | |
253 | ||
fd49bf02 SR |
254 | /* bank_parms is used to sort the bank sizes by descending order */ |
255 | struct bank_param { | |
256 | unsigned long cr; | |
257 | unsigned long bank_size_bytes; | |
258 | }; | |
259 | ||
260 | typedef struct bank_param BANKPARMS; | |
261 | ||
262 | #ifdef CFG_SIMULATE_SPD_EEPROM | |
263 | extern unsigned char cfg_simulate_spd_eeprom[128]; | |
264 | #endif | |
e2ebe696 | 265 | void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value); |
fe8c2806 | 266 | |
d2d43276 SR |
267 | static unsigned char spd_read(uchar chip, uint addr); |
268 | static void get_spd_info(unsigned long *dimm_populated, | |
269 | unsigned char *iic0_dimm_addr, | |
270 | unsigned long num_dimm_banks); | |
271 | static void check_mem_type(unsigned long *dimm_populated, | |
272 | unsigned char *iic0_dimm_addr, | |
273 | unsigned long num_dimm_banks); | |
274 | static void check_volt_type(unsigned long *dimm_populated, | |
275 | unsigned char *iic0_dimm_addr, | |
276 | unsigned long num_dimm_banks); | |
277 | static void program_cfg0(unsigned long *dimm_populated, | |
278 | unsigned char *iic0_dimm_addr, | |
279 | unsigned long num_dimm_banks); | |
280 | static void program_cfg1(unsigned long *dimm_populated, | |
281 | unsigned char *iic0_dimm_addr, | |
282 | unsigned long num_dimm_banks); | |
283 | static void program_rtr(unsigned long *dimm_populated, | |
284 | unsigned char *iic0_dimm_addr, | |
285 | unsigned long num_dimm_banks); | |
286 | static void program_tr0(unsigned long *dimm_populated, | |
287 | unsigned char *iic0_dimm_addr, | |
288 | unsigned long num_dimm_banks); | |
289 | static void program_tr1(void); | |
290 | ||
291 | #ifdef CONFIG_DDR_ECC | |
292 | static void program_ecc(unsigned long num_bytes); | |
293 | #endif | |
fe8c2806 | 294 | |
d2d43276 SR |
295 | static unsigned long program_bxcr(unsigned long *dimm_populated, |
296 | unsigned char *iic0_dimm_addr, | |
297 | unsigned long num_dimm_banks); | |
fe8c2806 WD |
298 | |
299 | /* | |
300 | * This function is reading data from the DIMM module EEPROM over the SPD bus | |
301 | * and uses that to program the sdram controller. | |
302 | * | |
0c8721a4 | 303 | * This works on boards that has the same schematics that the AMCC walnut has. |
fe8c2806 WD |
304 | * |
305 | * BUG: Don't handle ECC memory | |
306 | * BUG: A few values in the TR register is currently hardcoded | |
307 | */ | |
fe8c2806 | 308 | long int spd_sdram(void) { |
c157d8e2 SR |
309 | unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; |
310 | unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; | |
311 | unsigned long total_size; | |
312 | unsigned long cfg0; | |
313 | unsigned long mcsts; | |
f013dacf | 314 | unsigned long num_dimm_banks; /* on board dimm banks */ |
fe8c2806 | 315 | |
c157d8e2 | 316 | num_dimm_banks = sizeof(iic0_dimm_addr); |
fe8c2806 WD |
317 | |
318 | /* | |
319 | * Make sure I2C controller is initialized | |
320 | * before continuing. | |
321 | */ | |
322 | i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); | |
323 | ||
c157d8e2 SR |
324 | /* |
325 | * Read the SPD information using I2C interface. Check to see if the | |
326 | * DIMM slots are populated. | |
327 | */ | |
328 | get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
fe8c2806 | 329 | |
c157d8e2 SR |
330 | /* |
331 | * Check the memory type for the dimms plugged. | |
332 | */ | |
333 | check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
fe8c2806 | 334 | |
c157d8e2 SR |
335 | /* |
336 | * Check the voltage type for the dimms plugged. | |
337 | */ | |
338 | check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
fe8c2806 | 339 | |
ed4633c9 | 340 | #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) |
c157d8e2 SR |
341 | /* |
342 | * Soft-reset SDRAM controller. | |
343 | */ | |
344 | mtsdr(sdr_srst, SDR0_SRST_DMC); | |
345 | mtsdr(sdr_srst, 0x00000000); | |
63153492 WD |
346 | #endif |
347 | ||
c157d8e2 SR |
348 | /* |
349 | * program 440GP SDRAM controller options (SDRAM0_CFG0) | |
350 | */ | |
351 | program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
352 | ||
353 | /* | |
354 | * program 440GP SDRAM controller options (SDRAM0_CFG1) | |
355 | */ | |
356 | program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
357 | ||
358 | /* | |
359 | * program SDRAM refresh register (SDRAM0_RTR) | |
360 | */ | |
361 | program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
362 | ||
363 | /* | |
364 | * program SDRAM Timing Register 0 (SDRAM0_TR0) | |
365 | */ | |
366 | program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); | |
367 | ||
368 | /* | |
369 | * program the BxCR registers to find out total sdram installed | |
370 | */ | |
371 | total_size = program_bxcr(dimm_populated, iic0_dimm_addr, | |
372 | num_dimm_banks); | |
373 | ||
e2ebe696 SR |
374 | #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */ |
375 | /* and program tlb entries for this size (dynamic) */ | |
376 | program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE); | |
377 | #endif | |
378 | ||
c157d8e2 SR |
379 | /* |
380 | * program SDRAM Clock Timing Register (SDRAM0_CLKTR) | |
381 | */ | |
382 | mtsdram(mem_clktr, 0x40000000); | |
383 | ||
384 | /* | |
385 | * delay to ensure 200 usec has elapsed | |
386 | */ | |
387 | udelay(400); | |
388 | ||
389 | /* | |
390 | * enable the memory controller | |
391 | */ | |
392 | mfsdram(mem_cfg0, cfg0); | |
393 | mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); | |
394 | ||
395 | /* | |
396 | * wait for SDRAM_CFG0_DC_EN to complete | |
397 | */ | |
398 | while (1) { | |
399 | mfsdram(mem_mcsts, mcsts); | |
d2d43276 | 400 | if ((mcsts & SDRAM_MCSTS_MRSC) != 0) |
c157d8e2 | 401 | break; |
8bde7f77 | 402 | } |
fe8c2806 | 403 | |
c157d8e2 SR |
404 | /* |
405 | * program SDRAM Timing Register 1, adding some delays | |
406 | */ | |
407 | program_tr1(); | |
fe8c2806 | 408 | |
d2d43276 | 409 | #ifdef CONFIG_DDR_ECC |
c157d8e2 | 410 | /* |
d2d43276 | 411 | * If ecc is enabled, initialize the parity bits. |
c157d8e2 | 412 | */ |
d2d43276 SR |
413 | program_ecc(total_size); |
414 | #endif | |
fe8c2806 WD |
415 | |
416 | return total_size; | |
417 | } | |
418 | ||
d2d43276 | 419 | static unsigned char spd_read(uchar chip, uint addr) |
fd49bf02 | 420 | { |
fe8c2806 WD |
421 | unsigned char data[2]; |
422 | ||
fd49bf02 SR |
423 | #ifdef CFG_SIMULATE_SPD_EEPROM |
424 | if (chip == CFG_SIMULATE_SPD_EEPROM) { | |
425 | /* | |
426 | * Onboard spd eeprom requested -> simulate values | |
427 | */ | |
428 | return cfg_simulate_spd_eeprom[addr]; | |
429 | } | |
430 | #endif /* CFG_SIMULATE_SPD_EEPROM */ | |
431 | ||
c157d8e2 SR |
432 | if (i2c_probe(chip) == 0) { |
433 | if (i2c_read(chip, addr, 1, data, 1) == 0) { | |
434 | return data[0]; | |
435 | } | |
436 | } | |
437 | ||
438 | return 0; | |
fe8c2806 WD |
439 | } |
440 | ||
d2d43276 SR |
441 | static void get_spd_info(unsigned long *dimm_populated, |
442 | unsigned char *iic0_dimm_addr, | |
443 | unsigned long num_dimm_banks) | |
fe8c2806 | 444 | { |
c157d8e2 SR |
445 | unsigned long dimm_num; |
446 | unsigned long dimm_found; | |
447 | unsigned char num_of_bytes; | |
448 | unsigned char total_size; | |
449 | ||
450 | dimm_found = FALSE; | |
451 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
452 | num_of_bytes = 0; | |
453 | total_size = 0; | |
454 | ||
455 | num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); | |
456 | total_size = spd_read(iic0_dimm_addr[dimm_num], 1); | |
457 | ||
458 | if ((num_of_bytes != 0) && (total_size != 0)) { | |
459 | dimm_populated[dimm_num] = TRUE; | |
460 | dimm_found = TRUE; | |
d2d43276 | 461 | debug("DIMM slot %lu: populated\n", dimm_num); |
c157d8e2 SR |
462 | } else { |
463 | dimm_populated[dimm_num] = FALSE; | |
d2d43276 | 464 | debug("DIMM slot %lu: Not populated\n", dimm_num); |
c157d8e2 | 465 | } |
8bde7f77 | 466 | } |
fe8c2806 | 467 | |
c157d8e2 SR |
468 | if (dimm_found == FALSE) { |
469 | printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); | |
470 | hang(); | |
471 | } | |
fe8c2806 WD |
472 | } |
473 | ||
d2d43276 SR |
474 | static void check_mem_type(unsigned long *dimm_populated, |
475 | unsigned char *iic0_dimm_addr, | |
476 | unsigned long num_dimm_banks) | |
fe8c2806 | 477 | { |
c157d8e2 SR |
478 | unsigned long dimm_num; |
479 | unsigned char dimm_type; | |
480 | ||
481 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
482 | if (dimm_populated[dimm_num] == TRUE) { | |
483 | dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); | |
484 | switch (dimm_type) { | |
485 | case 7: | |
d2d43276 | 486 | debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); |
c157d8e2 SR |
487 | break; |
488 | default: | |
489 | printf("ERROR: Unsupported DIMM detected in slot %lu.\n", | |
490 | dimm_num); | |
491 | printf("Only DDR SDRAM DIMMs are supported.\n"); | |
492 | printf("Replace the DIMM module with a supported DIMM.\n\n"); | |
493 | hang(); | |
494 | break; | |
495 | } | |
496 | } | |
8bde7f77 | 497 | } |
fe8c2806 WD |
498 | } |
499 | ||
d2d43276 SR |
500 | static void check_volt_type(unsigned long *dimm_populated, |
501 | unsigned char *iic0_dimm_addr, | |
502 | unsigned long num_dimm_banks) | |
fe8c2806 | 503 | { |
c157d8e2 SR |
504 | unsigned long dimm_num; |
505 | unsigned long voltage_type; | |
506 | ||
507 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
508 | if (dimm_populated[dimm_num] == TRUE) { | |
509 | voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); | |
510 | if (voltage_type != 0x04) { | |
511 | printf("ERROR: DIMM %lu with unsupported voltage level.\n", | |
512 | dimm_num); | |
513 | hang(); | |
514 | } else { | |
d2d43276 | 515 | debug("DIMM %lu voltage level supported.\n", dimm_num); |
c157d8e2 SR |
516 | } |
517 | break; | |
518 | } | |
8bde7f77 | 519 | } |
fe8c2806 WD |
520 | } |
521 | ||
d2d43276 SR |
522 | static void program_cfg0(unsigned long *dimm_populated, |
523 | unsigned char *iic0_dimm_addr, | |
524 | unsigned long num_dimm_banks) | |
fe8c2806 | 525 | { |
c157d8e2 SR |
526 | unsigned long dimm_num; |
527 | unsigned long cfg0; | |
528 | unsigned long ecc_enabled; | |
529 | unsigned char ecc; | |
530 | unsigned char attributes; | |
531 | unsigned long data_width; | |
532 | unsigned long dimm_32bit; | |
533 | unsigned long dimm_64bit; | |
534 | ||
535 | /* | |
536 | * get Memory Controller Options 0 data | |
537 | */ | |
538 | mfsdram(mem_cfg0, cfg0); | |
539 | ||
540 | /* | |
541 | * clear bits | |
542 | */ | |
543 | cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | | |
544 | SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | | |
545 | SDRAM_CFG0_DMWD_MASK | | |
546 | SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); | |
547 | ||
548 | ||
549 | /* | |
550 | * FIXME: assume the DDR SDRAMs in both banks are the same | |
551 | */ | |
552 | ecc_enabled = TRUE; | |
553 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
554 | if (dimm_populated[dimm_num] == TRUE) { | |
555 | ecc = spd_read(iic0_dimm_addr[dimm_num], 11); | |
556 | if (ecc != 0x02) { | |
557 | ecc_enabled = FALSE; | |
558 | } | |
559 | ||
560 | /* | |
561 | * program Registered DIMM Enable | |
562 | */ | |
563 | attributes = spd_read(iic0_dimm_addr[dimm_num], 21); | |
564 | if ((attributes & 0x02) != 0x00) { | |
565 | cfg0 |= SDRAM_CFG0_RDEN; | |
566 | } | |
567 | ||
568 | /* | |
569 | * program DDR SDRAM Data Width | |
570 | */ | |
571 | data_width = | |
572 | (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + | |
573 | (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); | |
574 | if (data_width == 64 || data_width == 72) { | |
575 | dimm_64bit = TRUE; | |
576 | cfg0 |= SDRAM_CFG0_DMWD_64; | |
577 | } else if (data_width == 32 || data_width == 40) { | |
578 | dimm_32bit = TRUE; | |
579 | cfg0 |= SDRAM_CFG0_DMWD_32; | |
580 | } else { | |
581 | printf("WARNING: DIMM with datawidth of %lu bits.\n", | |
582 | data_width); | |
583 | printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); | |
584 | hang(); | |
585 | } | |
586 | break; | |
587 | } | |
8bde7f77 | 588 | } |
c157d8e2 SR |
589 | |
590 | /* | |
591 | * program Memory Data Error Checking | |
592 | */ | |
593 | if (ecc_enabled == TRUE) { | |
594 | cfg0 |= SDRAM_CFG0_MCHK_GEN; | |
595 | } else { | |
596 | cfg0 |= SDRAM_CFG0_MCHK_NON; | |
597 | } | |
598 | ||
599 | /* | |
a2c95a72 | 600 | * program Page Management Unit (0 == enabled) |
c157d8e2 | 601 | */ |
a2c95a72 | 602 | cfg0 &= ~SDRAM_CFG0_PMUD; |
c157d8e2 SR |
603 | |
604 | /* | |
605 | * program Memory Controller Options 0 | |
606 | * Note: DCEN must be enabled after all DDR SDRAM controller | |
607 | * configuration registers get initialized. | |
608 | */ | |
609 | mtsdram(mem_cfg0, cfg0); | |
fe8c2806 WD |
610 | } |
611 | ||
d2d43276 SR |
612 | static void program_cfg1(unsigned long *dimm_populated, |
613 | unsigned char *iic0_dimm_addr, | |
614 | unsigned long num_dimm_banks) | |
fe8c2806 | 615 | { |
c157d8e2 SR |
616 | unsigned long cfg1; |
617 | mfsdram(mem_cfg1, cfg1); | |
618 | ||
619 | /* | |
620 | * Self-refresh exit, disable PM | |
621 | */ | |
622 | cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); | |
623 | ||
624 | /* | |
625 | * program Memory Controller Options 1 | |
626 | */ | |
627 | mtsdram(mem_cfg1, cfg1); | |
fe8c2806 WD |
628 | } |
629 | ||
d2d43276 SR |
630 | static void program_rtr(unsigned long *dimm_populated, |
631 | unsigned char *iic0_dimm_addr, | |
632 | unsigned long num_dimm_banks) | |
fe8c2806 | 633 | { |
c157d8e2 SR |
634 | unsigned long dimm_num; |
635 | unsigned long bus_period_x_10; | |
636 | unsigned long refresh_rate = 0; | |
637 | unsigned char refresh_rate_type; | |
638 | unsigned long refresh_interval; | |
639 | unsigned long sdram_rtr; | |
640 | PPC440_SYS_INFO sys_info; | |
641 | ||
642 | /* | |
643 | * get the board info | |
644 | */ | |
645 | get_sys_info(&sys_info); | |
646 | bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); | |
647 | ||
c157d8e2 SR |
648 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
649 | if (dimm_populated[dimm_num] == TRUE) { | |
650 | refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); | |
651 | switch (refresh_rate_type) { | |
652 | case 0x00: | |
653 | refresh_rate = 15625; | |
654 | break; | |
655 | case 0x01: | |
656 | refresh_rate = 15625/4; | |
657 | break; | |
658 | case 0x02: | |
659 | refresh_rate = 15625/2; | |
660 | break; | |
661 | case 0x03: | |
662 | refresh_rate = 15626*2; | |
663 | break; | |
664 | case 0x04: | |
665 | refresh_rate = 15625*4; | |
666 | break; | |
667 | case 0x05: | |
668 | refresh_rate = 15625*8; | |
669 | break; | |
670 | default: | |
671 | printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", | |
672 | dimm_num); | |
673 | printf("Replace the DIMM module with a supported DIMM.\n"); | |
674 | break; | |
675 | } | |
676 | ||
677 | break; | |
678 | } | |
8bde7f77 | 679 | } |
fe8c2806 | 680 | |
c157d8e2 SR |
681 | refresh_interval = refresh_rate * 10 / bus_period_x_10; |
682 | sdram_rtr = (refresh_interval & 0x3ff8) << 16; | |
fe8c2806 | 683 | |
c157d8e2 SR |
684 | /* |
685 | * program Refresh Timer Register (SDRAM0_RTR) | |
686 | */ | |
687 | mtsdram(mem_rtr, sdram_rtr); | |
fe8c2806 WD |
688 | } |
689 | ||
d2d43276 SR |
690 | static void program_tr0(unsigned long *dimm_populated, |
691 | unsigned char *iic0_dimm_addr, | |
692 | unsigned long num_dimm_banks) | |
fe8c2806 | 693 | { |
c157d8e2 SR |
694 | unsigned long dimm_num; |
695 | unsigned long tr0; | |
696 | unsigned char wcsbc; | |
697 | unsigned char t_rp_ns; | |
698 | unsigned char t_rcd_ns; | |
699 | unsigned char t_ras_ns; | |
700 | unsigned long t_rp_clk; | |
701 | unsigned long t_ras_rcd_clk; | |
702 | unsigned long t_rcd_clk; | |
703 | unsigned long t_rfc_clk; | |
704 | unsigned long plb_check; | |
705 | unsigned char cas_bit; | |
706 | unsigned long cas_index; | |
707 | unsigned char cas_2_0_available; | |
708 | unsigned char cas_2_5_available; | |
709 | unsigned char cas_3_0_available; | |
710 | unsigned long cycle_time_ns_x_10[3]; | |
711 | unsigned long tcyc_3_0_ns_x_10; | |
712 | unsigned long tcyc_2_5_ns_x_10; | |
713 | unsigned long tcyc_2_0_ns_x_10; | |
714 | unsigned long tcyc_reg; | |
715 | unsigned long bus_period_x_10; | |
716 | PPC440_SYS_INFO sys_info; | |
717 | unsigned long residue; | |
8bde7f77 | 718 | |
c157d8e2 SR |
719 | /* |
720 | * get the board info | |
721 | */ | |
722 | get_sys_info(&sys_info); | |
723 | bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); | |
8bde7f77 | 724 | |
c157d8e2 SR |
725 | /* |
726 | * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits | |
727 | */ | |
728 | mfsdram(mem_tr0, tr0); | |
729 | tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | | |
730 | SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | | |
731 | SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | | |
732 | SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); | |
733 | ||
734 | /* | |
735 | * initialization | |
736 | */ | |
737 | wcsbc = 0; | |
738 | t_rp_ns = 0; | |
739 | t_rcd_ns = 0; | |
740 | t_ras_ns = 0; | |
741 | cas_2_0_available = TRUE; | |
742 | cas_2_5_available = TRUE; | |
743 | cas_3_0_available = TRUE; | |
744 | tcyc_2_0_ns_x_10 = 0; | |
745 | tcyc_2_5_ns_x_10 = 0; | |
746 | tcyc_3_0_ns_x_10 = 0; | |
747 | ||
748 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
749 | if (dimm_populated[dimm_num] == TRUE) { | |
750 | wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); | |
f013dacf | 751 | t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; |
c157d8e2 SR |
752 | t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; |
753 | t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); | |
754 | cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); | |
755 | ||
756 | for (cas_index = 0; cas_index < 3; cas_index++) { | |
757 | switch (cas_index) { | |
758 | case 0: | |
759 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); | |
760 | break; | |
761 | case 1: | |
762 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); | |
763 | break; | |
764 | default: | |
765 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); | |
766 | break; | |
767 | } | |
768 | ||
769 | if ((tcyc_reg & 0x0F) >= 10) { | |
770 | printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", | |
771 | dimm_num); | |
772 | hang(); | |
773 | } | |
774 | ||
775 | cycle_time_ns_x_10[cas_index] = | |
776 | (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); | |
777 | } | |
778 | ||
779 | cas_index = 0; | |
780 | ||
781 | if ((cas_bit & 0x80) != 0) { | |
782 | cas_index += 3; | |
783 | } else if ((cas_bit & 0x40) != 0) { | |
784 | cas_index += 2; | |
785 | } else if ((cas_bit & 0x20) != 0) { | |
786 | cas_index += 1; | |
787 | } | |
788 | ||
789 | if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { | |
790 | tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; | |
791 | cas_index++; | |
792 | } else { | |
793 | if (cas_index != 0) { | |
794 | cas_index++; | |
795 | } | |
796 | cas_3_0_available = FALSE; | |
797 | } | |
798 | ||
799 | if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { | |
800 | tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; | |
801 | cas_index++; | |
802 | } else { | |
803 | if (cas_index != 0) { | |
804 | cas_index++; | |
805 | } | |
806 | cas_2_5_available = FALSE; | |
807 | } | |
808 | ||
809 | if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { | |
810 | tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; | |
811 | cas_index++; | |
812 | } else { | |
813 | if (cas_index != 0) { | |
814 | cas_index++; | |
815 | } | |
816 | cas_2_0_available = FALSE; | |
817 | } | |
818 | ||
819 | break; | |
8bde7f77 | 820 | } |
c157d8e2 SR |
821 | } |
822 | ||
823 | /* | |
824 | * Program SD_WR and SD_WCSBC fields | |
825 | */ | |
f013dacf | 826 | tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ |
c157d8e2 SR |
827 | switch (wcsbc) { |
828 | case 0: | |
829 | tr0 |= SDRAM_TR0_SDWD_0_CLK; | |
830 | break; | |
831 | default: | |
832 | tr0 |= SDRAM_TR0_SDWD_1_CLK; | |
833 | break; | |
834 | } | |
835 | ||
836 | /* | |
837 | * Program SD_CASL field | |
838 | */ | |
839 | if ((cas_2_0_available == TRUE) && | |
840 | (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { | |
841 | tr0 |= SDRAM_TR0_SDCL_2_0_CLK; | |
842 | } else if ((cas_2_5_available == TRUE) && | |
843 | (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { | |
844 | tr0 |= SDRAM_TR0_SDCL_2_5_CLK; | |
845 | } else if ((cas_3_0_available == TRUE) && | |
846 | (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { | |
847 | tr0 |= SDRAM_TR0_SDCL_3_0_CLK; | |
848 | } else { | |
849 | printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); | |
850 | printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); | |
851 | printf("Make sure the PLB speed is within the supported range.\n"); | |
852 | hang(); | |
853 | } | |
854 | ||
855 | /* | |
856 | * Calculate Trp in clock cycles and round up if necessary | |
857 | * Program SD_PTA field | |
858 | */ | |
859 | t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; | |
860 | plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; | |
861 | if (sys_info.freqPLB != plb_check) { | |
862 | t_rp_clk++; | |
863 | } | |
864 | switch ((unsigned long)t_rp_clk) { | |
865 | case 0: | |
866 | case 1: | |
867 | case 2: | |
868 | tr0 |= SDRAM_TR0_SDPA_2_CLK; | |
869 | break; | |
870 | case 3: | |
871 | tr0 |= SDRAM_TR0_SDPA_3_CLK; | |
872 | break; | |
873 | default: | |
874 | tr0 |= SDRAM_TR0_SDPA_4_CLK; | |
875 | break; | |
876 | } | |
877 | ||
878 | /* | |
879 | * Program SD_CTP field | |
880 | */ | |
881 | t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; | |
882 | plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); | |
883 | if (sys_info.freqPLB != plb_check) { | |
884 | t_ras_rcd_clk++; | |
885 | } | |
886 | switch (t_ras_rcd_clk) { | |
887 | case 0: | |
888 | case 1: | |
889 | case 2: | |
890 | tr0 |= SDRAM_TR0_SDCP_2_CLK; | |
891 | break; | |
892 | case 3: | |
893 | tr0 |= SDRAM_TR0_SDCP_3_CLK; | |
894 | break; | |
895 | case 4: | |
896 | tr0 |= SDRAM_TR0_SDCP_4_CLK; | |
897 | break; | |
898 | default: | |
899 | tr0 |= SDRAM_TR0_SDCP_5_CLK; | |
900 | break; | |
901 | } | |
902 | ||
903 | /* | |
904 | * Program SD_LDF field | |
905 | */ | |
906 | tr0 |= SDRAM_TR0_SDLD_2_CLK; | |
907 | ||
908 | /* | |
909 | * Program SD_RFTA field | |
910 | * FIXME tRFC hardcoded as 75 nanoseconds | |
911 | */ | |
912 | t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); | |
913 | residue = sys_info.freqPLB % (ONE_BILLION / 75); | |
914 | if (residue >= (ONE_BILLION / 150)) { | |
915 | t_rfc_clk++; | |
916 | } | |
917 | switch (t_rfc_clk) { | |
918 | case 0: | |
919 | case 1: | |
920 | case 2: | |
921 | case 3: | |
922 | case 4: | |
923 | case 5: | |
924 | case 6: | |
925 | tr0 |= SDRAM_TR0_SDRA_6_CLK; | |
926 | break; | |
927 | case 7: | |
928 | tr0 |= SDRAM_TR0_SDRA_7_CLK; | |
929 | break; | |
930 | case 8: | |
931 | tr0 |= SDRAM_TR0_SDRA_8_CLK; | |
932 | break; | |
933 | case 9: | |
934 | tr0 |= SDRAM_TR0_SDRA_9_CLK; | |
935 | break; | |
936 | case 10: | |
937 | tr0 |= SDRAM_TR0_SDRA_10_CLK; | |
938 | break; | |
939 | case 11: | |
940 | tr0 |= SDRAM_TR0_SDRA_11_CLK; | |
941 | break; | |
942 | case 12: | |
943 | tr0 |= SDRAM_TR0_SDRA_12_CLK; | |
944 | break; | |
945 | default: | |
946 | tr0 |= SDRAM_TR0_SDRA_13_CLK; | |
947 | break; | |
948 | } | |
8bde7f77 | 949 | |
c157d8e2 SR |
950 | /* |
951 | * Program SD_RCD field | |
952 | */ | |
953 | t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; | |
954 | plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; | |
955 | if (sys_info.freqPLB != plb_check) { | |
956 | t_rcd_clk++; | |
957 | } | |
958 | switch (t_rcd_clk) { | |
959 | case 0: | |
960 | case 1: | |
961 | case 2: | |
962 | tr0 |= SDRAM_TR0_SDRD_2_CLK; | |
963 | break; | |
964 | case 3: | |
965 | tr0 |= SDRAM_TR0_SDRD_3_CLK; | |
966 | break; | |
967 | default: | |
968 | tr0 |= SDRAM_TR0_SDRD_4_CLK; | |
969 | break; | |
8bde7f77 | 970 | } |
fe8c2806 | 971 | |
d2d43276 | 972 | debug("tr0: %x\n", tr0); |
c157d8e2 | 973 | mtsdram(mem_tr0, tr0); |
fe8c2806 WD |
974 | } |
975 | ||
d2d43276 SR |
976 | static int short_mem_test(void) |
977 | { | |
978 | unsigned long i, j; | |
979 | unsigned long bxcr_num; | |
980 | unsigned long *membase; | |
981 | const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { | |
982 | {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, | |
983 | 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, | |
984 | {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, | |
985 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, | |
986 | {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, | |
987 | 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, | |
988 | {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, | |
989 | 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, | |
990 | {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, | |
991 | 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, | |
992 | {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, | |
993 | 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, | |
994 | {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, | |
995 | 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, | |
996 | {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, | |
997 | 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; | |
998 | ||
999 | for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { | |
1000 | mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); | |
1001 | if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { | |
1002 | /* Bank is enabled */ | |
1003 | membase = (unsigned long*) | |
1004 | (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); | |
1005 | ||
1006 | /* | |
1007 | * Run the short memory test | |
1008 | */ | |
1009 | for (i = 0; i < NUMMEMTESTS; i++) { | |
1010 | for (j = 0; j < NUMMEMWORDS; j++) { | |
1011 | membase[j] = test[i][j]; | |
1012 | ppcDcbf((unsigned long)&(membase[j])); | |
1013 | } | |
1014 | ||
1015 | for (j = 0; j < NUMMEMWORDS; j++) { | |
1016 | if (membase[j] != test[i][j]) { | |
1017 | ppcDcbf((unsigned long)&(membase[j])); | |
1018 | return 0; | |
1019 | } | |
1020 | ppcDcbf((unsigned long)&(membase[j])); | |
1021 | } | |
1022 | ||
1023 | if (j < NUMMEMWORDS) | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * see if the rdclt value passed | |
1029 | */ | |
1030 | if (i < NUMMEMTESTS) | |
1031 | return 0; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | return 1; | |
1036 | } | |
1037 | ||
1038 | static void program_tr1(void) | |
fe8c2806 | 1039 | { |
c157d8e2 SR |
1040 | unsigned long tr0; |
1041 | unsigned long tr1; | |
1042 | unsigned long cfg0; | |
1043 | unsigned long ecc_temp; | |
1044 | unsigned long dlycal; | |
1045 | unsigned long dly_val; | |
d2d43276 | 1046 | unsigned long k; |
c157d8e2 SR |
1047 | unsigned long max_pass_length; |
1048 | unsigned long current_pass_length; | |
1049 | unsigned long current_fail_length; | |
1050 | unsigned long current_start; | |
1051 | unsigned long rdclt; | |
1052 | unsigned long rdclt_offset; | |
1053 | long max_start; | |
1054 | long max_end; | |
1055 | long rdclt_average; | |
1056 | unsigned char window_found; | |
1057 | unsigned char fail_found; | |
1058 | unsigned char pass_found; | |
c157d8e2 SR |
1059 | PPC440_SYS_INFO sys_info; |
1060 | ||
1061 | /* | |
1062 | * get the board info | |
1063 | */ | |
1064 | get_sys_info(&sys_info); | |
1065 | ||
1066 | /* | |
1067 | * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits | |
1068 | */ | |
1069 | mfsdram(mem_tr1, tr1); | |
1070 | tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | | |
1071 | SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); | |
1072 | ||
1073 | mfsdram(mem_tr0, tr0); | |
1074 | if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && | |
1075 | (sys_info.freqPLB > 100000000)) { | |
1076 | tr1 |= SDRAM_TR1_RDSS_TR2; | |
1077 | tr1 |= SDRAM_TR1_RDSL_STAGE3; | |
1078 | tr1 |= SDRAM_TR1_RDCD_RCD_1_2; | |
1079 | } else { | |
1080 | tr1 |= SDRAM_TR1_RDSS_TR1; | |
1081 | tr1 |= SDRAM_TR1_RDSL_STAGE2; | |
1082 | tr1 |= SDRAM_TR1_RDCD_RCD_0_0; | |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * save CFG0 ECC setting to a temporary variable and turn ECC off | |
1087 | */ | |
1088 | mfsdram(mem_cfg0, cfg0); | |
1089 | ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; | |
1090 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); | |
1091 | ||
1092 | /* | |
1093 | * get the delay line calibration register value | |
1094 | */ | |
1095 | mfsdram(mem_dlycal, dlycal); | |
1096 | dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; | |
1097 | ||
1098 | max_pass_length = 0; | |
1099 | max_start = 0; | |
1100 | max_end = 0; | |
1101 | current_pass_length = 0; | |
1102 | current_fail_length = 0; | |
1103 | current_start = 0; | |
1104 | rdclt_offset = 0; | |
1105 | window_found = FALSE; | |
1106 | fail_found = FALSE; | |
1107 | pass_found = FALSE; | |
d2d43276 SR |
1108 | debug("Starting memory test "); |
1109 | ||
c157d8e2 | 1110 | for (k = 0; k < NUMHALFCYCLES; k++) { |
d2d43276 | 1111 | for (rdclt = 0; rdclt < dly_val; rdclt++) { |
c157d8e2 SR |
1112 | /* |
1113 | * Set the timing reg for the test. | |
1114 | */ | |
1115 | mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); | |
1116 | ||
d2d43276 | 1117 | if (short_mem_test()) { |
c157d8e2 SR |
1118 | if (fail_found == TRUE) { |
1119 | pass_found = TRUE; | |
1120 | if (current_pass_length == 0) { | |
1121 | current_start = rdclt_offset + rdclt; | |
1122 | } | |
1123 | ||
1124 | current_fail_length = 0; | |
1125 | current_pass_length++; | |
1126 | ||
1127 | if (current_pass_length > max_pass_length) { | |
1128 | max_pass_length = current_pass_length; | |
1129 | max_start = current_start; | |
1130 | max_end = rdclt_offset + rdclt; | |
1131 | } | |
1132 | } | |
1133 | } else { | |
1134 | current_pass_length = 0; | |
1135 | current_fail_length++; | |
1136 | ||
1137 | if (current_fail_length >= (dly_val>>2)) { | |
1138 | if (fail_found == FALSE) { | |
1139 | fail_found = TRUE; | |
1140 | } else if (pass_found == TRUE) { | |
1141 | window_found = TRUE; | |
1142 | break; | |
1143 | } | |
1144 | } | |
8bde7f77 | 1145 | } |
8bde7f77 | 1146 | } |
d2d43276 SR |
1147 | debug("."); |
1148 | ||
c157d8e2 | 1149 | if (window_found == TRUE) { |
8bde7f77 | 1150 | break; |
8bde7f77 | 1151 | } |
c157d8e2 SR |
1152 | |
1153 | tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; | |
1154 | rdclt_offset += dly_val; | |
8bde7f77 | 1155 | } |
d2d43276 | 1156 | debug("\n"); |
c157d8e2 SR |
1157 | |
1158 | /* | |
1159 | * make sure we find the window | |
1160 | */ | |
1161 | if (window_found == FALSE) { | |
1162 | printf("ERROR: Cannot determine a common read delay.\n"); | |
1163 | hang(); | |
8bde7f77 | 1164 | } |
fe8c2806 | 1165 | |
c157d8e2 SR |
1166 | /* |
1167 | * restore the orignal ECC setting | |
1168 | */ | |
1169 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); | |
1170 | ||
1171 | /* | |
1172 | * set the SDRAM TR1 RDCD value | |
1173 | */ | |
1174 | tr1 &= ~SDRAM_TR1_RDCD_MASK; | |
1175 | if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { | |
1176 | tr1 |= SDRAM_TR1_RDCD_RCD_1_2; | |
1177 | } else { | |
1178 | tr1 |= SDRAM_TR1_RDCD_RCD_0_0; | |
1179 | } | |
fe8c2806 | 1180 | |
c157d8e2 SR |
1181 | /* |
1182 | * set the SDRAM TR1 RDCLT value | |
1183 | */ | |
1184 | tr1 &= ~SDRAM_TR1_RDCT_MASK; | |
1185 | while (max_end >= (dly_val << 1)) { | |
1186 | max_end -= (dly_val << 1); | |
1187 | max_start -= (dly_val << 1); | |
1188 | } | |
1189 | ||
1190 | rdclt_average = ((max_start + max_end) >> 1); | |
1191 | if (rdclt_average >= 0x60) | |
1192 | while (1) | |
1193 | ; | |
1194 | ||
1195 | if (rdclt_average < 0) { | |
1196 | rdclt_average = 0; | |
1197 | } | |
1198 | ||
1199 | if (rdclt_average >= dly_val) { | |
1200 | rdclt_average -= dly_val; | |
1201 | tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; | |
1202 | } | |
1203 | tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); | |
fe8c2806 | 1204 | |
d2d43276 SR |
1205 | debug("tr1: %x\n", tr1); |
1206 | ||
c157d8e2 SR |
1207 | /* |
1208 | * program SDRAM Timing Register 1 TR1 | |
1209 | */ | |
1210 | mtsdram(mem_tr1, tr1); | |
fe8c2806 WD |
1211 | } |
1212 | ||
d2d43276 SR |
1213 | static unsigned long program_bxcr(unsigned long *dimm_populated, |
1214 | unsigned char *iic0_dimm_addr, | |
1215 | unsigned long num_dimm_banks) | |
fe8c2806 | 1216 | { |
c157d8e2 | 1217 | unsigned long dimm_num; |
c157d8e2 | 1218 | unsigned long bank_base_addr; |
c157d8e2 SR |
1219 | unsigned long cr; |
1220 | unsigned long i; | |
fd49bf02 | 1221 | unsigned long j; |
c157d8e2 SR |
1222 | unsigned long temp; |
1223 | unsigned char num_row_addr; | |
1224 | unsigned char num_col_addr; | |
1225 | unsigned char num_banks; | |
1226 | unsigned char bank_size_id; | |
fd49bf02 SR |
1227 | unsigned long ctrl_bank_num[MAXBANKS]; |
1228 | unsigned long bx_cr_num; | |
1229 | unsigned long largest_size_index; | |
f013dacf WD |
1230 | unsigned long largest_size; |
1231 | unsigned long current_size_index; | |
fd49bf02 SR |
1232 | BANKPARMS bank_parms[MAXBXCR]; |
1233 | unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ | |
1234 | unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ | |
c157d8e2 SR |
1235 | |
1236 | /* | |
1237 | * Set the BxCR regs. First, wipe out the bank config registers. | |
1238 | */ | |
fd49bf02 SR |
1239 | for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { |
1240 | mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); | |
c157d8e2 | 1241 | mtdcr(memcfgd, 0x00000000); |
fd49bf02 | 1242 | bank_parms[bx_cr_num].bank_size_bytes = 0; |
c157d8e2 | 1243 | } |
fd49bf02 SR |
1244 | |
1245 | #ifdef CONFIG_BAMBOO | |
1246 | /* | |
1247 | * This next section is hardware dependent and must be programmed | |
d2d43276 SR |
1248 | * to match the hardware. For bamboo, the following holds... |
1249 | * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard) | |
fd49bf02 SR |
1250 | * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 |
1251 | * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 | |
1252 | * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 | |
1253 | * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM | |
1254 | */ | |
1255 | ctrl_bank_num[0] = 0; | |
1256 | ctrl_bank_num[1] = 1; | |
1257 | ctrl_bank_num[2] = 3; | |
1258 | #else | |
d2d43276 SR |
1259 | /* |
1260 | * Ocotea, Ebony and the other IBM/AMCC eval boards have | |
1261 | * 2 DIMM slots with each max 2 banks | |
1262 | */ | |
fd49bf02 | 1263 | ctrl_bank_num[0] = 0; |
d2d43276 | 1264 | ctrl_bank_num[1] = 2; |
17f50f22 | 1265 | #endif |
c157d8e2 SR |
1266 | |
1267 | /* | |
1268 | * reset the bank_base address | |
1269 | */ | |
1270 | bank_base_addr = CFG_SDRAM_BASE; | |
1271 | ||
1272 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { | |
1273 | if (dimm_populated[dimm_num] == TRUE) { | |
1274 | num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); | |
1275 | num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); | |
1276 | num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); | |
1277 | bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); | |
d2d43276 SR |
1278 | debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num, |
1279 | num_row_addr, num_col_addr, num_banks); | |
c157d8e2 SR |
1280 | |
1281 | /* | |
1282 | * Set the SDRAM0_BxCR regs | |
1283 | */ | |
1284 | cr = 0; | |
c157d8e2 SR |
1285 | switch (bank_size_id) { |
1286 | case 0x02: | |
1287 | cr |= SDRAM_BXCR_SDSZ_8; | |
1288 | break; | |
1289 | case 0x04: | |
1290 | cr |= SDRAM_BXCR_SDSZ_16; | |
1291 | break; | |
1292 | case 0x08: | |
1293 | cr |= SDRAM_BXCR_SDSZ_32; | |
1294 | break; | |
1295 | case 0x10: | |
1296 | cr |= SDRAM_BXCR_SDSZ_64; | |
1297 | break; | |
1298 | case 0x20: | |
1299 | cr |= SDRAM_BXCR_SDSZ_128; | |
1300 | break; | |
1301 | case 0x40: | |
1302 | cr |= SDRAM_BXCR_SDSZ_256; | |
1303 | break; | |
1304 | case 0x80: | |
1305 | cr |= SDRAM_BXCR_SDSZ_512; | |
1306 | break; | |
1307 | default: | |
1308 | printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", | |
1309 | dimm_num); | |
1310 | printf("ERROR: Unsupported value for the banksize: %d.\n", | |
1311 | bank_size_id); | |
1312 | printf("Replace the DIMM module with a supported DIMM.\n\n"); | |
1313 | hang(); | |
1314 | } | |
1315 | ||
1316 | switch (num_col_addr) { | |
1317 | case 0x08: | |
1318 | cr |= SDRAM_BXCR_SDAM_1; | |
1319 | break; | |
1320 | case 0x09: | |
1321 | cr |= SDRAM_BXCR_SDAM_2; | |
1322 | break; | |
1323 | case 0x0A: | |
1324 | cr |= SDRAM_BXCR_SDAM_3; | |
1325 | break; | |
1326 | case 0x0B: | |
1327 | cr |= SDRAM_BXCR_SDAM_4; | |
1328 | break; | |
1329 | default: | |
1330 | printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", | |
1331 | dimm_num); | |
1332 | printf("ERROR: Unsupported value for number of " | |
1333 | "column addresses: %d.\n", num_col_addr); | |
1334 | printf("Replace the DIMM module with a supported DIMM.\n\n"); | |
1335 | hang(); | |
1336 | } | |
1337 | ||
1338 | /* | |
1339 | * enable the bank | |
1340 | */ | |
1341 | cr |= SDRAM_BXCR_SDBE; | |
1342 | ||
e2ebe696 | 1343 | for (i = 0; i < num_banks; i++) { |
d2d43276 SR |
1344 | bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = |
1345 | (4 << 20) * bank_size_id; | |
1346 | bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; | |
1347 | debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", | |
1348 | dimm_num, i, ctrl_bank_num[dimm_num]+i, | |
1349 | bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); | |
e2ebe696 | 1350 | } |
8bde7f77 | 1351 | } |
8bde7f77 | 1352 | } |
fe8c2806 | 1353 | |
fd49bf02 SR |
1354 | /* Initialize sort tables */ |
1355 | for (i = 0; i < MAXBXCR; i++) { | |
1356 | sorted_bank_num[i] = i; | |
1357 | sorted_bank_size[i] = bank_parms[i].bank_size_bytes; | |
1358 | } | |
1359 | ||
1360 | for (i = 0; i < MAXBXCR-1; i++) { | |
1361 | largest_size = sorted_bank_size[i]; | |
1362 | largest_size_index = 255; | |
1363 | ||
1364 | /* Find the largest remaining value */ | |
1365 | for (j = i + 1; j < MAXBXCR; j++) { | |
1366 | if (sorted_bank_size[j] > largest_size) { | |
1367 | /* Save largest remaining value and its index */ | |
1368 | largest_size = sorted_bank_size[j]; | |
1369 | largest_size_index = j; | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | if (largest_size_index != 255) { | |
1374 | /* Swap the current and largest values */ | |
1375 | current_size_index = sorted_bank_num[largest_size_index]; | |
1376 | sorted_bank_size[largest_size_index] = sorted_bank_size[i]; | |
1377 | sorted_bank_size[i] = largest_size; | |
1378 | sorted_bank_num[largest_size_index] = sorted_bank_num[i]; | |
1379 | sorted_bank_num[i] = current_size_index; | |
1380 | } | |
1381 | } | |
1382 | ||
1383 | /* Set the SDRAM0_BxCR regs thanks to sort tables */ | |
1384 | for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { | |
1385 | if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { | |
1386 | mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); | |
1387 | temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | | |
1388 | SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); | |
1389 | temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | | |
1390 | bank_parms[sorted_bank_num[bx_cr_num]].cr; | |
1391 | mtdcr(memcfgd, temp); | |
1392 | bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; | |
d2d43276 | 1393 | debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); |
fd49bf02 SR |
1394 | } |
1395 | } | |
1396 | ||
c157d8e2 | 1397 | return(bank_base_addr); |
fe8c2806 WD |
1398 | } |
1399 | ||
d2d43276 SR |
1400 | #ifdef CONFIG_DDR_ECC |
1401 | static void program_ecc(unsigned long num_bytes) | |
fe8c2806 | 1402 | { |
c157d8e2 SR |
1403 | unsigned long bank_base_addr; |
1404 | unsigned long current_address; | |
1405 | unsigned long end_address; | |
1406 | unsigned long address_increment; | |
1407 | unsigned long cfg0; | |
8bde7f77 | 1408 | |
c157d8e2 SR |
1409 | /* |
1410 | * get Memory Controller Options 0 data | |
1411 | */ | |
1412 | mfsdram(mem_cfg0, cfg0); | |
8bde7f77 | 1413 | |
c157d8e2 SR |
1414 | /* |
1415 | * reset the bank_base address | |
1416 | */ | |
1417 | bank_base_addr = CFG_SDRAM_BASE; | |
1418 | ||
1419 | if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { | |
d2d43276 | 1420 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); |
c157d8e2 | 1421 | |
d2d43276 | 1422 | if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) |
c157d8e2 | 1423 | address_increment = 4; |
d2d43276 | 1424 | else |
c157d8e2 | 1425 | address_increment = 8; |
c157d8e2 SR |
1426 | |
1427 | current_address = (unsigned long)(bank_base_addr); | |
1428 | end_address = (unsigned long)(bank_base_addr) + num_bytes; | |
8bde7f77 | 1429 | |
c157d8e2 SR |
1430 | while (current_address < end_address) { |
1431 | *((unsigned long*)current_address) = 0x00000000; | |
1432 | current_address += address_increment; | |
1433 | } | |
1434 | ||
1435 | mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | | |
1436 | SDRAM_CFG0_MCHK_CHK); | |
1437 | } | |
fe8c2806 | 1438 | } |
d2d43276 | 1439 | #endif /* CONFIG_DDR_ECC */ |
fe8c2806 | 1440 | #endif /* CONFIG_SPD_EEPROM */ |