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Restructure POST directory to support of other CPUs, boards, etc.
[people/ms/u-boot.git] / cpu / ppc4xx / 44x_spd_ddr2.c
CommitLineData
4037ed3b
SR		 1/*
2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those are 440SP/SPe.
5 *
6 * (C) Copyright 2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * COPYRIGHT AMCC CORPORATION 2004
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 *
29 */
30
31/* define DEBUG for debugging output (obviously ;-)) */
32#if 0
33#define DEBUG
34#endif
35
36#include <common.h>
ba58e4c9 37#include <command.h>
4037ed3b
SR		 38#include <ppc4xx.h>
39#include <i2c.h>
40#include <asm/io.h>
41#include <asm/processor.h>
42#include <asm/mmu.h>
43
44#if defined(CONFIG_SPD_EEPROM) && \
45 (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
46
ba58e4c9
SR		 47/*-----------------------------------------------------------------------------+
48 * Defines
49 *-----------------------------------------------------------------------------*/
4037ed3b 50#ifndef TRUE
74357114 51#define TRUE 1
4037ed3b
SR		 52#endif
53#ifndef FALSE
74357114 54#define FALSE 0
4037ed3b
SR		 55#endif
56
57#define SDRAM_DDR1 1
58#define SDRAM_DDR2 2
59#define SDRAM_NONE 0
60
61#define MAXDIMMS 2
62#define MAXRANKS 4
63#define MAXBXCF 4
64#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
65
66#define ONE_BILLION 1000000000
67
68#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
69
ba58e4c9
SR		 70#define CMD_NOP (7 << 19)
71#define CMD_PRECHARGE (2 << 19)
72#define CMD_REFRESH (1 << 19)
73#define CMD_EMR (0 << 19)
74#define CMD_READ (5 << 19)
75#define CMD_WRITE (4 << 19)
76
77#define SELECT_MR (0 << 16)
78#define SELECT_EMR (1 << 16)
79#define SELECT_EMR2 (2 << 16)
80#define SELECT_EMR3 (3 << 16)
81
82/* MR */
83#define DLL_RESET 0x00000100
84
85#define WRITE_RECOV_2 (1 << 9)
86#define WRITE_RECOV_3 (2 << 9)
87#define WRITE_RECOV_4 (3 << 9)
88#define WRITE_RECOV_5 (4 << 9)
89#define WRITE_RECOV_6 (5 << 9)
90
91#define BURST_LEN_4 0x00000002
92
93/* EMR */
94#define ODT_0_OHM 0x00000000
95#define ODT_50_OHM 0x00000044
96#define ODT_75_OHM 0x00000004
97#define ODT_150_OHM 0x00000040
98
99#define ODS_FULL 0x00000000
100#define ODS_REDUCED 0x00000002
101
102/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
103#define ODT_EB0R (0x80000000 >> 8)
104#define ODT_EB0W (0x80000000 >> 7)
105#define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
106#define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
107#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
4037ed3b 108
4037ed3b
SR		 109/* Defines for the Read Cycle Delay test */
110#define NUMMEMTESTS 8
111#define NUMMEMWORDS 8
112
ba58e4c9
SR		 113#define CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
114
115/*
116 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
117 * region. Right now the cache should still be disabled in U-Boot because of the
118 * EMAC driver, that need it's buffer descriptor to be located in non cached
119 * memory.
120 *
121 * If at some time this restriction doesn't apply anymore, just define
122 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
123 * everything correctly.
124 */
125#ifdef CFG_ENABLE_SDRAM_CACHE
126#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
127#else
128#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
129#endif
130
4037ed3b
SR		 131/* Private Structure Definitions */
132
133/* enum only to ease code for cas latency setting */
134typedef enum ddr_cas_id {
135 DDR_CAS_2 = 20,
136 DDR_CAS_2_5 = 25,
137 DDR_CAS_3 = 30,
138 DDR_CAS_4 = 40,
139 DDR_CAS_5 = 50
140} ddr_cas_id_t;
141
142/*-----------------------------------------------------------------------------+
143 * Prototypes
144 *-----------------------------------------------------------------------------*/
145static unsigned long sdram_memsize(void);
ba58e4c9 146void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
4037ed3b
SR		 147static void get_spd_info(unsigned long *dimm_populated,
148 unsigned char *iic0_dimm_addr,
149 unsigned long num_dimm_banks);
150static void check_mem_type(unsigned long *dimm_populated,
151 unsigned char *iic0_dimm_addr,
152 unsigned long num_dimm_banks);
153static void check_frequency(unsigned long *dimm_populated,
154 unsigned char *iic0_dimm_addr,
155 unsigned long num_dimm_banks);
156static void check_rank_number(unsigned long *dimm_populated,
157 unsigned char *iic0_dimm_addr,
158 unsigned long num_dimm_banks);
159static void check_voltage_type(unsigned long *dimm_populated,
160 unsigned char *iic0_dimm_addr,
161 unsigned long num_dimm_banks);
162static void program_memory_queue(unsigned long *dimm_populated,
163 unsigned char *iic0_dimm_addr,
164 unsigned long num_dimm_banks);
165static void program_codt(unsigned long *dimm_populated,
166 unsigned char *iic0_dimm_addr,
167 unsigned long num_dimm_banks);
168static void program_mode(unsigned long *dimm_populated,
169 unsigned char *iic0_dimm_addr,
170 unsigned long num_dimm_banks,
ad5bb451
WD		 171 ddr_cas_id_t *selected_cas,
172 int *write_recovery);
4037ed3b
SR		 173static void program_tr(unsigned long *dimm_populated,
174 unsigned char *iic0_dimm_addr,
175 unsigned long num_dimm_banks);
176static void program_rtr(unsigned long *dimm_populated,
177 unsigned char *iic0_dimm_addr,
178 unsigned long num_dimm_banks);
179static void program_bxcf(unsigned long *dimm_populated,
180 unsigned char *iic0_dimm_addr,
181 unsigned long num_dimm_banks);
182static void program_copt1(unsigned long *dimm_populated,
183 unsigned char *iic0_dimm_addr,
184 unsigned long num_dimm_banks);
185static void program_initplr(unsigned long *dimm_populated,
186 unsigned char *iic0_dimm_addr,
187 unsigned long num_dimm_banks,
ad5bb451 188 ddr_cas_id_t selected_cas,
ba58e4c9 189 int write_recovery);
4037ed3b
SR		 190static unsigned long is_ecc_enabled(void);
191static void program_ecc(unsigned long *dimm_populated,
192 unsigned char *iic0_dimm_addr,
ba58e4c9
SR		 193 unsigned long num_dimm_banks,
194 unsigned long tlb_word2_i_value);
4037ed3b 195static void program_ecc_addr(unsigned long start_address,
ba58e4c9
SR		 196 unsigned long num_bytes,
197 unsigned long tlb_word2_i_value);
198static void program_DQS_calibration(unsigned long *dimm_populated,
199 unsigned char *iic0_dimm_addr,
200 unsigned long num_dimm_banks);
4037ed3b 201#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
74357114 202static void test(void);
4037ed3b 203#else
74357114 204static void DQS_calibration_process(void);
4037ed3b 205#endif
ba58e4c9
SR		 206#if defined(DEBUG)
207static void ppc440sp_sdram_register_dump(void);
208#endif
209int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
210void dcbz_area(u32 start_address, u32 num_bytes);
211void dflush(void);
4037ed3b
SR		 212
213static u32 mfdcr_any(u32 dcr)
214{
215 u32 val;
216
217 switch (dcr) {
218 case SDRAM_R0BAS + 0:
219 val = mfdcr(SDRAM_R0BAS + 0);
220 break;
221 case SDRAM_R0BAS + 1:
222 val = mfdcr(SDRAM_R0BAS + 1);
223 break;
224 case SDRAM_R0BAS + 2:
225 val = mfdcr(SDRAM_R0BAS + 2);
226 break;
227 case SDRAM_R0BAS + 3:
228 val = mfdcr(SDRAM_R0BAS + 3);
229 break;
230 default:
231 printf("DCR %d not defined in case statement!!!\n", dcr);
232 val = 0; /* just to satisfy the compiler */
233 }
234
235 return val;
236}
237
238static void mtdcr_any(u32 dcr, u32 val)
239{
240 switch (dcr) {
241 case SDRAM_R0BAS + 0:
242 mtdcr(SDRAM_R0BAS + 0, val);
243 break;
244 case SDRAM_R0BAS + 1:
245 mtdcr(SDRAM_R0BAS + 1, val);
246 break;
247 case SDRAM_R0BAS + 2:
248 mtdcr(SDRAM_R0BAS + 2, val);
249 break;
250 case SDRAM_R0BAS + 3:
251 mtdcr(SDRAM_R0BAS + 3, val);
252 break;
253 default:
254 printf("DCR %d not defined in case statement!!!\n", dcr);
255 }
256}
257
258static void wait_ddr_idle(void)
259{
260 u32 val;
261
262 do {
263 mfsdram(SDRAM_MCSTAT, val);
264 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
265}
266
267static unsigned char spd_read(uchar chip, uint addr)
268{
269 unsigned char data[2];
270
271 if (i2c_probe(chip) == 0)
272 if (i2c_read(chip, addr, 1, data, 1) == 0)
273 return data[0];
274
275 return 0;
276}
277
278/*-----------------------------------------------------------------------------+
279 * sdram_memsize
280 *-----------------------------------------------------------------------------*/
281static unsigned long sdram_memsize(void)
282{
283 unsigned long mem_size;
284 unsigned long mcopt2;
285 unsigned long mcstat;
286 unsigned long mb0cf;
287 unsigned long sdsz;
288 unsigned long i;
289
290 mem_size = 0;
291
292 mfsdram(SDRAM_MCOPT2, mcopt2);
293 mfsdram(SDRAM_MCSTAT, mcstat);
294
295 /* DDR controller must be enabled and not in self-refresh. */
296 /* Otherwise memsize is zero. */
297 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
298 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
299 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
300 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
ba58e4c9 301 for (i = 0; i < MAXBXCF; i++) {
4037ed3b
SR		 302 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
303 /* Banks enabled */
304 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
305 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
306
307 switch(sdsz) {
308 case SDRAM_RXBAS_SDSZ_8:
309 mem_size+=8;
310 break;
311 case SDRAM_RXBAS_SDSZ_16:
312 mem_size+=16;
313 break;
314 case SDRAM_RXBAS_SDSZ_32:
315 mem_size+=32;
316 break;
317 case SDRAM_RXBAS_SDSZ_64:
318 mem_size+=64;
319 break;
320 case SDRAM_RXBAS_SDSZ_128:
321 mem_size+=128;
322 break;
323 case SDRAM_RXBAS_SDSZ_256:
324 mem_size+=256;
325 break;
326 case SDRAM_RXBAS_SDSZ_512:
327 mem_size+=512;
328 break;
329 case SDRAM_RXBAS_SDSZ_1024:
330 mem_size+=1024;
331 break;
332 case SDRAM_RXBAS_SDSZ_2048:
333 mem_size+=2048;
334 break;
335 case SDRAM_RXBAS_SDSZ_4096:
336 mem_size+=4096;
337 break;
338 default:
339 mem_size=0;
340 break;
341 }
342 }
343 }
344 }
345
346 mem_size *= 1024 * 1024;
347 return(mem_size);
348}
349
350/*-----------------------------------------------------------------------------+
351 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
352 * Note: This routine runs from flash with a stack set up in the chip's
353 * sram space. It is important that the routine does not require .sbss, .bss or
354 * .data sections. It also cannot call routines that require these sections.
355 *-----------------------------------------------------------------------------*/
356/*-----------------------------------------------------------------------------
74357114 357 * Function: initdram
4037ed3b 358 * Description: Configures SDRAM memory banks for DDR operation.
74357114
WD		 359 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
360 * via the IIC bus and then configures the DDR SDRAM memory
361 * banks appropriately. If Auto Memory Configuration is
362 * not used, it is assumed that no DIMM is plugged
4037ed3b
SR		 363 *-----------------------------------------------------------------------------*/
364long int initdram(int board_type)
365{
ba58e4c9 366 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
4037ed3b
SR		 367 unsigned char spd0[MAX_SPD_BYTES];
368 unsigned char spd1[MAX_SPD_BYTES];
369 unsigned char *dimm_spd[MAXDIMMS];
370 unsigned long dimm_populated[MAXDIMMS];
4037ed3b
SR		 371 unsigned long num_dimm_banks; /* on board dimm banks */
372 unsigned long val;
373 ddr_cas_id_t selected_cas;
ba58e4c9 374 int write_recovery;
4037ed3b
SR		 375 unsigned long dram_size = 0;
376
377 num_dimm_banks = sizeof(iic0_dimm_addr);
378
379 /*------------------------------------------------------------------
380 * Set up an array of SPD matrixes.
381 *-----------------------------------------------------------------*/
382 dimm_spd[0] = spd0;
383 dimm_spd[1] = spd1;
384
4037ed3b
SR		 385 /*------------------------------------------------------------------
386 * Reset the DDR-SDRAM controller.
387 *-----------------------------------------------------------------*/
ba58e4c9 388 mtsdr(SDR0_SRST, (0x80000000 >> 10));
4037ed3b
SR		 389 mtsdr(SDR0_SRST, 0x00000000);
390
391 /*
392 * Make sure I2C controller is initialized
393 * before continuing.
394 */
395
396 /* switch to correct I2C bus */
397 I2C_SET_BUS(CFG_SPD_BUS_NUM);
398 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
399
400 /*------------------------------------------------------------------
401 * Clear out the serial presence detect buffers.
402 * Perform IIC reads from the dimm. Fill in the spds.
403 * Check to see if the dimm slots are populated
404 *-----------------------------------------------------------------*/
405 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
406
407 /*------------------------------------------------------------------
408 * Check the memory type for the dimms plugged.
409 *-----------------------------------------------------------------*/
410 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
411
412 /*------------------------------------------------------------------
413 * Check the frequency supported for the dimms plugged.
414 *-----------------------------------------------------------------*/
415 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
416
417 /*------------------------------------------------------------------
418 * Check the total rank number.
419 *-----------------------------------------------------------------*/
420 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
421
422 /*------------------------------------------------------------------
423 * Check the voltage type for the dimms plugged.
424 *-----------------------------------------------------------------*/
425 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
426
427 /*------------------------------------------------------------------
428 * Program SDRAM controller options 2 register
429 * Except Enabling of the memory controller.
430 *-----------------------------------------------------------------*/
431 mfsdram(SDRAM_MCOPT2, val);
432 mtsdram(SDRAM_MCOPT2,
433 (val &
434 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
435 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
436 SDRAM_MCOPT2_ISIE_MASK))
437 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
438 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
439 SDRAM_MCOPT2_ISIE_ENABLE));
440
441 /*------------------------------------------------------------------
442 * Program SDRAM controller options 1 register
443 * Note: Does not enable the memory controller.
444 *-----------------------------------------------------------------*/
445 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
446
447 /*------------------------------------------------------------------
448 * Set the SDRAM Controller On Die Termination Register
449 *-----------------------------------------------------------------*/
450 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
451
452 /*------------------------------------------------------------------
453 * Program SDRAM refresh register.
454 *-----------------------------------------------------------------*/
455 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
456
457 /*------------------------------------------------------------------
458 * Program SDRAM mode register.
459 *-----------------------------------------------------------------*/
ba58e4c9
SR		 460 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
461 &selected_cas, &write_recovery);
4037ed3b
SR		 462
463 /*------------------------------------------------------------------
464 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
465 *-----------------------------------------------------------------*/
466 mfsdram(SDRAM_WRDTR, val);
467 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
468 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
469
470 /*------------------------------------------------------------------
471 * Set the SDRAM Clock Timing Register
472 *-----------------------------------------------------------------*/
473 mfsdram(SDRAM_CLKTR, val);
474 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
475
476 /*------------------------------------------------------------------
477 * Program the BxCF registers.
478 *-----------------------------------------------------------------*/
479 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
480
481 /*------------------------------------------------------------------
482 * Program SDRAM timing registers.
483 *-----------------------------------------------------------------*/
484 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
485
486 /*------------------------------------------------------------------
487 * Set the Extended Mode register
488 *-----------------------------------------------------------------*/
489 mfsdram(SDRAM_MEMODE, val);
490 mtsdram(SDRAM_MEMODE,
491 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
492 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
493 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
494 | SDRAM_MEMODE_RTT_75OHM | SDRAM_MEMODE_DQS_ENABLE));
495
496 /*------------------------------------------------------------------
497 * Program Initialization preload registers.
498 *-----------------------------------------------------------------*/
499 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
ba58e4c9 500 selected_cas, write_recovery);
4037ed3b
SR		 501
502 /*------------------------------------------------------------------
503 * Delay to ensure 200usec have elapsed since reset.
504 *-----------------------------------------------------------------*/
505 udelay(400);
506
507 /*------------------------------------------------------------------
508 * Set the memory queue core base addr.
509 *-----------------------------------------------------------------*/
510 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
511
512 /*------------------------------------------------------------------
513 * Program SDRAM controller options 2 register
514 * Enable the memory controller.
515 *-----------------------------------------------------------------*/
516 mfsdram(SDRAM_MCOPT2, val);
517 mtsdram(SDRAM_MCOPT2,
518 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
519 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
520 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
521
522 /*------------------------------------------------------------------
523 * Wait for SDRAM_CFG0_DC_EN to complete.
524 *-----------------------------------------------------------------*/
525 do {
526 mfsdram(SDRAM_MCSTAT, val);
527 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
528
529 /* get installed memory size */
530 dram_size = sdram_memsize();
531
532 /* and program tlb entries for this size (dynamic) */
ba58e4c9 533 program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
4037ed3b 534
4037ed3b 535 /*------------------------------------------------------------------
ba58e4c9 536 * DQS calibration.
4037ed3b 537 *-----------------------------------------------------------------*/
ba58e4c9 538 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
4037ed3b
SR		 539
540 /*------------------------------------------------------------------
ba58e4c9 541 * If ecc is enabled, initialize the parity bits.
4037ed3b 542 *-----------------------------------------------------------------*/
ba58e4c9 543 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
4037ed3b
SR		 544
545#ifdef DEBUG
546 ppc440sp_sdram_register_dump();
547#endif
548
549 return dram_size;
550}
551
552static void get_spd_info(unsigned long *dimm_populated,
553 unsigned char *iic0_dimm_addr,
554 unsigned long num_dimm_banks)
555{
556 unsigned long dimm_num;
557 unsigned long dimm_found;
558 unsigned char num_of_bytes;
559 unsigned char total_size;
560
561 dimm_found = FALSE;
562 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
563 num_of_bytes = 0;
564 total_size = 0;
565
566 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
567 debug("\nspd_read(0x%x) returned %d\n",
568 iic0_dimm_addr[dimm_num], num_of_bytes);
569 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
570 debug("spd_read(0x%x) returned %d\n",
571 iic0_dimm_addr[dimm_num], total_size);
572
573 if ((num_of_bytes != 0) && (total_size != 0)) {
574 dimm_populated[dimm_num] = TRUE;
575 dimm_found = TRUE;
576 debug("DIMM slot %lu: populated\n", dimm_num);
577 } else {
578 dimm_populated[dimm_num] = FALSE;
579 debug("DIMM slot %lu: Not populated\n", dimm_num);
580 }
581 }
582
583 if (dimm_found == FALSE) {
584 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
585 hang();
586 }
587}
588
589#ifdef CONFIG_ADD_RAM_INFO
590void board_add_ram_info(int use_default)
591{
74357114
WD		 592 if (is_ecc_enabled())
593 puts(" (ECC enabled)");
594 else
595 puts(" (ECC not enabled)");
4037ed3b
SR		 596}
597#endif
598
599/*------------------------------------------------------------------
600 * For the memory DIMMs installed, this routine verifies that they
601 * really are DDR specific DIMMs.
602 *-----------------------------------------------------------------*/
603static void check_mem_type(unsigned long *dimm_populated,
604 unsigned char *iic0_dimm_addr,
605 unsigned long num_dimm_banks)
606{
607 unsigned long dimm_num;
608 unsigned long dimm_type;
609
610 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
611 if (dimm_populated[dimm_num] == TRUE) {
612 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
613 switch (dimm_type) {
614 case 1:
615 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
616 "slot %d.\n", (unsigned int)dimm_num);
617 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
618 printf("Replace the DIMM module with a supported DIMM.\n\n");
619 hang();
620 break;
621 case 2:
622 printf("ERROR: EDO DIMM detected in slot %d.\n",
623 (unsigned int)dimm_num);
624 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
625 printf("Replace the DIMM module with a supported DIMM.\n\n");
626 hang();
627 break;
628 case 3:
629 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
630 (unsigned int)dimm_num);
631 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
632 printf("Replace the DIMM module with a supported DIMM.\n\n");
633 hang();
634 break;
635 case 4:
636 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
637 (unsigned int)dimm_num);
638 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
639 printf("Replace the DIMM module with a supported DIMM.\n\n");
640 hang();
641 break;
642 case 5:
643 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
644 (unsigned int)dimm_num);
645 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
646 printf("Replace the DIMM module with a supported DIMM.\n\n");
647 hang();
648 break;
649 case 6:
650 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
651 (unsigned int)dimm_num);
652 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
653 printf("Replace the DIMM module with a supported DIMM.\n\n");
654 hang();
655 break;
656 case 7:
657 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
658 dimm_populated[dimm_num] = SDRAM_DDR1;
659 break;
660 case 8:
661 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
662 dimm_populated[dimm_num] = SDRAM_DDR2;
663 break;
664 default:
665 printf("ERROR: Unknown DIMM detected in slot %d.\n",
666 (unsigned int)dimm_num);
667 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
668 printf("Replace the DIMM module with a supported DIMM.\n\n");
669 hang();
670 break;
671 }
672 }
673 }
674 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
675 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
676 && (dimm_populated[dimm_num] != SDRAM_NONE)
677 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
678 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
679 hang();
680 }
681 }
682}
683
684/*------------------------------------------------------------------
685 * For the memory DIMMs installed, this routine verifies that
686 * frequency previously calculated is supported.
687 *-----------------------------------------------------------------*/
688static void check_frequency(unsigned long *dimm_populated,
689 unsigned char *iic0_dimm_addr,
690 unsigned long num_dimm_banks)
691{
692 unsigned long dimm_num;
693 unsigned long tcyc_reg;
694 unsigned long cycle_time;
695 unsigned long calc_cycle_time;
696 unsigned long sdram_freq;
697 unsigned long sdr_ddrpll;
698 PPC440_SYS_INFO board_cfg;
699
700 /*------------------------------------------------------------------
701 * Get the board configuration info.
702 *-----------------------------------------------------------------*/
703 get_sys_info(&board_cfg);
704
705 mfsdr(sdr_ddr0, sdr_ddrpll);
706 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
707
708 /*
709 * calc_cycle_time is calculated from DDR frequency set by board/chip
710 * and is expressed in multiple of 10 picoseconds
711 * to match the way DIMM cycle time is calculated below.
712 */
713 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
714
715 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
716 if (dimm_populated[dimm_num] != SDRAM_NONE) {
717 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
718 /*
719 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
720 * the higher order nibble (bits 4-7) designates the cycle time
721 * to a granularity of 1ns;
722 * the value presented by the lower order nibble (bits 0-3)
723 * has a granularity of .1ns and is added to the value designated
724 * by the higher nibble. In addition, four lines of the lower order
725 * nibble are assigned to support +.25,+.33, +.66 and +.75.
726 */
727 /* Convert from hex to decimal */
728 if ((tcyc_reg & 0x0F) == 0x0D)
729 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
730 else if ((tcyc_reg & 0x0F) == 0x0C)
731 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
732 else if ((tcyc_reg & 0x0F) == 0x0B)
733 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
734 else if ((tcyc_reg & 0x0F) == 0x0A)
735 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
736 else
737 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
738 ((tcyc_reg & 0x0F)*10);
739
740 if (cycle_time > (calc_cycle_time + 10)) {
741 /*
742 * the provided sdram cycle_time is too small
743 * for the available DIMM cycle_time.
744 * The additionnal 100ps is here to accept a small incertainty.
745 */
746 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
747 "slot %d \n while calculated cycle time is %d ps.\n",
748 (unsigned int)(cycle_time*10),
749 (unsigned int)dimm_num,
750 (unsigned int)(calc_cycle_time*10));
751 printf("Replace the DIMM, or change DDR frequency via "
752 "strapping bits.\n\n");
753 hang();
754 }
755 }
756 }
757}
758
759/*------------------------------------------------------------------
760 * For the memory DIMMs installed, this routine verifies two
761 * ranks/banks maximum are availables.
762 *-----------------------------------------------------------------*/
763static void check_rank_number(unsigned long *dimm_populated,
764 unsigned char *iic0_dimm_addr,
765 unsigned long num_dimm_banks)
766{
767 unsigned long dimm_num;
768 unsigned long dimm_rank;
769 unsigned long total_rank = 0;
770
771 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
772 if (dimm_populated[dimm_num] != SDRAM_NONE) {
773 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
774 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
775 dimm_rank = (dimm_rank & 0x0F) +1;
776 else
777 dimm_rank = dimm_rank & 0x0F;
778
779
780 if (dimm_rank > MAXRANKS) {
781 printf("ERROR: DRAM DIMM detected with %d ranks in "
782 "slot %d is not supported.\n", dimm_rank, dimm_num);
783 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
784 printf("Replace the DIMM module with a supported DIMM.\n\n");
785 hang();
786 } else
787 total_rank += dimm_rank;
788 }
789 if (total_rank > MAXRANKS) {
790 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
791 "for all slots.\n", (unsigned int)total_rank);
792 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
793 printf("Remove one of the DIMM modules.\n\n");
794 hang();
795 }
796 }
797}
798
799/*------------------------------------------------------------------
800 * only support 2.5V modules.
801 * This routine verifies this.
802 *-----------------------------------------------------------------*/
803static void check_voltage_type(unsigned long *dimm_populated,
804 unsigned char *iic0_dimm_addr,
805 unsigned long num_dimm_banks)
806{
807 unsigned long dimm_num;
808 unsigned long voltage_type;
809
810 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
811 if (dimm_populated[dimm_num] != SDRAM_NONE) {
812 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
813 switch (voltage_type) {
814 case 0x00:
815 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
816 printf("This DIMM is 5.0 Volt/TTL.\n");
817 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
818 (unsigned int)dimm_num);
819 hang();
820 break;
821 case 0x01:
822 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
823 printf("This DIMM is LVTTL.\n");
824 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
825 (unsigned int)dimm_num);
826 hang();
827 break;
828 case 0x02:
829 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
830 printf("This DIMM is 1.5 Volt.\n");
831 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
832 (unsigned int)dimm_num);
833 hang();
834 break;
835 case 0x03:
836 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
837 printf("This DIMM is 3.3 Volt/TTL.\n");
838 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
839 (unsigned int)dimm_num);
840 hang();
841 break;
842 case 0x04:
843 /* 2.5 Voltage only for DDR1 */
844 break;
845 case 0x05:
846 /* 1.8 Voltage only for DDR2 */
847 break;
848 default:
849 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
850 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
851 (unsigned int)dimm_num);
852 hang();
853 break;
854 }
855 }
856 }
857}
858
859/*-----------------------------------------------------------------------------+
860 * program_copt1.
861 *-----------------------------------------------------------------------------*/
862static void program_copt1(unsigned long *dimm_populated,
863 unsigned char *iic0_dimm_addr,
864 unsigned long num_dimm_banks)
865{
866 unsigned long dimm_num;
867 unsigned long mcopt1;
868 unsigned long ecc_enabled;
869 unsigned long ecc = 0;
870 unsigned long data_width = 0;
871 unsigned long dimm_32bit;
872 unsigned long dimm_64bit;
873 unsigned long registered = 0;
874 unsigned long attribute = 0;
875 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
876 unsigned long bankcount;
877 unsigned long ddrtype;
878 unsigned long val;
879
880 ecc_enabled = TRUE;
881 dimm_32bit = FALSE;
882 dimm_64bit = FALSE;
883 buf0 = FALSE;
884 buf1 = FALSE;
885
886 /*------------------------------------------------------------------
887 * Set memory controller options reg 1, SDRAM_MCOPT1.
888 *-----------------------------------------------------------------*/
889 mfsdram(SDRAM_MCOPT1, val);
890 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
891 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
892 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
893 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
894 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
895 SDRAM_MCOPT1_DREF_MASK);
896
897 mcopt1 |= SDRAM_MCOPT1_QDEP;
898 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
899 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
900 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
901 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
902 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
903
904 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
905 if (dimm_populated[dimm_num] != SDRAM_NONE) {
906 /* test ecc support */
907 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
908 if (ecc != 0x02) /* ecc not supported */
909 ecc_enabled = FALSE;
910
911 /* test bank count */
912 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
913 if (bankcount == 0x04) /* bank count = 4 */
914 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
915 else /* bank count = 8 */
916 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
917
918 /* test DDR type */
919 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
920 /* test for buffered/unbuffered, registered, differential clocks */
921 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
922 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
923
924 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
925 if (dimm_num == 0) {
926 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
927 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
928 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
929 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
930 if (registered == 1) { /* DDR2 always buffered */
931 /* TODO: what about above comments ? */
932 mcopt1 |= SDRAM_MCOPT1_RDEN;
933 buf0 = TRUE;
934 } else {
935 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
936 if ((attribute & 0x02) == 0x00) {
937 /* buffered not supported */
938 buf0 = FALSE;
939 } else {
940 mcopt1 |= SDRAM_MCOPT1_RDEN;
941 buf0 = TRUE;
942 }
943 }
944 }
945 else if (dimm_num == 1) {
946 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
947 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
948 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
949 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
950 if (registered == 1) {
951 /* DDR2 always buffered */
952 mcopt1 |= SDRAM_MCOPT1_RDEN;
953 buf1 = TRUE;
954 } else {
955 if ((attribute & 0x02) == 0x00) {
956 /* buffered not supported */
957 buf1 = FALSE;
958 } else {
959 mcopt1 |= SDRAM_MCOPT1_RDEN;
960 buf1 = TRUE;
961 }
962 }
963 }
964
965 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
966 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
967 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
968
969 switch (data_width) {
970 case 72:
971 case 64:
972 dimm_64bit = TRUE;
973 break;
974 case 40:
975 case 32:
976 dimm_32bit = TRUE;
977 break;
978 default:
979 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
980 data_width);
981 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
982 break;
983 }
984 }
985 }
986
987 /* verify matching properties */
988 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
989 if (buf0 != buf1) {
990 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
991 hang();
992 }
993 }
994
995 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
996 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
997 hang();
998 }
999 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1000 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1001 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1002 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1003 } else {
1004 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1005 hang();
1006 }
1007
1008 if (ecc_enabled == TRUE)
1009 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1010 else
1011 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1012
1013 mtsdram(SDRAM_MCOPT1, mcopt1);
1014}
1015
1016/*-----------------------------------------------------------------------------+
1017 * program_codt.
1018 *-----------------------------------------------------------------------------*/
1019static void program_codt(unsigned long *dimm_populated,
1020 unsigned char *iic0_dimm_addr,
1021 unsigned long num_dimm_banks)
1022{
1023 unsigned long codt;
1024 unsigned long modt0 = 0;
1025 unsigned long modt1 = 0;
1026 unsigned long modt2 = 0;
1027 unsigned long modt3 = 0;
1028 unsigned char dimm_num;
1029 unsigned char dimm_rank;
1030 unsigned char total_rank = 0;
1031 unsigned char total_dimm = 0;
1032 unsigned char dimm_type = 0;
1033 unsigned char firstSlot = 0;
1034
1035 /*------------------------------------------------------------------
1036 * Set the SDRAM Controller On Die Termination Register
1037 *-----------------------------------------------------------------*/
1038 mfsdram(SDRAM_CODT, codt);
1039 codt |= (SDRAM_CODT_IO_NMODE
1040 & (~SDRAM_CODT_DQS_SINGLE_END
1041 & ~SDRAM_CODT_CKSE_SINGLE_END
1042 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1043 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1044
1045 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1046 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1047 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1048 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1049 dimm_rank = (dimm_rank & 0x0F) + 1;
1050 dimm_type = SDRAM_DDR2;
1051 } else {
1052 dimm_rank = dimm_rank & 0x0F;
1053 dimm_type = SDRAM_DDR1;
1054 }
1055
ba58e4c9
SR		 1056 total_rank += dimm_rank;
1057 total_dimm++;
4037ed3b
SR		 1058 if ((dimm_num == 0) && (total_dimm == 1))
1059 firstSlot = TRUE;
1060 else
1061 firstSlot = FALSE;
1062 }
1063 }
1064 if (dimm_type == SDRAM_DDR2) {
1065 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1066 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1067 if (total_rank == 1) {
ba58e4c9
SR		 1068 codt |= CALC_ODT_R(0);
1069 modt0 = CALC_ODT_W(0);
4037ed3b
SR		 1070 modt1 = 0x00000000;
1071 modt2 = 0x00000000;
1072 modt3 = 0x00000000;
1073 }
1074 if (total_rank == 2) {
ba58e4c9
SR		 1075 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1076 modt0 = CALC_ODT_W(0);
1077 modt1 = CALC_ODT_W(0);
4037ed3b
SR		 1078 modt2 = 0x00000000;
1079 modt3 = 0x00000000;
1080 }
ba58e4c9 1081 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
4037ed3b 1082 if (total_rank == 1) {
ba58e4c9
SR		 1083 codt |= CALC_ODT_R(2);
1084 modt0 = 0x00000000;
4037ed3b 1085 modt1 = 0x00000000;
ba58e4c9 1086 modt2 = CALC_ODT_W(2);
4037ed3b
SR		 1087 modt3 = 0x00000000;
1088 }
1089 if (total_rank == 2) {
ba58e4c9
SR		 1090 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1091 modt0 = 0x00000000;
1092 modt1 = 0x00000000;
1093 modt2 = CALC_ODT_W(2);
1094 modt3 = CALC_ODT_W(2);
4037ed3b
SR		 1095 }
1096 }
1097 if (total_dimm == 2) {
1098 if (total_rank == 2) {
ba58e4c9
SR		 1099 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1100 modt0 = CALC_ODT_RW(2);
4037ed3b 1101 modt1 = 0x00000000;
ba58e4c9 1102 modt2 = CALC_ODT_RW(0);
4037ed3b
SR		 1103 modt3 = 0x00000000;
1104 }
1105 if (total_rank == 4) {
ba58e4c9
SR		 1106 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
1107 modt0 = CALC_ODT_RW(2);
1108 modt1 = 0x00000000;
1109 modt2 = CALC_ODT_RW(0);
1110 modt3 = 0x00000000;
4037ed3b
SR		 1111 }
1112 }
1113 } else {
1114 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1115 modt0 = 0x00000000;
1116 modt1 = 0x00000000;
1117 modt2 = 0x00000000;
1118 modt3 = 0x00000000;
1119
1120 if (total_dimm == 1) {
1121 if (total_rank == 1)
1122 codt |= 0x00800000;
1123 if (total_rank == 2)
1124 codt |= 0x02800000;
1125 }
1126 if (total_dimm == 2) {
1127 if (total_rank == 2)
1128 codt |= 0x08800000;
1129 if (total_rank == 4)
1130 codt |= 0x2a800000;
1131 }
1132 }
1133
1134 debug("nb of dimm %d\n", total_dimm);
1135 debug("nb of rank %d\n", total_rank);
1136 if (total_dimm == 1)
1137 debug("dimm in slot %d\n", firstSlot);
1138
1139 mtsdram(SDRAM_CODT, codt);
1140 mtsdram(SDRAM_MODT0, modt0);
1141 mtsdram(SDRAM_MODT1, modt1);
1142 mtsdram(SDRAM_MODT2, modt2);
1143 mtsdram(SDRAM_MODT3, modt3);
1144}
1145
1146/*-----------------------------------------------------------------------------+
1147 * program_initplr.
1148 *-----------------------------------------------------------------------------*/
1149static void program_initplr(unsigned long *dimm_populated,
1150 unsigned char *iic0_dimm_addr,
1151 unsigned long num_dimm_banks,
ad5bb451 1152 ddr_cas_id_t selected_cas,
ba58e4c9 1153 int write_recovery)
4037ed3b 1154{
ba58e4c9
SR		 1155 u32 cas = 0;
1156 u32 odt = 0;
1157 u32 ods = 0;
1158 u32 mr;
1159 u32 wr;
1160 u32 emr;
1161 u32 emr2;
1162 u32 emr3;
1163 int dimm_num;
1164 int total_dimm = 0;
4037ed3b
SR		 1165
1166 /******************************************************
1167 ** Assumption: if more than one DIMM, all DIMMs are the same
74357114 1168 ** as already checked in check_memory_type
4037ed3b
SR		 1169 ******************************************************/
1170
1171 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1172 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1173 mtsdram(SDRAM_INITPLR1, 0x81900400);
1174 mtsdram(SDRAM_INITPLR2, 0x81810000);
1175 mtsdram(SDRAM_INITPLR3, 0xff800162);
1176 mtsdram(SDRAM_INITPLR4, 0x81900400);
1177 mtsdram(SDRAM_INITPLR5, 0x86080000);
1178 mtsdram(SDRAM_INITPLR6, 0x86080000);
1179 mtsdram(SDRAM_INITPLR7, 0x81000062);
1180 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1181 switch (selected_cas) {
4037ed3b 1182 case DDR_CAS_3:
ba58e4c9 1183 cas = 3 << 4;
4037ed3b
SR		 1184 break;
1185 case DDR_CAS_4:
ba58e4c9 1186 cas = 4 << 4;
4037ed3b
SR		 1187 break;
1188 case DDR_CAS_5:
ba58e4c9 1189 cas = 5 << 4;
4037ed3b
SR		 1190 break;
1191 default:
ba58e4c9 1192 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
4037ed3b
SR		 1193 hang();
1194 break;
1195 }
1196
ba58e4c9
SR		 1197#if 0
1198 /*
1199 * ToDo - Still a problem with the write recovery:
1200 * On the Corsair CM2X512-5400C4 module, setting write recovery
1201 * in the INITPLR reg to the value calculated in program_mode()
1202 * results in not correctly working DDR2 memory (crash after
1203 * relocation).
1204 *
1205 * So for now, set the write recovery to 3. This seems to work
1206 * on the Corair module too.
1207 *
1208 * 2007-03-01, sr
1209 */
1210 switch (write_recovery) {
1211 case 3:
1212 wr = WRITE_RECOV_3;
1213 break;
1214 case 4:
1215 wr = WRITE_RECOV_4;
1216 break;
1217 case 5:
1218 wr = WRITE_RECOV_5;
1219 break;
1220 case 6:
1221 wr = WRITE_RECOV_6;
1222 break;
1223 default:
1224 printf("ERROR: write recovery not support (%d)", write_recovery);
1225 hang();
1226 break;
1227 }
1228#else
1229 wr = WRITE_RECOV_3; /* test-only, see description above */
1230#endif
1231
1232 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1233 if (dimm_populated[dimm_num] != SDRAM_NONE)
1234 total_dimm++;
1235 if (total_dimm == 1) {
1236 odt = ODT_150_OHM;
1237 ods = ODS_FULL;
1238 } else if (total_dimm == 2) {
1239 odt = ODT_75_OHM;
1240 ods = ODS_REDUCED;
1241 } else {
1242 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1243 hang();
1244 }
1245
1246 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1247 emr = CMD_EMR | SELECT_EMR | odt | ods;
1248 emr2 = CMD_EMR | SELECT_EMR2;
1249 emr3 = CMD_EMR | SELECT_EMR3;
1250 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1251 udelay(1000);
1252 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1253 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1254 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1255 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1256 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1257 udelay(1000);
1258 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1259 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1260 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1261 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1262 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1263 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1264 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1265 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
4037ed3b
SR		 1266 } else {
1267 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1268 hang();
1269 }
1270}
1271
1272/*------------------------------------------------------------------
1273 * This routine programs the SDRAM_MMODE register.
1274 * the selected_cas is an output parameter, that will be passed
1275 * by caller to call the above program_initplr( )
1276 *-----------------------------------------------------------------*/
1277static void program_mode(unsigned long *dimm_populated,
1278 unsigned char *iic0_dimm_addr,
1279 unsigned long num_dimm_banks,
ba58e4c9
SR		 1280 ddr_cas_id_t *selected_cas,
1281 int *write_recovery)
4037ed3b
SR		 1282{
1283 unsigned long dimm_num;
1284 unsigned long sdram_ddr1;
1285 unsigned long t_wr_ns;
1286 unsigned long t_wr_clk;
1287 unsigned long cas_bit;
1288 unsigned long cas_index;
1289 unsigned long sdram_freq;
1290 unsigned long ddr_check;
1291 unsigned long mmode;
1292 unsigned long tcyc_reg;
1293 unsigned long cycle_2_0_clk;
1294 unsigned long cycle_2_5_clk;
1295 unsigned long cycle_3_0_clk;
1296 unsigned long cycle_4_0_clk;
1297 unsigned long cycle_5_0_clk;
1298 unsigned long max_2_0_tcyc_ns_x_100;
1299 unsigned long max_2_5_tcyc_ns_x_100;
1300 unsigned long max_3_0_tcyc_ns_x_100;
1301 unsigned long max_4_0_tcyc_ns_x_100;
1302 unsigned long max_5_0_tcyc_ns_x_100;
1303 unsigned long cycle_time_ns_x_100[3];
1304 PPC440_SYS_INFO board_cfg;
1305 unsigned char cas_2_0_available;
1306 unsigned char cas_2_5_available;
1307 unsigned char cas_3_0_available;
1308 unsigned char cas_4_0_available;
1309 unsigned char cas_5_0_available;
1310 unsigned long sdr_ddrpll;
1311
1312 /*------------------------------------------------------------------
1313 * Get the board configuration info.
1314 *-----------------------------------------------------------------*/
1315 get_sys_info(&board_cfg);
1316
1317 mfsdr(sdr_ddr0, sdr_ddrpll);
1318 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1319
1320 /*------------------------------------------------------------------
1321 * Handle the timing. We need to find the worst case timing of all
1322 * the dimm modules installed.
1323 *-----------------------------------------------------------------*/
1324 t_wr_ns = 0;
1325 cas_2_0_available = TRUE;
1326 cas_2_5_available = TRUE;
1327 cas_3_0_available = TRUE;
1328 cas_4_0_available = TRUE;
1329 cas_5_0_available = TRUE;
1330 max_2_0_tcyc_ns_x_100 = 10;
1331 max_2_5_tcyc_ns_x_100 = 10;
1332 max_3_0_tcyc_ns_x_100 = 10;
1333 max_4_0_tcyc_ns_x_100 = 10;
1334 max_5_0_tcyc_ns_x_100 = 10;
1335 sdram_ddr1 = TRUE;
1336
1337 /* loop through all the DIMM slots on the board */
1338 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1339 /* If a dimm is installed in a particular slot ... */
1340 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1341 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1342 sdram_ddr1 = TRUE;
1343 else
1344 sdram_ddr1 = FALSE;
1345
1346 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1347 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1348
1349 /* For a particular DIMM, grab the three CAS values it supports */
1350 for (cas_index = 0; cas_index < 3; cas_index++) {
1351 switch (cas_index) {
1352 case 0:
1353 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1354 break;
1355 case 1:
1356 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1357 break;
1358 default:
1359 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1360 break;
1361 }
1362
1363 if ((tcyc_reg & 0x0F) >= 10) {
1364 if ((tcyc_reg & 0x0F) == 0x0D) {
1365 /* Convert from hex to decimal */
1366 cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1367 } else {
1368 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1369 "in slot %d\n", (unsigned int)dimm_num);
1370 hang();
1371 }
1372 } else {
1373 /* Convert from hex to decimal */
1374 cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) +
1375 ((tcyc_reg & 0x0F)*10);
1376 }
1377 }
1378
1379 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1380 /* supported for a particular DIMM. */
1381 cas_index = 0;
1382
1383 if (sdram_ddr1) {
1384 /*
1385 * DDR devices use the following bitmask for CAS latency:
1386 * Bit 7 6 5 4 3 2 1 0
1387 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1388 */
1389 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1390 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1391 cas_index++;
1392 } else {
1393 if (cas_index != 0)
1394 cas_index++;
1395 cas_4_0_available = FALSE;
1396 }
1397
1398 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1399 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1400 cas_index++;
1401 } else {
1402 if (cas_index != 0)
1403 cas_index++;
1404 cas_3_0_available = FALSE;
1405 }
1406
1407 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1408 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1409 cas_index++;
1410 } else {
1411 if (cas_index != 0)
1412 cas_index++;
1413 cas_2_5_available = FALSE;
1414 }
1415
1416 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1417 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1418 cas_index++;
1419 } else {
1420 if (cas_index != 0)
1421 cas_index++;
1422 cas_2_0_available = FALSE;
1423 }
1424 } else {
1425 /*
1426 * DDR2 devices use the following bitmask for CAS latency:
1427 * Bit 7 6 5 4 3 2 1 0
1428 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1429 */
1430 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1431 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1432 cas_index++;
1433 } else {
1434 if (cas_index != 0)
1435 cas_index++;
1436 cas_5_0_available = FALSE;
1437 }
1438
1439 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1440 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1441 cas_index++;
1442 } else {
1443 if (cas_index != 0)
1444 cas_index++;
1445 cas_4_0_available = FALSE;
1446 }
1447
1448 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1449 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1450 cas_index++;
1451 } else {
1452 if (cas_index != 0)
1453 cas_index++;
1454 cas_3_0_available = FALSE;
1455 }
1456 }
1457 }
1458 }
1459
1460 /*------------------------------------------------------------------
1461 * Set the SDRAM mode, SDRAM_MMODE
1462 *-----------------------------------------------------------------*/
1463 mfsdram(SDRAM_MMODE, mmode);
1464 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1465
1466 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100);
1467 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100);
1468 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100);
1469 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100);
1470 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100);
1471
1472 if (sdram_ddr1 == TRUE) { /* DDR1 */
1473 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1474 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1475 *selected_cas = DDR_CAS_2;
1476 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1477 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1478 *selected_cas = DDR_CAS_2_5;
1479 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1480 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1481 *selected_cas = DDR_CAS_3;
1482 } else {
1483 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1484 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1485 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1486 hang();
1487 }
1488 } else { /* DDR2 */
1489 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1490 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1491 *selected_cas = DDR_CAS_3;
1492 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1493 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1494 *selected_cas = DDR_CAS_4;
1495 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1496 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1497 *selected_cas = DDR_CAS_5;
1498 } else {
1499 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1500 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1501 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1502 hang();
1503 }
1504 }
1505
1506 if (sdram_ddr1 == TRUE)
1507 mmode |= SDRAM_MMODE_WR_DDR1;
1508 else {
1509
1510 /* loop through all the DIMM slots on the board */
1511 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1512 /* If a dimm is installed in a particular slot ... */
1513 if (dimm_populated[dimm_num] != SDRAM_NONE)
1514 t_wr_ns = max(t_wr_ns,
1515 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1516 }
1517
1518 /*
1519 * convert from nanoseconds to ddr clocks
1520 * round up if necessary
1521 */
1522 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1523 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1524 if (sdram_freq != ddr_check)
1525 t_wr_clk++;
1526
1527 switch (t_wr_clk) {
1528 case 0:
1529 case 1:
1530 case 2:
1531 case 3:
1532 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1533 break;
1534 case 4:
1535 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1536 break;
1537 case 5:
1538 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1539 break;
1540 default:
1541 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1542 break;
1543 }
ba58e4c9 1544 *write_recovery = t_wr_clk;
4037ed3b
SR		 1545 }
1546
ba58e4c9
SR		 1547 debug("CAS latency = %d\n", *selected_cas);
1548 debug("Write recovery = %d\n", *write_recovery);
1549
4037ed3b
SR		 1550 mtsdram(SDRAM_MMODE, mmode);
1551}
1552
1553/*-----------------------------------------------------------------------------+
1554 * program_rtr.
1555 *-----------------------------------------------------------------------------*/
1556static void program_rtr(unsigned long *dimm_populated,
1557 unsigned char *iic0_dimm_addr,
1558 unsigned long num_dimm_banks)
1559{
1560 PPC440_SYS_INFO board_cfg;
1561 unsigned long max_refresh_rate;
1562 unsigned long dimm_num;
1563 unsigned long refresh_rate_type;
1564 unsigned long refresh_rate;
1565 unsigned long rint;
1566 unsigned long sdram_freq;
1567 unsigned long sdr_ddrpll;
1568 unsigned long val;
1569
1570 /*------------------------------------------------------------------
1571 * Get the board configuration info.
1572 *-----------------------------------------------------------------*/
1573 get_sys_info(&board_cfg);
1574
1575 /*------------------------------------------------------------------
1576 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1577 *-----------------------------------------------------------------*/
1578 mfsdr(sdr_ddr0, sdr_ddrpll);
1579 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1580
1581 max_refresh_rate = 0;
1582 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1583 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1584
1585 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1586 refresh_rate_type &= 0x7F;
1587 switch (refresh_rate_type) {
1588 case 0:
1589 refresh_rate = 15625;
1590 break;
1591 case 1:
1592 refresh_rate = 3906;
1593 break;
1594 case 2:
1595 refresh_rate = 7812;
1596 break;
1597 case 3:
1598 refresh_rate = 31250;
1599 break;
1600 case 4:
1601 refresh_rate = 62500;
1602 break;
1603 case 5:
1604 refresh_rate = 125000;
1605 break;
1606 default:
1607 refresh_rate = 0;
1608 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1609 (unsigned int)dimm_num);
1610 printf("Replace the DIMM module with a supported DIMM.\n\n");
1611 hang();
1612 break;
1613 }
1614
1615 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1616 }
1617 }
1618
1619 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1620 mfsdram(SDRAM_RTR, val);
1621 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1622 (SDRAM_RTR_RINT_ENCODE(rint)));
1623}
1624
1625/*------------------------------------------------------------------
1626 * This routine programs the SDRAM_TRx registers.
1627 *-----------------------------------------------------------------*/
1628static void program_tr(unsigned long *dimm_populated,
1629 unsigned char *iic0_dimm_addr,
1630 unsigned long num_dimm_banks)
1631{
1632 unsigned long dimm_num;
1633 unsigned long sdram_ddr1;
1634 unsigned long t_rp_ns;
1635 unsigned long t_rcd_ns;
1636 unsigned long t_rrd_ns;
1637 unsigned long t_ras_ns;
1638 unsigned long t_rc_ns;
1639 unsigned long t_rfc_ns;
1640 unsigned long t_wpc_ns;
1641 unsigned long t_wtr_ns;
1642 unsigned long t_rpc_ns;
1643 unsigned long t_rp_clk;
1644 unsigned long t_rcd_clk;
1645 unsigned long t_rrd_clk;
1646 unsigned long t_ras_clk;
1647 unsigned long t_rc_clk;
1648 unsigned long t_rfc_clk;
1649 unsigned long t_wpc_clk;
1650 unsigned long t_wtr_clk;
1651 unsigned long t_rpc_clk;
1652 unsigned long sdtr1, sdtr2, sdtr3;
1653 unsigned long ddr_check;
1654 unsigned long sdram_freq;
1655 unsigned long sdr_ddrpll;
1656
1657 PPC440_SYS_INFO board_cfg;
1658
1659 /*------------------------------------------------------------------
1660 * Get the board configuration info.
1661 *-----------------------------------------------------------------*/
1662 get_sys_info(&board_cfg);
1663
1664 mfsdr(sdr_ddr0, sdr_ddrpll);
1665 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1666
1667 /*------------------------------------------------------------------
1668 * Handle the timing. We need to find the worst case timing of all
1669 * the dimm modules installed.
1670 *-----------------------------------------------------------------*/
1671 t_rp_ns = 0;
1672 t_rrd_ns = 0;
1673 t_rcd_ns = 0;
1674 t_ras_ns = 0;
1675 t_rc_ns = 0;
1676 t_rfc_ns = 0;
1677 t_wpc_ns = 0;
1678 t_wtr_ns = 0;
1679 t_rpc_ns = 0;
1680 sdram_ddr1 = TRUE;
1681
1682 /* loop through all the DIMM slots on the board */
1683 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1684 /* If a dimm is installed in a particular slot ... */
1685 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1686 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1687 sdram_ddr1 = TRUE;
1688 else
1689 sdram_ddr1 = FALSE;
1690
1691 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1692 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1693 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1694 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1695 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1696 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1697 }
1698 }
1699
1700 /*------------------------------------------------------------------
1701 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1702 *-----------------------------------------------------------------*/
1703 mfsdram(SDRAM_SDTR1, sdtr1);
1704 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1705 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1706
1707 /* default values */
1708 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1709 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1710
1711 /* normal operations */
1712 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1713 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1714
1715 mtsdram(SDRAM_SDTR1, sdtr1);
1716
1717 /*------------------------------------------------------------------
1718 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1719 *-----------------------------------------------------------------*/
1720 mfsdram(SDRAM_SDTR2, sdtr2);
1721 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1722 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1723 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1724 SDRAM_SDTR2_RRD_MASK);
1725
1726 /*
1727 * convert t_rcd from nanoseconds to ddr clocks
1728 * round up if necessary
1729 */
1730 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1731 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1732 if (sdram_freq != ddr_check)
1733 t_rcd_clk++;
1734
1735 switch (t_rcd_clk) {
1736 case 0:
1737 case 1:
1738 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1739 break;
1740 case 2:
1741 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1742 break;
1743 case 3:
1744 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1745 break;
1746 case 4:
1747 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1748 break;
1749 default:
1750 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1751 break;
1752 }
1753
1754 if (sdram_ddr1 == TRUE) { /* DDR1 */
1755 if (sdram_freq < 200000000) {
1756 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1757 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1758 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1759 } else {
1760 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1761 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1762 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1763 }
1764 } else { /* DDR2 */
1765 /* loop through all the DIMM slots on the board */
1766 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1767 /* If a dimm is installed in a particular slot ... */
1768 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1769 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1770 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1771 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1772 }
1773 }
1774
1775 /*
1776 * convert from nanoseconds to ddr clocks
1777 * round up if necessary
1778 */
1779 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1780 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1781 if (sdram_freq != ddr_check)
1782 t_wpc_clk++;
1783
1784 switch (t_wpc_clk) {
1785 case 0:
1786 case 1:
1787 case 2:
1788 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1789 break;
1790 case 3:
1791 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1792 break;
1793 case 4:
1794 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1795 break;
1796 case 5:
1797 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1798 break;
1799 default:
1800 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1801 break;
1802 }
1803
1804 /*
1805 * convert from nanoseconds to ddr clocks
1806 * round up if necessary
1807 */
1808 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1809 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1810 if (sdram_freq != ddr_check)
1811 t_wtr_clk++;
1812
1813 switch (t_wtr_clk) {
1814 case 0:
1815 case 1:
1816 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1817 break;
1818 case 2:
1819 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1820 break;
1821 case 3:
1822 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1823 break;
1824 default:
1825 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1826 break;
1827 }
1828
1829 /*
1830 * convert from nanoseconds to ddr clocks
1831 * round up if necessary
1832 */
1833 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1834 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1835 if (sdram_freq != ddr_check)
1836 t_rpc_clk++;
1837
1838 switch (t_rpc_clk) {
1839 case 0:
1840 case 1:
1841 case 2:
1842 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1843 break;
1844 case 3:
1845 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1846 break;
1847 default:
1848 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1849 break;
1850 }
1851 }
1852
1853 /* default value */
1854 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1855
1856 /*
1857 * convert t_rrd from nanoseconds to ddr clocks
1858 * round up if necessary
1859 */
1860 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1861 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1862 if (sdram_freq != ddr_check)
1863 t_rrd_clk++;
1864
1865 if (t_rrd_clk == 3)
1866 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1867 else
1868 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1869
1870 /*
1871 * convert t_rp from nanoseconds to ddr clocks
1872 * round up if necessary
1873 */
1874 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1875 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1876 if (sdram_freq != ddr_check)
1877 t_rp_clk++;
1878
1879 switch (t_rp_clk) {
1880 case 0:
1881 case 1:
1882 case 2:
1883 case 3:
1884 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1885 break;
1886 case 4:
1887 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1888 break;
1889 case 5:
1890 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1891 break;
1892 case 6:
1893 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1894 break;
1895 default:
1896 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1897 break;
1898 }
1899
1900 mtsdram(SDRAM_SDTR2, sdtr2);
1901
1902 /*------------------------------------------------------------------
1903 * Set the SDRAM Timing Reg 3, SDRAM_TR3
1904 *-----------------------------------------------------------------*/
1905 mfsdram(SDRAM_SDTR3, sdtr3);
1906 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
1907 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1908
1909 /*
1910 * convert t_ras from nanoseconds to ddr clocks
1911 * round up if necessary
1912 */
1913 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1914 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1915 if (sdram_freq != ddr_check)
1916 t_ras_clk++;
1917
1918 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1919
1920 /*
1921 * convert t_rc from nanoseconds to ddr clocks
1922 * round up if necessary
1923 */
1924 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1925 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1926 if (sdram_freq != ddr_check)
1927 t_rc_clk++;
1928
1929 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1930
1931 /* default xcs value */
1932 sdtr3 |= SDRAM_SDTR3_XCS;
1933
1934 /*
1935 * convert t_rfc from nanoseconds to ddr clocks
1936 * round up if necessary
1937 */
1938 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1939 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
1940 if (sdram_freq != ddr_check)
1941 t_rfc_clk++;
1942
1943 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
1944
1945 mtsdram(SDRAM_SDTR3, sdtr3);
1946}
1947
1948/*-----------------------------------------------------------------------------+
1949 * program_bxcf.
1950 *-----------------------------------------------------------------------------*/
1951static void program_bxcf(unsigned long *dimm_populated,
1952 unsigned char *iic0_dimm_addr,
1953 unsigned long num_dimm_banks)
1954{
1955 unsigned long dimm_num;
1956 unsigned long num_col_addr;
1957 unsigned long num_ranks;
1958 unsigned long num_banks;
1959 unsigned long mode;
1960 unsigned long ind_rank;
1961 unsigned long ind;
1962 unsigned long ind_bank;
1963 unsigned long bank_0_populated;
1964
1965 /*------------------------------------------------------------------
1966 * Set the BxCF regs. First, wipe out the bank config registers.
1967 *-----------------------------------------------------------------*/
1968 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
1969 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1970 mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
1971 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1972 mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
1973 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1974 mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
1975 mtdcr(SDRAMC_CFGDATA, 0x00000000);
1976
1977 mode = SDRAM_BXCF_M_BE_ENABLE;
1978
1979 bank_0_populated = 0;
1980
1981 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1982 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1983 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1984 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
1985 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
1986 num_ranks = (num_ranks & 0x0F) +1;
1987 else
1988 num_ranks = num_ranks & 0x0F;
1989
1990 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
1991
1992 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
1993 if (num_banks == 4)
1994 ind = 0;
1995 else
1996 ind = 5;
1997 switch (num_col_addr) {
1998 case 0x08:
1999 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2000 break;
2001 case 0x09:
2002 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2003 break;
2004 case 0x0A:
2005 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2006 break;
2007 case 0x0B:
2008 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2009 break;
2010 case 0x0C:
2011 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2012 break;
2013 default:
2014 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2015 (unsigned int)dimm_num);
2016 printf("ERROR: Unsupported value for number of "
2017 "column addresses: %d.\n", (unsigned int)num_col_addr);
2018 printf("Replace the DIMM module with a supported DIMM.\n\n");
2019 hang();
2020 }
2021 }
2022
2023 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2024 bank_0_populated = 1;
2025
2026 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2027 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2028 mtdcr(SDRAMC_CFGDATA, mode);
2029 }
2030 }
2031 }
2032}
2033
2034/*------------------------------------------------------------------
2035 * program memory queue.
2036 *-----------------------------------------------------------------*/
2037static void program_memory_queue(unsigned long *dimm_populated,
2038 unsigned char *iic0_dimm_addr,
2039 unsigned long num_dimm_banks)
2040{
2041 unsigned long dimm_num;
2042 unsigned long rank_base_addr;
2043 unsigned long rank_reg;
2044 unsigned long rank_size_bytes;
2045 unsigned long rank_size_id;
2046 unsigned long num_ranks;
2047 unsigned long baseadd_size;
2048 unsigned long i;
2049 unsigned long bank_0_populated = 0;
2050
2051 /*------------------------------------------------------------------
2052 * Reset the rank_base_address.
2053 *-----------------------------------------------------------------*/
2054 rank_reg = SDRAM_R0BAS;
2055
2056 rank_base_addr = 0x00000000;
2057
2058 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2059 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2060 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2061 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2062 num_ranks = (num_ranks & 0x0F) + 1;
2063 else
2064 num_ranks = num_ranks & 0x0F;
2065
2066 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2067
2068 /*------------------------------------------------------------------
2069 * Set the sizes
2070 *-----------------------------------------------------------------*/
2071 baseadd_size = 0;
2072 rank_size_bytes = 1024 * 1024 * rank_size_id;
2073 switch (rank_size_id) {
2074 case 0x02:
2075 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2076 break;
2077 case 0x04:
2078 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2079 break;
2080 case 0x08:
2081 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2082 break;
2083 case 0x10:
2084 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2085 break;
2086 case 0x20:
2087 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2088 break;
2089 case 0x40:
2090 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2091 break;
2092 case 0x80:
2093 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2094 break;
2095 default:
2096 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2097 (unsigned int)dimm_num);
2098 printf("ERROR: Unsupported value for the banksize: %d.\n",
2099 (unsigned int)rank_size_id);
2100 printf("Replace the DIMM module with a supported DIMM.\n\n");
2101 hang();
2102 }
2103
2104 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2105 bank_0_populated = 1;
2106
2107 for (i = 0; i < num_ranks; i++) {
2108 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2109 (rank_base_addr & SDRAM_RXBAS_SDBA_MASK) |
2110 baseadd_size);
2111 rank_base_addr += rank_size_bytes;
2112 }
2113 }
2114 }
2115}
2116
2117/*-----------------------------------------------------------------------------+
2118 * is_ecc_enabled.
2119 *-----------------------------------------------------------------------------*/
2120static unsigned long is_ecc_enabled(void)
2121{
2122 unsigned long dimm_num;
2123 unsigned long ecc;
2124 unsigned long val;
2125
2126 ecc = 0;
2127 /* loop through all the DIMM slots on the board */
2128 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2129 mfsdram(SDRAM_MCOPT1, val);
2130 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2131 }
2132
2133 return(ecc);
2134}
2135
2136/*-----------------------------------------------------------------------------+
2137 * program_ecc.
2138 *-----------------------------------------------------------------------------*/
2139static void program_ecc(unsigned long *dimm_populated,
2140 unsigned char *iic0_dimm_addr,
ba58e4c9
SR		 2141 unsigned long num_dimm_banks,
2142 unsigned long tlb_word2_i_value)
4037ed3b
SR		 2143{
2144 unsigned long mcopt1;
2145 unsigned long mcopt2;
2146 unsigned long mcstat;
2147 unsigned long dimm_num;
2148 unsigned long ecc;
2149
2150 ecc = 0;
2151 /* loop through all the DIMM slots on the board */
2152 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2153 /* If a dimm is installed in a particular slot ... */
2154 if (dimm_populated[dimm_num] != SDRAM_NONE)
2155 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2156 }
2157 if (ecc == 0)
2158 return;
2159
2160 mfsdram(SDRAM_MCOPT1, mcopt1);
2161 mfsdram(SDRAM_MCOPT2, mcopt2);
2162
2163 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2164 /* DDR controller must be enabled and not in self-refresh. */
2165 mfsdram(SDRAM_MCSTAT, mcstat);
2166 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2167 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2168 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2169 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2170
ba58e4c9 2171 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
4037ed3b
SR		 2172 }
2173 }
2174
2175 return;
2176}
2177
ba58e4c9
SR		 2178#ifdef CONFIG_ECC_ERROR_RESET
2179/*
2180 * Check for ECC errors and reset board upon any error here
2181 *
2182 * On the Katmai 440SPe eval board, from time to time, the first
2183 * lword write access after DDR2 initializazion with ECC checking
2184 * enabled, leads to an ECC error. I couldn't find a configuration
2185 * without this happening. On my board with the current setup it
2186 * happens about 1 from 10 times.
2187 *
2188 * The ECC modules used for testing are:
2189 * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2190 *
2191 * This has to get fixed for the Katmai and tested for the other
2192 * board (440SP/440SPe) that will eventually use this code in the
2193 * future.
2194 *
2195 * 2007-03-01, sr
2196 */
2197static void check_ecc(void)
2198{
2199 u32 val;
2200
2201 mfsdram(SDRAM_ECCCR, val);
2202 if (val != 0) {
2203 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2204 val, mfdcr(0x4c), mfdcr(0x4e));
2205 printf("ECC error occured, resetting board...\n");
2206 do_reset(NULL, 0, 0, NULL);
2207 }
2208}
2209#endif
2210
4037ed3b
SR		 2211/*-----------------------------------------------------------------------------+
2212 * program_ecc_addr.
2213 *-----------------------------------------------------------------------------*/
2214static void program_ecc_addr(unsigned long start_address,
ba58e4c9
SR		 2215 unsigned long num_bytes,
2216 unsigned long tlb_word2_i_value)
4037ed3b
SR		 2217{
2218 unsigned long current_address;
2219 unsigned long end_address;
2220 unsigned long address_increment;
2221 unsigned long mcopt1;
ba58e4c9
SR		 2222 char str[] = "ECC generation...";
2223 int i;
4037ed3b
SR		 2224
2225 current_address = start_address;
2226 mfsdram(SDRAM_MCOPT1, mcopt1);
2227 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2228 mtsdram(SDRAM_MCOPT1,
2229 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2230 sync();
2231 eieio();
2232 wait_ddr_idle();
2233
ba58e4c9
SR		 2234 puts(str);
2235 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2236 /* ECC bit set method for non-cached memory */
2237 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2238 address_increment = 4;
2239 else
2240 address_increment = 8;
2241 end_address = current_address + num_bytes;
4037ed3b 2242
ba58e4c9
SR		 2243 while (current_address < end_address) {
2244 *((unsigned long *)current_address) = 0x00000000;
2245 current_address += address_increment;
2246 }
2247 } else {
2248 /* ECC bit set method for cached memory */
2249 dcbz_area(start_address, num_bytes);
2250 dflush();
4037ed3b 2251 }
ba58e4c9
SR		 2252 for (i=0; i<strlen(str); i++)
2253 putc('\b');
2254
4037ed3b
SR		 2255 sync();
2256 eieio();
2257 wait_ddr_idle();
2258
ba58e4c9
SR		 2259 /* clear ECC error repoting registers */
2260 mtsdram(SDRAM_ECCCR, 0xffffffff);
2261 mtdcr(0x4c, 0xffffffff);
2262
4037ed3b 2263 mtsdram(SDRAM_MCOPT1,
ba58e4c9 2264 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
4037ed3b
SR		 2265 sync();
2266 eieio();
2267 wait_ddr_idle();
ba58e4c9
SR		 2268
2269#ifdef CONFIG_ECC_ERROR_RESET
2270 /*
2271 * One write to 0 is enough to trigger this ECC error
2272 * (see description above)
2273 */
2274 out_be32(0, 0x12345678);
2275 check_ecc();
2276#endif
4037ed3b
SR		 2277 }
2278}
2279
2280/*-----------------------------------------------------------------------------+
2281 * program_DQS_calibration.
2282 *-----------------------------------------------------------------------------*/
2283static void program_DQS_calibration(unsigned long *dimm_populated,
2284 unsigned char *iic0_dimm_addr,
2285 unsigned long num_dimm_banks)
2286{
2287 unsigned long val;
2288
2289#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2290 mtsdram(SDRAM_RQDC, 0x80000037);
2291 mtsdram(SDRAM_RDCC, 0x40000000);
2292 mtsdram(SDRAM_RFDC, 0x000001DF);
2293
2294 test();
2295#else
2296 /*------------------------------------------------------------------
2297 * Program RDCC register
2298 * Read sample cycle auto-update enable
2299 *-----------------------------------------------------------------*/
2300
2301 /*
2302 * Modified for the Katmai platform: with some DIMMs, the DDR2
2303 * controller automatically selects the T2 read cycle, but this
2304 * proves unreliable. Go ahead and force the DDR2 controller
2305 * to use the T4 sample and disable the automatic update of the
2306 * RDSS field.
2307 */
2308 mfsdram(SDRAM_RDCC, val);
2309 mtsdram(SDRAM_RDCC,
2310 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2311 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2312
2313 /*------------------------------------------------------------------
2314 * Program RQDC register
2315 * Internal DQS delay mechanism enable
2316 *-----------------------------------------------------------------*/
2317 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2318
2319 /*------------------------------------------------------------------
2320 * Program RFDC register
2321 * Set Feedback Fractional Oversample
2322 * Auto-detect read sample cycle enable
2323 *-----------------------------------------------------------------*/
2324 mfsdram(SDRAM_RFDC, val);
2325 mtsdram(SDRAM_RFDC,
2326 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2327 SDRAM_RFDC_RFFD_MASK))
2328 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2329 SDRAM_RFDC_RFFD_ENCODE(0)));
2330
2331 DQS_calibration_process();
2332#endif
2333}
2334
2335static u32 short_mem_test(void)
2336{
2337 u32 *membase;
2338 u32 bxcr_num;
2339 u32 bxcf;
2340 int i;
2341 int j;
2342 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2343 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2344 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2345 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2346 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2347 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2348 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2349 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2350 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2351 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2352 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2353 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2354 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2355 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2356 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2357 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2358 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2359
2360 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2361 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2362
2363 /* Banks enabled */
2364 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2365
2366 /* Bank is enabled */
2367 membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2368
2369 /*------------------------------------------------------------------
2370 * Run the short memory test.
2371 *-----------------------------------------------------------------*/
2372 for (i = 0; i < NUMMEMTESTS; i++) {
2373 for (j = 0; j < NUMMEMWORDS; j++) {
2374 membase[j] = test[i][j];
2375 ppcDcbf((u32)&(membase[j]));
2376 }
2377 sync();
2378 for (j = 0; j < NUMMEMWORDS; j++) {
2379 if (membase[j] != test[i][j]) {
2380 ppcDcbf((u32)&(membase[j]));
2381 break;
2382 }
2383 ppcDcbf((u32)&(membase[j]));
2384 }
2385 sync();
2386 if (j < NUMMEMWORDS)
2387 break;
2388 }
2389 if (i < NUMMEMTESTS)
2390 break;
2391 } /* if bank enabled */
2392 } /* for bxcf_num */
2393
2394 return bxcr_num;
2395}
2396
2397#ifndef HARD_CODED_DQS
2398/*-----------------------------------------------------------------------------+
2399 * DQS_calibration_process.
2400 *-----------------------------------------------------------------------------*/
2401static void DQS_calibration_process(void)
2402{
2403 unsigned long ecc_temp;
2404 unsigned long rfdc_reg;
2405 unsigned long rffd;
2406 unsigned long rqdc_reg;
2407 unsigned long rqfd;
2408 unsigned long bxcr_num;
2409 unsigned long val;
2410 long rqfd_average;
2411 long rffd_average;
2412 long max_start;
2413 long min_end;
2414 unsigned long begin_rqfd[MAXRANKS];
2415 unsigned long begin_rffd[MAXRANKS];
2416 unsigned long end_rqfd[MAXRANKS];
2417 unsigned long end_rffd[MAXRANKS];
2418 char window_found;
2419 unsigned long dlycal;
2420 unsigned long dly_val;
2421 unsigned long max_pass_length;
2422 unsigned long current_pass_length;
2423 unsigned long current_fail_length;
2424 unsigned long current_start;
2425 long max_end;
2426 unsigned char fail_found;
2427 unsigned char pass_found;
2428
2429 /*------------------------------------------------------------------
2430 * Test to determine the best read clock delay tuning bits.
2431 *
2432 * Before the DDR controller can be used, the read clock delay needs to be
2433 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2434 * This value cannot be hardcoded into the program because it changes
2435 * depending on the board's setup and environment.
2436 * To do this, all delay values are tested to see if they
2437 * work or not. By doing this, you get groups of fails with groups of
2438 * passing values. The idea is to find the start and end of a passing
2439 * window and take the center of it to use as the read clock delay.
2440 *
2441 * A failure has to be seen first so that when we hit a pass, we know
2442 * that it is truely the start of the window. If we get passing values
2443 * to start off with, we don't know if we are at the start of the window.
2444 *
2445 * The code assumes that a failure will always be found.
2446 * If a failure is not found, there is no easy way to get the middle
2447 * of the passing window. I guess we can pretty much pick any value
2448 * but some values will be better than others. Since the lowest speed
2449 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2450 * from experimentation it is safe to say you will always have a failure.
2451 *-----------------------------------------------------------------*/
2452 mfsdram(SDRAM_MCOPT1, ecc_temp);
2453 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2454 mfsdram(SDRAM_MCOPT1, val);
2455 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2456 SDRAM_MCOPT1_MCHK_NON);
2457
2458 max_start = 0;
2459 min_end = 0;
2460 begin_rqfd[0] = 0;
2461 begin_rffd[0] = 0;
2462 begin_rqfd[1] = 0;
2463 begin_rffd[1] = 0;
2464 end_rqfd[0] = 0;
2465 end_rffd[0] = 0;
2466 end_rqfd[1] = 0;
2467 end_rffd[1] = 0;
2468 window_found = FALSE;
2469
2470 max_pass_length = 0;
2471 max_start = 0;
2472 max_end = 0;
2473 current_pass_length = 0;
2474 current_fail_length = 0;
2475 current_start = 0;
2476 window_found = FALSE;
2477 fail_found = FALSE;
2478 pass_found = FALSE;
2479
2480 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2481 /* rqdc_reg = mfsdram(SDRAM_RQDC) & ~(SDRAM_RQDC_RQFD_MASK); */
2482
2483 /*
2484 * get the delay line calibration register value
2485 */
2486 mfsdram(SDRAM_DLCR, dlycal);
2487 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2488
2489 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2490 mfsdram(SDRAM_RFDC, rfdc_reg);
2491 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2492
2493 /*------------------------------------------------------------------
2494 * Set the timing reg for the test.
2495 *-----------------------------------------------------------------*/
2496 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2497
2498 /* do the small memory test */
2499 bxcr_num = short_mem_test();
2500
2501 /*------------------------------------------------------------------
2502 * See if the rffd value passed.
2503 *-----------------------------------------------------------------*/
2504 if (bxcr_num == MAXBXCF) {
2505 if (fail_found == TRUE) {
2506 pass_found = TRUE;
2507 if (current_pass_length == 0)
2508 current_start = rffd;
2509
2510 current_fail_length = 0;
2511 current_pass_length++;
2512
2513 if (current_pass_length > max_pass_length) {
2514 max_pass_length = current_pass_length;
2515 max_start = current_start;
2516 max_end = rffd;
2517 }
2518 }
2519 } else {
2520 current_pass_length = 0;
2521 current_fail_length++;
2522
2523 if (current_fail_length >= (dly_val >> 2)) {
2524 if (fail_found == FALSE) {
2525 fail_found = TRUE;
2526 } else if (pass_found == TRUE) {
2527 window_found = TRUE;
2528 break;
2529 }
2530 }
2531 }
2532 } /* for rffd */
2533
2534
2535 /*------------------------------------------------------------------
2536 * Set the average RFFD value
2537 *-----------------------------------------------------------------*/
2538 rffd_average = ((max_start + max_end) >> 1);
2539
2540 if (rffd_average < 0)
2541 rffd_average = 0;
2542
2543 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2544 rffd_average = SDRAM_RFDC_RFFD_MAX;
2545 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2546 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2547
2548 max_pass_length = 0;
2549 max_start = 0;
2550 max_end = 0;
2551 current_pass_length = 0;
2552 current_fail_length = 0;
2553 current_start = 0;
2554 window_found = FALSE;
2555 fail_found = FALSE;
2556 pass_found = FALSE;
2557
2558 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2559 mfsdram(SDRAM_RQDC, rqdc_reg);
2560 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2561
2562 /*------------------------------------------------------------------
2563 * Set the timing reg for the test.
2564 *-----------------------------------------------------------------*/
2565 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2566
2567 /* do the small memory test */
2568 bxcr_num = short_mem_test();
2569
2570 /*------------------------------------------------------------------
2571 * See if the rffd value passed.
2572 *-----------------------------------------------------------------*/
2573 if (bxcr_num == MAXBXCF) {
2574 if (fail_found == TRUE) {
2575 pass_found = TRUE;
2576 if (current_pass_length == 0)
2577 current_start = rqfd;
2578
2579 current_fail_length = 0;
2580 current_pass_length++;
2581
2582 if (current_pass_length > max_pass_length) {
2583 max_pass_length = current_pass_length;
2584 max_start = current_start;
2585 max_end = rqfd;
2586 }
2587 }
2588 } else {
2589 current_pass_length = 0;
2590 current_fail_length++;
2591
2592 if (fail_found == FALSE) {
2593 fail_found = TRUE;
2594 } else if (pass_found == TRUE) {
2595 window_found = TRUE;
2596 break;
2597 }
2598 }
2599 }
2600
2601 /*------------------------------------------------------------------
2602 * Make sure we found the valid read passing window. Halt if not
2603 *-----------------------------------------------------------------*/
2604 if (window_found == FALSE) {
2605 printf("ERROR: Cannot determine a common read delay for the "
2606 "DIMM(s) installed.\n");
2607 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2608 hang();
2609 }
2610
2611 rqfd_average = ((max_start + max_end) >> 1);
2612
2613 if (rqfd_average < 0)
2614 rqfd_average = 0;
2615
2616 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2617 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2618
2619 /*------------------------------------------------------------------
2620 * Restore the ECC variable to what it originally was
2621 *-----------------------------------------------------------------*/
2622 mfsdram(SDRAM_MCOPT1, val);
2623 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | ecc_temp);
2624
2625 mtsdram(SDRAM_RQDC,
2626 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2627 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2628
2629 mfsdram(SDRAM_DLCR, val);
2630 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2631 mfsdram(SDRAM_RQDC, val);
2632 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2633 mfsdram(SDRAM_RFDC, val);
2634 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2635}
2636#else /* calibration test with hardvalues */
2637/*-----------------------------------------------------------------------------+
2638 * DQS_calibration_process.
2639 *-----------------------------------------------------------------------------*/
2640static void test(void)
2641{
2642 unsigned long dimm_num;
2643 unsigned long ecc_temp;
2644 unsigned long i, j;
2645 unsigned long *membase;
2646 unsigned long bxcf[MAXRANKS];
2647 unsigned long val;
2648 char window_found;
2649 char begin_found[MAXDIMMS];
2650 char end_found[MAXDIMMS];
2651 char search_end[MAXDIMMS];
2652 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2653 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2654 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2655 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2656 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2657 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2658 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2659 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2660 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2661 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2662 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2663 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2664 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2665 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2666 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2667 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2668 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2669
2670 /*------------------------------------------------------------------
2671 * Test to determine the best read clock delay tuning bits.
2672 *
2673 * Before the DDR controller can be used, the read clock delay needs to be
2674 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2675 * This value cannot be hardcoded into the program because it changes
2676 * depending on the board's setup and environment.
2677 * To do this, all delay values are tested to see if they
2678 * work or not. By doing this, you get groups of fails with groups of
2679 * passing values. The idea is to find the start and end of a passing
2680 * window and take the center of it to use as the read clock delay.
2681 *
2682 * A failure has to be seen first so that when we hit a pass, we know
2683 * that it is truely the start of the window. If we get passing values
2684 * to start off with, we don't know if we are at the start of the window.
2685 *
2686 * The code assumes that a failure will always be found.
2687 * If a failure is not found, there is no easy way to get the middle
2688 * of the passing window. I guess we can pretty much pick any value
2689 * but some values will be better than others. Since the lowest speed
2690 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2691 * from experimentation it is safe to say you will always have a failure.
2692 *-----------------------------------------------------------------*/
2693 mfsdram(SDRAM_MCOPT1, ecc_temp);
2694 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2695 mfsdram(SDRAM_MCOPT1, val);
2696 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2697 SDRAM_MCOPT1_MCHK_NON);
2698
2699 window_found = FALSE;
2700 begin_found[0] = FALSE;
2701 end_found[0] = FALSE;
2702 search_end[0] = FALSE;
2703 begin_found[1] = FALSE;
2704 end_found[1] = FALSE;
2705 search_end[1] = FALSE;
2706
2707 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2708 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2709
2710 /* Banks enabled */
2711 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2712
2713 /* Bank is enabled */
2714 membase =
2715 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2716
2717 /*------------------------------------------------------------------
2718 * Run the short memory test.
2719 *-----------------------------------------------------------------*/
2720 for (i = 0; i < NUMMEMTESTS; i++) {
2721 for (j = 0; j < NUMMEMWORDS; j++) {
2722 membase[j] = test[i][j];
2723 ppcDcbf((u32)&(membase[j]));
2724 }
2725 sync();
2726 for (j = 0; j < NUMMEMWORDS; j++) {
2727 if (membase[j] != test[i][j]) {
2728 ppcDcbf((u32)&(membase[j]));
2729 break;
2730 }
2731 ppcDcbf((u32)&(membase[j]));
2732 }
2733 sync();
2734 if (j < NUMMEMWORDS)
2735 break;
2736 }
2737
2738 /*------------------------------------------------------------------
2739 * See if the rffd value passed.
2740 *-----------------------------------------------------------------*/
2741 if (i < NUMMEMTESTS) {
2742 if ((end_found[dimm_num] == FALSE) &&
2743 (search_end[dimm_num] == TRUE)) {
2744 end_found[dimm_num] = TRUE;
2745 }
2746 if ((end_found[0] == TRUE) &&
2747 (end_found[1] == TRUE))
2748 break;
2749 } else {
2750 if (begin_found[dimm_num] == FALSE) {
2751 begin_found[dimm_num] = TRUE;
2752 search_end[dimm_num] = TRUE;
2753 }
2754 }
2755 } else {
2756 begin_found[dimm_num] = TRUE;
2757 end_found[dimm_num] = TRUE;
2758 }
2759 }
2760
2761 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2762 window_found = TRUE;
2763
2764 /*------------------------------------------------------------------
2765 * Make sure we found the valid read passing window. Halt if not
2766 *-----------------------------------------------------------------*/
2767 if (window_found == FALSE) {
2768 printf("ERROR: Cannot determine a common read delay for the "
2769 "DIMM(s) installed.\n");
2770 hang();
2771 }
2772
2773 /*------------------------------------------------------------------
2774 * Restore the ECC variable to what it originally was
2775 *-----------------------------------------------------------------*/
2776 mtsdram(SDRAM_MCOPT1,
2777 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2778 | ecc_temp);
2779}
2780#endif
2781
2782#if defined(DEBUG)
2783static void ppc440sp_sdram_register_dump(void)
2784{
2785 unsigned int sdram_reg;
2786 unsigned int sdram_data;
2787 unsigned int dcr_data;
2788
2789 printf("\n Register Dump:\n");
2790 sdram_reg = SDRAM_MCSTAT;
2791 mfsdram(sdram_reg, sdram_data);
2792 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2793 sdram_reg = SDRAM_MCOPT1;
2794 mfsdram(sdram_reg, sdram_data);
2795 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2796 sdram_reg = SDRAM_MCOPT2;
2797 mfsdram(sdram_reg, sdram_data);
2798 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2799 sdram_reg = SDRAM_MODT0;
2800 mfsdram(sdram_reg, sdram_data);
2801 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2802 sdram_reg = SDRAM_MODT1;
2803 mfsdram(sdram_reg, sdram_data);
2804 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2805 sdram_reg = SDRAM_MODT2;
2806 mfsdram(sdram_reg, sdram_data);
2807 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2808 sdram_reg = SDRAM_MODT3;
2809 mfsdram(sdram_reg, sdram_data);
2810 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2811 sdram_reg = SDRAM_CODT;
2812 mfsdram(sdram_reg, sdram_data);
2813 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2814 sdram_reg = SDRAM_VVPR;
2815 mfsdram(sdram_reg, sdram_data);
2816 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2817 sdram_reg = SDRAM_OPARS;
2818 mfsdram(sdram_reg, sdram_data);
2819 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2820 /*
2821 * OPAR2 is only used as a trigger register.
2822 * No data is contained in this register, and reading or writing
2823 * to is can cause bad things to happen (hangs). Just skip it
2824 * and report NA
2825 * sdram_reg = SDRAM_OPAR2;
2826 * mfsdram(sdram_reg, sdram_data);
2827 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2828 */
2829 printf(" SDRAM_OPART = N/A ");
2830 sdram_reg = SDRAM_RTR;
2831 mfsdram(sdram_reg, sdram_data);
2832 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
2833 sdram_reg = SDRAM_MB0CF;
2834 mfsdram(sdram_reg, sdram_data);
2835 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
2836 sdram_reg = SDRAM_MB1CF;
2837 mfsdram(sdram_reg, sdram_data);
2838 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
2839 sdram_reg = SDRAM_MB2CF;
2840 mfsdram(sdram_reg, sdram_data);
2841 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
2842 sdram_reg = SDRAM_MB3CF;
2843 mfsdram(sdram_reg, sdram_data);
2844 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
2845 sdram_reg = SDRAM_INITPLR0;
2846 mfsdram(sdram_reg, sdram_data);
2847 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
2848 sdram_reg = SDRAM_INITPLR1;
2849 mfsdram(sdram_reg, sdram_data);
2850 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
2851 sdram_reg = SDRAM_INITPLR2;
2852 mfsdram(sdram_reg, sdram_data);
2853 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
2854 sdram_reg = SDRAM_INITPLR3;
2855 mfsdram(sdram_reg, sdram_data);
2856 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
2857 sdram_reg = SDRAM_INITPLR4;
2858 mfsdram(sdram_reg, sdram_data);
2859 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
2860 sdram_reg = SDRAM_INITPLR5;
2861 mfsdram(sdram_reg, sdram_data);
2862 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
2863 sdram_reg = SDRAM_INITPLR6;
2864 mfsdram(sdram_reg, sdram_data);
2865 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
2866 sdram_reg = SDRAM_INITPLR7;
2867 mfsdram(sdram_reg, sdram_data);
2868 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
2869 sdram_reg = SDRAM_INITPLR8;
2870 mfsdram(sdram_reg, sdram_data);
2871 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
2872 sdram_reg = SDRAM_INITPLR9;
2873 mfsdram(sdram_reg, sdram_data);
2874 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
2875 sdram_reg = SDRAM_INITPLR10;
2876 mfsdram(sdram_reg, sdram_data);
2877 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
2878 sdram_reg = SDRAM_INITPLR11;
2879 mfsdram(sdram_reg, sdram_data);
2880 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2881 sdram_reg = SDRAM_INITPLR12;
2882 mfsdram(sdram_reg, sdram_data);
2883 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
2884 sdram_reg = SDRAM_INITPLR13;
2885 mfsdram(sdram_reg, sdram_data);
2886 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2887 sdram_reg = SDRAM_INITPLR14;
2888 mfsdram(sdram_reg, sdram_data);
2889 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
2890 sdram_reg = SDRAM_INITPLR15;
2891 mfsdram(sdram_reg, sdram_data);
2892 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2893 sdram_reg = SDRAM_RQDC;
2894 mfsdram(sdram_reg, sdram_data);
2895 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
2896 sdram_reg = SDRAM_RFDC;
2897 mfsdram(sdram_reg, sdram_data);
2898 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
2899 sdram_reg = SDRAM_RDCC;
2900 mfsdram(sdram_reg, sdram_data);
2901 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
2902 sdram_reg = SDRAM_DLCR;
2903 mfsdram(sdram_reg, sdram_data);
2904 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
2905 sdram_reg = SDRAM_CLKTR;
2906 mfsdram(sdram_reg, sdram_data);
2907 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
2908 sdram_reg = SDRAM_WRDTR;
2909 mfsdram(sdram_reg, sdram_data);
2910 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
2911 sdram_reg = SDRAM_SDTR1;
2912 mfsdram(sdram_reg, sdram_data);
2913 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
2914 sdram_reg = SDRAM_SDTR2;
2915 mfsdram(sdram_reg, sdram_data);
2916 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
2917 sdram_reg = SDRAM_SDTR3;
2918 mfsdram(sdram_reg, sdram_data);
2919 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
2920 sdram_reg = SDRAM_MMODE;
2921 mfsdram(sdram_reg, sdram_data);
2922 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
2923 sdram_reg = SDRAM_MEMODE;
2924 mfsdram(sdram_reg, sdram_data);
2925 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
2926 sdram_reg = SDRAM_ECCCR;
2927 mfsdram(sdram_reg, sdram_data);
2928 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
2929
2930 dcr_data = mfdcr(SDRAM_R0BAS);
2931 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
2932 dcr_data = mfdcr(SDRAM_R1BAS);
2933 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
2934 dcr_data = mfdcr(SDRAM_R2BAS);
2935 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
2936 dcr_data = mfdcr(SDRAM_R3BAS);
2937 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
2938}
2939#endif
2940#endif /* CONFIG_SPD_EEPROM */
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