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c609719b | 1 | /* |
4d816774 | 2 | * (C) Copyright 2000-2003 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
c609719b WD |
25 | * CPU specific code |
26 | * | |
27 | * written or collected and sometimes rewritten by | |
28 | * Magnus Damm <damm@bitsmart.com> | |
29 | * | |
30 | * minor modifications by | |
31 | * Wolfgang Denk <wd@denx.de> | |
32 | */ | |
33 | ||
34 | #include <common.h> | |
35 | #include <watchdog.h> | |
36 | #include <command.h> | |
37 | #include <asm/cache.h> | |
38 | #include <ppc4xx.h> | |
39 | ||
40 | ||
41 | #if defined(CONFIG_440) | |
42 | static int do_chip_reset( unsigned long sys0, unsigned long sys1 ); | |
43 | #endif | |
44 | ||
45 | /* ------------------------------------------------------------------------- */ | |
46 | ||
47 | int checkcpu (void) | |
48 | { | |
b867d705 SR |
49 | #if defined(CONFIG_405GP) || \ |
50 | defined(CONFIG_405CR) || \ | |
12f34241 WD |
51 | defined(CONFIG_405EP) || \ |
52 | defined(CONFIG_440) || \ | |
53 | defined(CONFIG_IOP480) | |
c609719b WD |
54 | uint pvr = get_pvr(); |
55 | #endif | |
b867d705 SR |
56 | #if defined(CONFIG_405GP) || \ |
57 | defined(CONFIG_405CR) || \ | |
12f34241 WD |
58 | defined(CONFIG_405EP) || \ |
59 | defined(CONFIG_IOP480) | |
c609719b WD |
60 | DECLARE_GLOBAL_DATA_PTR; |
61 | ||
62 | ulong clock = gd->cpu_clk; | |
63 | char buf[32]; | |
64 | #endif | |
65 | ||
b867d705 | 66 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) |
c609719b WD |
67 | PPC405_SYS_INFO sys_info; |
68 | ||
69 | puts ("CPU: "); | |
70 | ||
71 | get_sys_info(&sys_info); | |
72 | ||
42dfe7a1 | 73 | #ifdef CONFIG_405GP |
4d816774 | 74 | puts ("IBM PowerPC 405GP"); |
baa3d528 | 75 | if (pvr == PVR_405GPR_RB) { |
c609719b WD |
76 | putc('r'); |
77 | } | |
4d816774 | 78 | puts (" Rev. "); |
c609719b | 79 | #endif |
42dfe7a1 | 80 | #ifdef CONFIG_405CR |
4d816774 | 81 | puts ("IBM PowerPC 405CR Rev. "); |
b867d705 | 82 | #endif |
42dfe7a1 | 83 | #ifdef CONFIG_405EP |
4d816774 | 84 | puts ("IBM PowerPC 405EP Rev. "); |
c609719b WD |
85 | #endif |
86 | switch (pvr) { | |
87 | case PVR_405GP_RB: | |
baa3d528 | 88 | case PVR_405GPR_RB: |
c609719b WD |
89 | putc('B'); |
90 | break; | |
91 | case PVR_405GP_RC: | |
42dfe7a1 | 92 | #ifdef CONFIG_405CR |
c609719b WD |
93 | case PVR_405CR_RC: |
94 | #endif | |
95 | putc('C'); | |
96 | break; | |
97 | case PVR_405GP_RD: | |
98 | putc('D'); | |
99 | break; | |
42dfe7a1 | 100 | #ifdef CONFIG_405GP |
c609719b WD |
101 | case PVR_405GP_RE: |
102 | putc('E'); | |
103 | break; | |
104 | #endif | |
105 | case PVR_405CR_RA: | |
c609719b WD |
106 | putc('A'); |
107 | break; | |
108 | case PVR_405CR_RB: | |
b867d705 | 109 | case PVR_405EP_RB: |
c609719b WD |
110 | putc('B'); |
111 | break; | |
112 | default: | |
4d816774 | 113 | printf ("? (PVR=%08x)", pvr); |
c609719b WD |
114 | break; |
115 | } | |
116 | ||
4d816774 | 117 | printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), |
c609719b WD |
118 | sys_info.freqPLB / 1000000, |
119 | sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, | |
120 | sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); | |
121 | ||
b867d705 | 122 | #if defined(CONFIG_405GP) |
4d816774 WD |
123 | if (mfdcr(strap) & PSR_PCI_ASYNC_EN) { |
124 | printf (" PCI async ext clock used, "); | |
125 | } else { | |
126 | printf (" PCI sync clock at %lu MHz, ", | |
c609719b | 127 | sys_info.freqPLB / sys_info.pllPciDiv / 1000000); |
4d816774 WD |
128 | } |
129 | printf ("%sternal PCI arbiter enabled\n", | |
130 | (mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex"); | |
b867d705 | 131 | #elif defined(CONFIG_405EP) |
4d816774 WD |
132 | printf (" IIC Boot EEPROM %sabled\n", |
133 | (mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis"); | |
134 | printf (" PCI async ext clock used, "); | |
135 | printf ("%sternal PCI arbiter enabled\n", | |
136 | (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex"); | |
c609719b WD |
137 | #endif |
138 | ||
b867d705 | 139 | #if defined(CONFIG_405EP) |
4d816774 | 140 | printf (" 16 kB I-Cache 16 kB D-Cache"); |
b867d705 | 141 | #else |
4d816774 WD |
142 | printf (" 16 kB I-Cache %d kB D-Cache", |
143 | ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); | |
b867d705 | 144 | #endif |
c609719b WD |
145 | #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ |
146 | ||
147 | #ifdef CONFIG_IOP480 | |
4d816774 WD |
148 | printf ("PLX IOP480 (PVR=%08x)", pvr); |
149 | printf (" at %s MHz:", strmhz(buf, clock)); | |
150 | printf (" %u kB I-Cache", 4); | |
151 | printf (" %u kB D-Cache", 2); | |
c609719b WD |
152 | #endif |
153 | ||
154 | #if defined(CONFIG_440) | |
ba56f625 | 155 | puts ("IBM PowerPC 440 G"); |
4d816774 | 156 | switch(pvr) { |
8bde7f77 | 157 | case PVR_440GP_RB: |
ba56f625 | 158 | puts("P Rev. B"); |
4d816774 WD |
159 | /* See errata 1.12: CHIP_4 */ |
160 | if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || | |
161 | (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ | |
162 | puts ( "\n\t CPC0_SYSx DCRs corrupted. " | |
163 | "Resetting chip ...\n"); | |
164 | udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ | |
165 | do_chip_reset ( mfdcr(cpc0_strp0), | |
166 | mfdcr(cpc0_strp1) ); | |
167 | } | |
c609719b | 168 | break; |
8bde7f77 | 169 | case PVR_440GP_RC: |
ba56f625 WD |
170 | puts("P Rev. C"); |
171 | break; | |
172 | case PVR_440GX_RA: | |
173 | puts("X Rev. A"); | |
174 | break; | |
175 | case PVR_440GX_RB: | |
176 | puts("X Rev. B"); | |
c609719b | 177 | break; |
8bde7f77 | 178 | default: |
4d816774 | 179 | printf ("UNKNOWN (PVR=%08x)", pvr); |
c609719b WD |
180 | break; |
181 | } | |
182 | #endif | |
4d816774 | 183 | puts ("\n"); |
c609719b WD |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
188 | ||
189 | /* ------------------------------------------------------------------------- */ | |
190 | ||
8bde7f77 | 191 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
c609719b | 192 | { |
8bde7f77 WD |
193 | /* |
194 | * Initiate system reset in debug control register DBCR | |
195 | */ | |
c609719b WD |
196 | __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); |
197 | #if defined(CONFIG_440) | |
198 | __asm__ __volatile__("mtspr 0x134, 3"); | |
199 | #else | |
200 | __asm__ __volatile__("mtspr 0x3f2, 3"); | |
201 | #endif | |
202 | return 1; | |
203 | } | |
204 | ||
205 | #if defined(CONFIG_440) | |
206 | static | |
4d816774 | 207 | int do_chip_reset (unsigned long sys0, unsigned long sys1) |
c609719b | 208 | { |
4d816774 WD |
209 | /* Changes to cpc0_sys0 and cpc0_sys1 require chip |
210 | * reset. | |
211 | */ | |
212 | mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ | |
213 | mtdcr (cpc0_sys0, sys0); | |
214 | mtdcr (cpc0_sys1, sys1); | |
215 | mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ | |
216 | mtspr (dbcr0, 0x20000000); /* Reset the chip */ | |
217 | ||
218 | return 1; | |
c609719b WD |
219 | } |
220 | #endif | |
221 | ||
222 | ||
223 | /* | |
224 | * Get timebase clock frequency | |
225 | */ | |
226 | unsigned long get_tbclk (void) | |
227 | { | |
228 | #if defined(CONFIG_440) | |
229 | ||
230 | sys_info_t sys_info; | |
231 | ||
232 | get_sys_info(&sys_info); | |
233 | return (sys_info.freqProcessor); | |
234 | ||
b867d705 SR |
235 | #elif defined(CONFIG_405GP) || \ |
236 | defined(CONFIG_405CR) || \ | |
237 | defined(CONFIG_405) || \ | |
238 | defined(CONFIG_405EP) | |
c609719b WD |
239 | |
240 | PPC405_SYS_INFO sys_info; | |
241 | ||
242 | get_sys_info(&sys_info); | |
243 | return (sys_info.freqProcessor); | |
244 | ||
245 | #elif defined(CONFIG_IOP480) | |
246 | ||
247 | return (66000000); | |
248 | ||
249 | #else | |
250 | ||
251 | # error get_tbclk() not implemented | |
252 | ||
253 | #endif | |
254 | ||
255 | } | |
256 | ||
257 | ||
258 | #if defined(CONFIG_WATCHDOG) | |
259 | void | |
260 | watchdog_reset(void) | |
261 | { | |
262 | int re_enable = disable_interrupts(); | |
263 | reset_4xx_watchdog(); | |
264 | if (re_enable) enable_interrupts(); | |
265 | } | |
266 | ||
267 | void | |
268 | reset_4xx_watchdog(void) | |
269 | { | |
270 | /* | |
271 | * Clear TSR(WIS) bit | |
272 | */ | |
273 | mtspr(tsr, 0x40000000); | |
274 | } | |
275 | #endif /* CONFIG_WATCHDOG */ |