[people/ms/u-boot.git] / cpu / ppc4xx / cpu.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <damm@bitsmart.com>
 *
 * minor modifications by
 * Wolfgang Denk <wd@denx.de>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>

#if !defined(CONFIG_405)
DECLARE_GLOBAL_DATA_PTR;
#endif


#if defined(CONFIG_440)
#define FREQ_EBC		(sys_info.freqEPB)
#else
#define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif

#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)

#define PCI_ASYNC

int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_440GP)
	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAE_MASK);
#endif
}
#endif

#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
	defined(CONFIG_440GX) || defined(CONFIG_440SP)

#define I2C_BOOTROM

int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
	unsigned long val;

	mfsdr(sdr_sdcs, val);
	return (val & SDR0_SDCS_SDD);
#endif
}
#endif


#if defined(CONFIG_440)
static int do_chip_reset(unsigned long sys0, unsigned long sys1);
#endif


int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];

#if !defined(CONFIG_IOP480)
	sys_info_t sys_info;

	puts ("CPU:   ");

	get_sys_info(&sys_info);

	puts("AMCC PowerPC 4");

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
	puts("05");
#endif
#if defined(CONFIG_440)
	puts("40");
#endif

	switch (pvr) {
	case PVR_405GP_RB:
		puts("GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("GP Rev. D");
		break;

#ifdef CONFIG_405GP
	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
		puts("GP Rev. E");
		break;
#endif

	case PVR_405CR_RA:
		puts("CR Rev. A");
		break;

	case PVR_405CR_RB:
		puts("CR Rev. B");
		break;

#ifdef CONFIG_405CR
	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
		puts("CR Rev. C");
		break;
#endif

	case PVR_405GPR_RB:
		puts("GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("EP Rev. B");
		break;

#if defined(CONFIG_440)
	case PVR_440GP_RB:
		puts("GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
			do_chip_reset ( mfdcr(cpc0_strp0),
					mfdcr(cpc0_strp1) );
		}
		break;

	case PVR_440GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_440GX_RA:
		puts("GX Rev. A");
		break;

	case PVR_440GX_RB:
		puts("GX Rev. B");
		break;

	case PVR_440GX_RC:
		puts("GX Rev. C");
		break;

	case PVR_440GX_RF:
		puts("GX Rev. F");
		break;

	case PVR_440EP_RA:
		puts("EP Rev. A");
		break;

#ifdef CONFIG_440EP
	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
		puts("EP Rev. B");
		break;
#endif /*  CONFIG_440EP */

#ifdef CONFIG_440GR
	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
		puts("GR Rev. A");
		break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */

	case PVR_440SP_RA:
		puts("SP Rev. A");
		break;

	case PVR_440SP_RB:
		puts("SP Rev. B");
		break;

	default:
		printf (" UNKNOWN (PVR=%08x)", pvr);
		break;
	}

	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
	       sys_info.freqPLB / 1000000,
	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
	       FREQ_EBC / 1000000);

#if defined(I2C_BOOTROM)
	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif

#if defined(CONFIG_PCI)
	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif

#if defined(PCI_ASYNC)
	if (pci_async_enabled()) {
		printf (", PCI async ext clock used");
	} else {
		printf (", PCI sync clock at %lu MHz",
		       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	}
#endif

#if defined(CONFIG_PCI)
	putc('\n');
#endif

#if defined(CONFIG_405EP)
	printf ("       16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
	printf ("       32 kB I-Cache 32 kB D-Cache");
#else
	printf ("       16 kB I-Cache %d kB D-Cache",
		((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */

#if defined(CONFIG_IOP480)
	printf ("PLX IOP480 (PVR=%08x)", pvr);
	printf (" at %s MHz:", strmhz(buf, clock));
	printf (" %u kB I-Cache", 4);
	printf (" %u kB D-Cache", 2);
#endif

#endif /* !defined(CONFIG_405) */

	putc ('\n');

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
	/*give reset to BCSR*/
	*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;

#else

	/*
	 * Initiate system reset in debug control register DBCR
	 */
	__asm__ __volatile__("lis   3, 0x3000" ::: "r3");
#if defined(CONFIG_440)
	__asm__ __volatile__("mtspr 0x134, 3");
#else
	__asm__ __volatile__("mtspr 0x3f2, 3");
#endif

#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
	return 1;
}

#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	 * reset.
	 */
	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
	mtdcr (cpc0_sys0, sys0);
	mtdcr (cpc0_sys1, sys1);
	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
	mtspr (dbcr0, 0x20000000);	/* Reset the chip */

	return 1;
}
#endif


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
#if !defined(CONFIG_IOP480)
	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return (sys_info.freqProcessor);
#else
	return (66000000);
#endif

}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_4xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_4xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit
	 */
	mtspr(tsr, 0x40000000);
}
#endif	/* CONFIG_WATCHDOG */
Commit	Line	Data
c609719b	1	/*
4d816774	2	* (C) Copyright 2000-2003
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
c609719b WD	25	* CPU specific code
	26	*
	27	* written or collected and sometimes rewritten by
	28	* Magnus Damm <damm@bitsmart.com>
	29	*
	30	* minor modifications by
	31	* Wolfgang Denk <wd@denx.de>
	32	*/
	33
	34	#include <common.h>
	35	#include <watchdog.h>
	36	#include <command.h>
	37	#include <asm/cache.h>
	38	#include <ppc4xx.h>
	39
d87080b7 WD	40	#if !defined(CONFIG_405)
	41	DECLARE_GLOBAL_DATA_PTR;
	42	#endif
	43
c609719b	44
6e7fb6ea SR	45	#if defined(CONFIG_440)
	46	#define FREQ_EBC (sys_info.freqEPB)
	47	#else
	48	#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
3d9569b2 SR	49	#endif
3d9569b2 SR	50
6e7fb6ea SR	51	#if defined(CONFIG_405GP) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	52
	53	#define PCI_ASYNC
	54
	55	int pci_async_enabled(void)
	56	{
	57	#if defined(CONFIG_405GP)
	58	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
3d9569b2 SR	59	#endif
	60
	61	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
6e7fb6ea SR	62	unsigned long val;
6e7fb6ea SR	63
7481266e	64	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	65	return (val & SDR0_SDSTP1_PAME_MASK);
	66	#endif
	67	}
	68	#endif
	69
a46726fd	70	#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
6e7fb6ea SR	71	int pci_arbiter_enabled(void)
	72	{
	73	#if defined(CONFIG_405GP)
	74	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
	75	#endif
3d9569b2	76
6e7fb6ea SR	77	#if defined(CONFIG_405EP)
6e7fb6ea SR	78	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
3d9569b2 SR	79	#endif
	80
	81	#if defined(CONFIG_440GP)
6e7fb6ea SR	82	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
	83	#endif
	84
	85	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| defined(CONFIG_440SP)
	86	unsigned long val;
3d9569b2	87
6e7fb6ea SR	88	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	89	return (val & SDR0_SDSTP1_PAE_MASK);
3d9569b2	90	#endif
6e7fb6ea SR	91	}
	92	#endif
	93
	94	#if defined(CONFIG_405EP)\|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
	95	defined(CONFIG_440GX) \|\| defined(CONFIG_440SP)
3d9569b2	96
6e7fb6ea	97	#define I2C_BOOTROM
3d9569b2	98
6e7fb6ea SR	99	int i2c_bootrom_enabled(void)
	100	{
	101	#if defined(CONFIG_405EP)
	102	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
3d9569b2 SR	103	#endif
3d9569b2 SR	104
6e7fb6ea SR	105	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| defined(CONFIG_440SP)
	106	unsigned long val;
	107
	108	mfsdr(sdr_sdcs, val);
	109	return (val & SDR0_SDCS_SDD);
	110	#endif
	111	}
3d9569b2 SR	112	#endif
	113
	114
c609719b	115	#if defined(CONFIG_440)
3d9569b2	116	static int do_chip_reset(unsigned long sys0, unsigned long sys1);
c609719b WD	117	#endif
c609719b WD	118
c609719b WD	119
	120	int checkcpu (void)
	121	{
3d9569b2	122	#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
3d9569b2	123	uint pvr = get_pvr();
c609719b WD	124	ulong clock = gd->cpu_clk;
c609719b WD	125	char buf[32];
c609719b	126
3d9569b2 SR	127	#if !defined(CONFIG_IOP480)
3d9569b2 SR	128	sys_info_t sys_info;
c609719b WD	129
	130	puts ("CPU: ");
	131
	132	get_sys_info(&sys_info);
	133
3d9569b2 SR	134	puts("AMCC PowerPC 4");
	135
	136	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405EP)
	137	puts("05");
b867d705	138	#endif
3d9569b2 SR	139	#if defined(CONFIG_440)
3d9569b2 SR	140	puts("40");
c609719b	141	#endif
3d9569b2	142
c609719b WD	143	switch (pvr) {
c609719b WD	144	case PVR_405GP_RB:
3d9569b2	145	puts("GP Rev. B");
c609719b	146	break;
3d9569b2	147
c609719b	148	case PVR_405GP_RC:
3d9569b2	149	puts("GP Rev. C");
c609719b	150	break;
3d9569b2	151
c609719b	152	case PVR_405GP_RD:
3d9569b2	153	puts("GP Rev. D");
c609719b	154	break;
3d9569b2	155
42dfe7a1	156	#ifdef CONFIG_405GP
3d9569b2 SR	157	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
3d9569b2 SR	158	puts("GP Rev. E");
c609719b WD	159	break;
c609719b WD	160	#endif
3d9569b2	161
c609719b	162	case PVR_405CR_RA:
3d9569b2	163	puts("CR Rev. A");
c609719b	164	break;
3d9569b2	165
c609719b	166	case PVR_405CR_RB:
3d9569b2	167	puts("CR Rev. B");
c609719b	168	break;
c609719b	169
3d9569b2 SR	170	#ifdef CONFIG_405CR
	171	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
	172	puts("CR Rev. C");
	173	break;
c609719b WD	174	#endif
c609719b WD	175
3d9569b2 SR	176	case PVR_405GPR_RB:
	177	puts("GPr Rev. B");
	178	break;
c609719b	179
3d9569b2 SR	180	case PVR_405EP_RB:
	181	puts("EP Rev. B");
	182	break;
c609719b WD	183
c609719b WD	184	#if defined(CONFIG_440)
8bde7f77	185	case PVR_440GP_RB:
c157d8e2	186	puts("GP Rev. B");
4d816774 WD	187	/* See errata 1.12: CHIP_4 */
	188	if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) \|\|
	189	(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
	190	puts ( "\n\t CPC0_SYSx DCRs corrupted. "
	191	"Resetting chip ...\n");
	192	udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
	193	do_chip_reset ( mfdcr(cpc0_strp0),
	194	mfdcr(cpc0_strp1) );
	195	}
c609719b	196	break;
3d9569b2	197
8bde7f77	198	case PVR_440GP_RC:
c157d8e2	199	puts("GP Rev. C");
ba56f625	200	break;
3d9569b2	201
ba56f625	202	case PVR_440GX_RA:
c157d8e2	203	puts("GX Rev. A");
ba56f625	204	break;
3d9569b2	205
ba56f625	206	case PVR_440GX_RB:
c157d8e2	207	puts("GX Rev. B");
c609719b	208	break;
3d9569b2	209
0a7c5391	210	case PVR_440GX_RC:
c157d8e2	211	puts("GX Rev. C");
0a7c5391	212	break;
3d9569b2	213
57275b69 SR	214	case PVR_440GX_RF:
	215	puts("GX Rev. F");
	216	break;
3d9569b2	217
c157d8e2 SR	218	case PVR_440EP_RA:
	219	puts("EP Rev. A");
	220	break;
3d9569b2	221
9a8d82fd SR	222	#ifdef CONFIG_440EP
9a8d82fd SR	223	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
c157d8e2 SR	224	puts("EP Rev. B");
c157d8e2 SR	225	break;
9a8d82fd	226	#endif /* CONFIG_440EP */
3d9569b2	227
9a8d82fd SR	228	#ifdef CONFIG_440GR
	229	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
	230	puts("GR Rev. A");
	231	break;
	232	#endif /* CONFIG_440GR */
3d9569b2 SR	233	#endif /* CONFIG_440 */
3d9569b2 SR	234
6e7fb6ea SR	235	case PVR_440SP_RA:
	236	puts("SP Rev. A");
	237	break;
	238
	239	case PVR_440SP_RB:
	240	puts("SP Rev. B");
	241	break;
	242
8bde7f77	243	default:
17f50f22	244	printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b WD	245	break;
c609719b WD	246	}
3d9569b2 SR	247
	248	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
	249	sys_info.freqPLB / 1000000,
	250	sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
	251	FREQ_EBC / 1000000);
	252
6e7fb6ea SR	253	#if defined(I2C_BOOTROM)
6e7fb6ea SR	254	printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
3d9569b2 SR	255	#endif
3d9569b2 SR	256
6e7fb6ea SR	257	#if defined(CONFIG_PCI)
6e7fb6ea SR	258	printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2 SR	259	#endif
3d9569b2 SR	260
6e7fb6ea SR	261	#if defined(PCI_ASYNC)
6e7fb6ea SR	262	if (pci_async_enabled()) {
3d9569b2 SR	263	printf (", PCI async ext clock used");
	264	} else {
	265	printf (", PCI sync clock at %lu MHz",
	266	sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	267	}
c609719b	268	#endif
3d9569b2	269
6e7fb6ea	270	#if defined(CONFIG_PCI)
3d9569b2 SR	271	putc('\n');
	272	#endif
	273
	274	#if defined(CONFIG_405EP)
	275	printf (" 16 kB I-Cache 16 kB D-Cache");
	276	#elif defined(CONFIG_440)
	277	printf (" 32 kB I-Cache 32 kB D-Cache");
	278	#else
	279	printf (" 16 kB I-Cache %d kB D-Cache",
	280	((pvr \| 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
	281	#endif
	282	#endif /* !defined(CONFIG_IOP480) */
	283
	284	#if defined(CONFIG_IOP480)
	285	printf ("PLX IOP480 (PVR=%08x)", pvr);
	286	printf (" at %s MHz:", strmhz(buf, clock));
	287	printf (" %u kB I-Cache", 4);
	288	printf (" %u kB D-Cache", 2);
	289	#endif
	290
	291	#endif /* !defined(CONFIG_405) */
	292
	293	putc ('\n');
c609719b WD	294
	295	return 0;
	296	}
	297
	298
	299	/* ------------------------------------------------------------------------- */
	300
8bde7f77	301	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
c609719b	302	{
c157d8e2 SR	303	#if defined(CONFIG_YOSEMITE) \|\| defined(CONFIG_YELLOWSTONE)
	304	/give reset to BCSR/
	305	(unsigned char)(CFG_BCSR_BASE \| 0x06) = 0x09;
	306
	307	#else
	308
8bde7f77 WD	309	/*
	310	* Initiate system reset in debug control register DBCR
	311	*/
c609719b WD	312	__asm__ __volatile__("lis 3, 0x3000" ::: "r3");
	313	#if defined(CONFIG_440)
	314	__asm__ __volatile__("mtspr 0x134, 3");
	315	#else
	316	__asm__ __volatile__("mtspr 0x3f2, 3");
	317	#endif
c157d8e2 SR	318
c157d8e2 SR	319	#endif/* defined(CONFIG_YOSEMITE) \|\| defined(CONFIG_YELLOWSTONE)*/
c609719b WD	320	return 1;
	321	}
	322
	323	#if defined(CONFIG_440)
3d9569b2	324	static int do_chip_reset (unsigned long sys0, unsigned long sys1)
c609719b	325	{
4d816774 WD	326	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	327	* reset.
	328	*/
	329	mtdcr (cntrl0, mfdcr (cntrl0) \| 0x80000000); /* Set SWE */
	330	mtdcr (cpc0_sys0, sys0);
	331	mtdcr (cpc0_sys1, sys1);
	332	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
	333	mtspr (dbcr0, 0x20000000); /* Reset the chip */
	334
	335	return 1;
c609719b WD	336	}
	337	#endif
	338
	339
	340	/*
	341	* Get timebase clock frequency
	342	*/
	343	unsigned long get_tbclk (void)
	344	{
3d9569b2	345	#if !defined(CONFIG_IOP480)
c609719b WD	346	sys_info_t sys_info;
	347
	348	get_sys_info(&sys_info);
	349	return (sys_info.freqProcessor);
c609719b	350	#else
3d9569b2	351	return (66000000);
c609719b WD	352	#endif
	353
	354	}
	355
	356
	357	#if defined(CONFIG_WATCHDOG)
	358	void
	359	watchdog_reset(void)
	360	{
	361	int re_enable = disable_interrupts();
	362	reset_4xx_watchdog();
	363	if (re_enable) enable_interrupts();
	364	}
	365
	366	void
	367	reset_4xx_watchdog(void)
	368	{
	369	/*
	370	* Clear TSR(WIS) bit
	371	*/
	372	mtspr(tsr, 0x40000000);
	373	}
	374	#endif /* CONFIG_WATCHDOG */