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4a9cbbe8 | 1 | /* |
a4c8d138 | 2 | * (C) Copyright 2000-2006 |
4a9cbbe8 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <watchdog.h> | |
d6c61aab | 26 | #include <ppc4xx_enet.h> |
4a9cbbe8 WD |
27 | #include <asm/processor.h> |
28 | #include <ppc4xx.h> | |
29 | ||
d87080b7 WD |
30 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | #endif | |
33 | ||
4a9cbbe8 WD |
34 | |
35 | #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) | |
36 | ||
37208785 SR |
37 | #ifdef CFG_INIT_DCACHE_CS |
38 | # if (CFG_INIT_DCACHE_CS == 0) | |
39 | # define PBxAP pb0ap | |
40 | # define PBxCR pb0cr | |
41 | # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) | |
42 | # define PBxAP_VAL CFG_EBC_PB0AP | |
43 | # define PBxCR_VAL CFG_EBC_PB0CR | |
44 | # endif | |
45 | # endif | |
46 | # if (CFG_INIT_DCACHE_CS == 1) | |
47 | # define PBxAP pb1ap | |
48 | # define PBxCR pb1cr | |
49 | # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) | |
50 | # define PBxAP_VAL CFG_EBC_PB1AP | |
51 | # define PBxCR_VAL CFG_EBC_PB1CR | |
52 | # endif | |
53 | # endif | |
54 | # if (CFG_INIT_DCACHE_CS == 2) | |
55 | # define PBxAP pb2ap | |
56 | # define PBxCR pb2cr | |
57 | # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) | |
58 | # define PBxAP_VAL CFG_EBC_PB2AP | |
59 | # define PBxCR_VAL CFG_EBC_PB2CR | |
60 | # endif | |
61 | # endif | |
62 | # if (CFG_INIT_DCACHE_CS == 3) | |
63 | # define PBxAP pb3ap | |
64 | # define PBxCR pb3cr | |
65 | # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) | |
66 | # define PBxAP_VAL CFG_EBC_PB3AP | |
67 | # define PBxCR_VAL CFG_EBC_PB3CR | |
68 | # endif | |
69 | # endif | |
70 | # if (CFG_INIT_DCACHE_CS == 4) | |
71 | # define PBxAP pb4ap | |
72 | # define PBxCR pb4cr | |
73 | # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) | |
74 | # define PBxAP_VAL CFG_EBC_PB4AP | |
75 | # define PBxCR_VAL CFG_EBC_PB4CR | |
76 | # endif | |
77 | # endif | |
78 | # if (CFG_INIT_DCACHE_CS == 5) | |
79 | # define PBxAP pb5ap | |
80 | # define PBxCR pb5cr | |
81 | # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) | |
82 | # define PBxAP_VAL CFG_EBC_PB5AP | |
83 | # define PBxCR_VAL CFG_EBC_PB5CR | |
84 | # endif | |
85 | # endif | |
86 | # if (CFG_INIT_DCACHE_CS == 6) | |
87 | # define PBxAP pb6ap | |
88 | # define PBxCR pb6cr | |
89 | # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) | |
90 | # define PBxAP_VAL CFG_EBC_PB6AP | |
91 | # define PBxCR_VAL CFG_EBC_PB6CR | |
92 | # endif | |
93 | # endif | |
94 | # if (CFG_INIT_DCACHE_CS == 7) | |
95 | # define PBxAP pb7ap | |
96 | # define PBxCR pb7cr | |
97 | # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) | |
98 | # define PBxAP_VAL CFG_EBC_PB7AP | |
99 | # define PBxCR_VAL CFG_EBC_PB7CR | |
100 | # endif | |
101 | # endif | |
102 | #endif /* CFG_INIT_DCACHE_CS */ | |
103 | ||
a4c8d138 SR |
104 | #if defined(CFG_440_GPIO_TABLE) |
105 | gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; | |
106 | ||
107 | void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX]) | |
108 | { | |
109 | unsigned char i=0, j=0, reg_offset = 0, gpio_core; | |
110 | unsigned long gpio_reg, gpio_core_add; | |
111 | ||
112 | for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) { | |
113 | j = 0; | |
114 | reg_offset = 0; | |
115 | /* GPIO config of the GPIOs 0 to 31 */ | |
116 | for (i=0; i<GPIO_MAX; i++, j++) { | |
117 | if (i == GPIO_MAX/2) { | |
118 | reg_offset = 4; | |
119 | j = i-16; | |
120 | } | |
121 | ||
122 | gpio_core_add = (*gpio_tab)[gpio_core][i].add; | |
123 | ||
124 | if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) || | |
125 | ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { | |
126 | ||
127 | switch ((*gpio_tab)[gpio_core][i].alt_nb) { | |
128 | case GPIO_SEL: | |
129 | break; | |
130 | ||
131 | case GPIO_ALT1: | |
132 | gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) | |
133 | & ~(GPIO_MASK >> (j*2)); | |
134 | gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); | |
135 | out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); | |
136 | break; | |
137 | ||
138 | case GPIO_ALT2: | |
139 | gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) | |
140 | & ~(GPIO_MASK >> (j*2)); | |
141 | gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); | |
142 | out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); | |
143 | break; | |
144 | ||
145 | case GPIO_ALT3: | |
146 | gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) | |
147 | & ~(GPIO_MASK >> (j*2)); | |
148 | gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); | |
149 | out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); | |
150 | break; | |
151 | } | |
152 | } | |
153 | ||
154 | if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) || | |
155 | ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { | |
156 | ||
157 | switch ((*gpio_tab)[gpio_core][i].alt_nb) { | |
158 | case GPIO_SEL: | |
159 | if (gpio_core == GPIO0) { | |
160 | gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j)); | |
161 | out32(GPIO0_TCR, gpio_reg); | |
162 | } | |
163 | ||
164 | if (gpio_core == GPIO1) { | |
165 | gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j)); | |
166 | out32(GPIO1_TCR, gpio_reg); | |
167 | } | |
168 | ||
169 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) | |
170 | & ~(GPIO_MASK >> (j*2)); | |
171 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); | |
172 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) | |
173 | & ~(GPIO_MASK >> (j*2)); | |
174 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); | |
175 | break; | |
176 | ||
177 | case GPIO_ALT1: | |
178 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) | |
179 | & ~(GPIO_MASK >> (j*2)); | |
180 | gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); | |
181 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); | |
182 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) | |
183 | & ~(GPIO_MASK >> (j*2)); | |
184 | gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); | |
185 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); | |
186 | break; | |
187 | ||
188 | case GPIO_ALT2: | |
189 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) | |
190 | & ~(GPIO_MASK >> (j*2)); | |
191 | gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); | |
192 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); | |
193 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) | |
194 | & ~(GPIO_MASK >> (j*2)); | |
195 | gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); | |
196 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); | |
197 | break; | |
198 | ||
199 | case GPIO_ALT3: | |
200 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) | |
201 | & ~(GPIO_MASK >> (j*2)); | |
202 | gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); | |
203 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); | |
204 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) | |
205 | & ~(GPIO_MASK >> (j*2)); | |
206 | gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); | |
207 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); | |
208 | break; | |
209 | } | |
210 | } | |
211 | } | |
212 | } | |
213 | } | |
214 | #endif /* CFG_440_GPIO_TABLE */ | |
4a9cbbe8 WD |
215 | |
216 | /* | |
217 | * Breath some life into the CPU... | |
218 | * | |
219 | * Set up the memory map, | |
220 | * initialize a bunch of registers | |
221 | */ | |
222 | void | |
223 | cpu_init_f (void) | |
224 | { | |
b867d705 SR |
225 | #if defined(CONFIG_405EP) |
226 | /* | |
227 | * GPIO0 setup (select GPIO or alternate function) | |
228 | */ | |
e0a46554 SR |
229 | #if defined(CFG_GPIO0_OR) |
230 | out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */ | |
231 | #endif | |
232 | #if defined(CFG_GPIO0_ODR) | |
233 | out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */ | |
234 | #endif | |
235 | out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ | |
b867d705 | 236 | out32(GPIO0_OSRL, CFG_GPIO0_OSRL); |
e0a46554 | 237 | out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ |
b867d705 | 238 | out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); |
e0a46554 | 239 | out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ |
b867d705 | 240 | out32(GPIO0_TSRL, CFG_GPIO0_TSRL); |
e0a46554 | 241 | out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ |
b867d705 SR |
242 | |
243 | /* | |
244 | * Set EMAC noise filter bits | |
245 | */ | |
246 | mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); | |
247 | #endif /* CONFIG_405EP */ | |
248 | ||
a4c8d138 SR |
249 | #if defined(CFG_440_GPIO_TABLE) |
250 | set_chip_gpio_configuration(&gpio_tab); | |
251 | #endif /* CFG_440_GPIO_TABLE */ | |
252 | ||
4a9cbbe8 WD |
253 | /* |
254 | * External Bus Controller (EBC) Setup | |
255 | */ | |
256 | #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) | |
a4c8d138 SR |
257 | #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
258 | defined(CONFIG_405EP) || defined(CONFIG_405)) | |
4a9cbbe8 WD |
259 | /* |
260 | * Move the next instructions into icache, since these modify the flash | |
261 | * we are running from! | |
262 | */ | |
263 | asm volatile(" bl 0f" ::: "lr"); | |
264 | asm volatile("0: mflr 3" ::: "r3"); | |
265 | asm volatile(" addi 4, 0, 14" ::: "r4"); | |
266 | asm volatile(" mtctr 4" ::: "ctr"); | |
267 | asm volatile("1: icbt 0, 3"); | |
268 | asm volatile(" addi 3, 3, 32" ::: "r3"); | |
269 | asm volatile(" bdnz 1b" ::: "ctr", "cr0"); | |
270 | asm volatile(" addis 3, 0, 0x0" ::: "r3"); | |
271 | asm volatile(" ori 3, 3, 0xA000" ::: "r3"); | |
272 | asm volatile(" mtctr 3" ::: "ctr"); | |
273 | asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); | |
a4c8d138 | 274 | #endif |
4a9cbbe8 WD |
275 | |
276 | mtebc(pb0ap, CFG_EBC_PB0AP); | |
277 | mtebc(pb0cr, CFG_EBC_PB0CR); | |
278 | #endif | |
279 | ||
37208785 | 280 | #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1)) |
4a9cbbe8 WD |
281 | mtebc(pb1ap, CFG_EBC_PB1AP); |
282 | mtebc(pb1cr, CFG_EBC_PB1CR); | |
283 | #endif | |
284 | ||
37208785 | 285 | #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2)) |
4a9cbbe8 WD |
286 | mtebc(pb2ap, CFG_EBC_PB2AP); |
287 | mtebc(pb2cr, CFG_EBC_PB2CR); | |
288 | #endif | |
289 | ||
37208785 | 290 | #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3)) |
4a9cbbe8 WD |
291 | mtebc(pb3ap, CFG_EBC_PB3AP); |
292 | mtebc(pb3cr, CFG_EBC_PB3CR); | |
293 | #endif | |
294 | ||
37208785 | 295 | #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) |
4a9cbbe8 WD |
296 | mtebc(pb4ap, CFG_EBC_PB4AP); |
297 | mtebc(pb4cr, CFG_EBC_PB4CR); | |
298 | #endif | |
299 | ||
37208785 | 300 | #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5)) |
4a9cbbe8 WD |
301 | mtebc(pb5ap, CFG_EBC_PB5AP); |
302 | mtebc(pb5cr, CFG_EBC_PB5CR); | |
303 | #endif | |
304 | ||
37208785 | 305 | #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6)) |
4a9cbbe8 WD |
306 | mtebc(pb6ap, CFG_EBC_PB6AP); |
307 | mtebc(pb6cr, CFG_EBC_PB6CR); | |
308 | #endif | |
309 | ||
37208785 | 310 | #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7)) |
4a9cbbe8 WD |
311 | mtebc(pb7ap, CFG_EBC_PB7AP); |
312 | mtebc(pb7cr, CFG_EBC_PB7CR); | |
313 | #endif | |
314 | ||
315 | #if defined(CONFIG_WATCHDOG) | |
316 | unsigned long val; | |
317 | ||
318 | val = mfspr(tcr); | |
846b0dd2 | 319 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
320 | val |= 0xb8000000; /* generate system reset after 1.34 seconds */ |
321 | #else | |
4a9cbbe8 | 322 | val |= 0xf0000000; /* generate system reset after 2.684 seconds */ |
1c2ce226 SR |
323 | #endif |
324 | #if defined(CFG_4xx_RESET_TYPE) | |
325 | val &= ~0x30000000; /* clear WRC bits */ | |
326 | val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ | |
c157d8e2 | 327 | #endif |
4a9cbbe8 WD |
328 | mtspr(tcr, val); |
329 | ||
330 | val = mfspr(tsr); | |
331 | val |= 0x80000000; /* enable watchdog timer */ | |
332 | mtspr(tsr, val); | |
333 | ||
334 | reset_4xx_watchdog(); | |
335 | #endif /* CONFIG_WATCHDOG */ | |
336 | } | |
337 | ||
338 | /* | |
339 | * initialize higher level parts of CPU like time base and timers | |
340 | */ | |
341 | int cpu_init_r (void) | |
342 | { | |
b867d705 | 343 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
4a9cbbe8 WD |
344 | bd_t *bd = gd->bd; |
345 | unsigned long reg; | |
b867d705 | 346 | #if defined(CONFIG_405GP) |
38daa27d | 347 | uint pvr = get_pvr(); |
b867d705 | 348 | #endif |
4a9cbbe8 | 349 | |
37208785 SR |
350 | #ifdef CFG_INIT_DCACHE_CS |
351 | /* | |
352 | * Flush and invalidate dcache, then disable CS for temporary stack. | |
353 | * Afterwards, this CS can be used for other purposes | |
354 | */ | |
355 | dcache_disable(); /* flush and invalidate dcache */ | |
356 | mtebc(PBxAP, 0); | |
357 | mtebc(PBxCR, 0); /* disable CS for temporary stack */ | |
358 | ||
359 | #if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) | |
360 | /* | |
361 | * Write new value into CS register | |
362 | */ | |
363 | mtebc(PBxAP, PBxAP_VAL); | |
364 | mtebc(PBxCR, PBxCR_VAL); | |
365 | #endif | |
366 | #endif /* CFG_INIT_DCACHE_CS */ | |
367 | ||
4a9cbbe8 WD |
368 | /* |
369 | * Write Ethernetaddress into on-chip register | |
370 | */ | |
371 | reg = 0x00000000; | |
372 | reg |= bd->bi_enetaddr[0]; /* set high address */ | |
373 | reg = reg << 8; | |
374 | reg |= bd->bi_enetaddr[1]; | |
375 | out32 (EMAC_IAH, reg); | |
376 | ||
377 | reg = 0x00000000; | |
378 | reg |= bd->bi_enetaddr[2]; /* set low address */ | |
379 | reg = reg << 8; | |
380 | reg |= bd->bi_enetaddr[3]; | |
381 | reg = reg << 8; | |
382 | reg |= bd->bi_enetaddr[4]; | |
383 | reg = reg << 8; | |
384 | reg |= bd->bi_enetaddr[5]; | |
385 | out32 (EMAC_IAL, reg); | |
38daa27d | 386 | |
b867d705 | 387 | #if defined(CONFIG_405GP) |
38daa27d SR |
388 | /* |
389 | * Set edge conditioning circuitry on PPC405GPr | |
390 | * for compatibility to existing PPC405GP designs. | |
391 | */ | |
baa3d528 | 392 | if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { |
38daa27d SR |
393 | mtdcr(ecr, 0x60606000); |
394 | } | |
b867d705 SR |
395 | #endif /* defined(CONFIG_405GP) */ |
396 | #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ | |
4a9cbbe8 WD |
397 | return (0); |
398 | } |