[people/ms/u-boot.git] / cpu / ppc4xx / i2c.c

/*****************************************************************************/
/* I2C Bus interface initialisation and I2C Commands                         */
/* for PPC405GP		                                                     */
/* Author : AS HARNOIS                                                       */
/* Date   : 13.Dec.00                                                        */
/*****************************************************************************/

#include <common.h>
#include <ppc4xx.h>
#if defined(CONFIG_440)
#   include <440_i2c.h>
#else
#   include <405gp_i2c.h>
#endif
#include <i2c.h>

#ifdef CONFIG_HARD_I2C

#define IIC_OK		0
#define IIC_NOK		1
#define IIC_NOK_LA	2		/* Lost arbitration */
#define IIC_NOK_ICT	3		/* Incomplete transfer */
#define IIC_NOK_XFRA	4		/* Transfer aborted */
#define IIC_NOK_DATA	5		/* No data in buffer */
#define IIC_NOK_TOUT	6		/* Transfer timeout */

#define IIC_TIMEOUT 1			/* 1 seconde */


static void _i2c_bus_reset (void)
{
	int i, status;

	/* Reset status register */
	/* write 1 in SCMP and IRQA to clear these fields */
	out8 (IIC_STS, 0x0A);

	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	out8 (IIC_EXTSTS, 0x8F);
	__asm__ volatile ("eieio");

	/*
	 * Get current state, reset bus
	 * only if no transfers are pending.
	 */
	i = 10;
	do {
		/* Get status */
		status = in8 (IIC_STS);
		udelay (500);			/* 500us */
		i--;
	} while ((status & IIC_STS_PT) && (i > 0));
	/* Soft reset controller */
	status = in8 (IIC_XTCNTLSS);
	out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
	__asm__ volatile ("eieio");

	/* make sure where in initial state, data hi, clock hi */
	out8 (IIC_DIRECTCNTL, 0xC);
	for (i = 0; i < 10; i++) {
		if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
			/* clock until we get to known state */
			out8 (IIC_DIRECTCNTL, 0x8);	/* clock lo */
			udelay (100);		/* 100us */
			out8 (IIC_DIRECTCNTL, 0xC);	/* clock hi */
			udelay (100);		/* 100us */
		} else {
			break;
		}
	}
	/* send start condition */
	out8 (IIC_DIRECTCNTL, 0x4);
	udelay (1000);				/* 1ms */
	/* send stop condition */
	out8 (IIC_DIRECTCNTL, 0xC);
	udelay (1000);				/* 1ms */
	/* Unreset controller */
	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
	udelay (1000);				/* 1ms */
}

void i2c_init (int speed, int slaveadd)
{
	sys_info_t sysInfo;
	unsigned long freqOPB;
	int val, divisor;

#ifdef CFG_I2C_INIT_BOARD        
	/* call board specific i2c bus reset routine before accessing the   */
	/* environment, which might be in a chip on that bus. For details   */
	/* about this problem see doc/I2C_Edge_Conditions.                  */
	i2c_init_board();
#endif

	/* Handle possible failed I2C state */
	/* FIXME: put this into i2c_init_board()? */
	_i2c_bus_reset ();

	/* clear lo master address */
	out8 (IIC_LMADR, 0);

	/* clear hi master address */
	out8 (IIC_HMADR, 0);

	/* clear lo slave address */
	out8 (IIC_LSADR, 0);

	/* clear hi slave address */
	out8 (IIC_HSADR, 0);

	/* Clock divide Register */
	/* get OPB frequency */
	get_sys_info (&sysInfo);
	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	/* set divisor according to freqOPB */
	divisor = (freqOPB - 1) / 10000000;
	if (divisor == 0)
		divisor = 1;
	out8 (IIC_CLKDIV, divisor);

	/* no interrupts */
	out8 (IIC_INTRMSK, 0);

	/* clear transfer count */
	out8 (IIC_XFRCNT, 0);

	/* clear extended control & stat */
	/* write 1 in SRC SRS SWC SWS to clear these fields */
	out8 (IIC_XTCNTLSS, 0xF0);

	/* Mode Control Register
	   Flush Slave/Master data buffer */
	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
	__asm__ volatile ("eieio");


        val = in8(IIC_MDCNTL);
        __asm__ volatile ("eieio");

        /* Ignore General Call, slave transfers are ignored,
           disable interrupts, exit unknown bus state, enable hold
           SCL
           100kHz normaly or FastMode for 400kHz and above
        */

        val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
        if( speed >= 400000 ){
                val |= IIC_MDCNTL_FSM;
        }
	out8 (IIC_MDCNTL, val);

	/* clear control reg */
	out8 (IIC_CNTL, 0x00);
	__asm__ volatile ("eieio");

}

/*
  This code tries to use the features of the 405GP i2c
  controller. It will transfer up to 4 bytes in one pass
  on the loop. It only does out8(lbz) to the buffer when it
  is possible to do out16(lhz) transfers.

  cmd_type is 0 for write 1 for read.

  addr_len can take any value from 0-255, it is only limited
  by the char, we could make it larger if needed. If it is
  0 we skip the address write cycle.

  Typical case is a Write of an addr followd by a Read. The
  IBM FAQ does not cover this. On the last byte of the write
  we don't set the creg CHT bit, and on the first bytes of the
  read we set the RPST bit.

  It does not support address only transfers, there must be
  a data part. If you want to write the address yourself, put
  it in the data pointer.

  It does not support transfer to/from address 0.

  It does not check XFRCNT.
*/
static
int i2c_transfer(unsigned char cmd_type,
                 unsigned char chip,
                 unsigned char addr[],
                 unsigned char addr_len,
                 unsigned char data[],
		 unsigned short data_len )
{
        unsigned char* ptr;
        int reading;
        int tran,cnt;
        int result;
        int status;
        int i;
        uchar creg;

        if( data == 0 || data_len == 0 ){
                /*Don't support data transfer of no length or to address 0*/
                printf( "i2c_transfer: bad call\n" );
                return IIC_NOK;
        }
        if( addr && addr_len ){
                ptr = addr;
                cnt = addr_len;
                reading = 0;
        }else{
                ptr = data;
                cnt = data_len;
                reading = cmd_type;
        }

        /*Clear Stop Complete Bit*/
        out8(IIC_STS,IIC_STS_SCMP);
        /* Check init */
        i=10;
        do {
                /* Get status */
                status = in8(IIC_STS);
                __asm__ volatile("eieio");
                i--;
        } while ((status & IIC_STS_PT) && (i>0));

        if (status & IIC_STS_PT) {
                result = IIC_NOK_TOUT;
                return(result);
        }
        /*flush the Master/Slave Databuffers*/
        out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
        /*need to wait 4 OPB clocks? code below should take that long*/

        /* 7-bit adressing */
        out8(IIC_HMADR,0);
        out8(IIC_LMADR, chip);
        __asm__ volatile("eieio");

        tran = 0;
        result = IIC_OK;
        creg = 0;

        while ( tran != cnt && (result == IIC_OK)) {
                int  bc,j;

                /* Control register =
                   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
                   Transfer is a sequence of transfers
                */
                creg |= IIC_CNTL_PT;

                bc = (cnt - tran) > 4 ? 4 :
                        cnt - tran;
                creg |= (bc-1)<<4;
                /* if the real cmd type is write continue trans*/
                if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
                        creg |= IIC_CNTL_CHT;

                if (reading)
                        creg |= IIC_CNTL_READ;
                else {
                        for(j=0; j<bc; j++) {
                                /* Set buffer */
                                out8(IIC_MDBUF,ptr[tran+j]);
                                __asm__ volatile("eieio");
                        }
                }
                out8(IIC_CNTL, creg );
                __asm__ volatile("eieio");

                /* Transfer is in progress
                   we have to wait for upto 5 bytes of data
                   1 byte chip address+r/w bit then bc bytes
                   of data.
                   udelay(10) is 1 bit time at 100khz
                   Doubled for slop. 20 is too small.
		*/
                i=2*5*8;
                do {
                        /* Get status */
                        status = in8(IIC_STS);
                        __asm__ volatile("eieio");
                        udelay (10);
                        i--;
                } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
			 && (i>0));

                if (status & IIC_STS_ERR) {
                        result = IIC_NOK;
                        status = in8 (IIC_EXTSTS);
                        /* Lost arbitration? */
                        if (status & IIC_EXTSTS_LA)
                                result = IIC_NOK_LA;
                        /* Incomplete transfer? */
                        if (status & IIC_EXTSTS_ICT)
                                result = IIC_NOK_ICT;
                        /* Transfer aborted? */
                        if (status & IIC_EXTSTS_XFRA)
                                result = IIC_NOK_XFRA;
                } else if ( status & IIC_STS_PT) {
                        result = IIC_NOK_TOUT;
                }
                /* Command is reading => get buffer */
                if ((reading) && (result == IIC_OK)) {
                        /* Are there data in buffer */
                        if (status & IIC_STS_MDBS) {
                                /*
                                  even if we have data we have to wait 4OPB clocks
                                  for it to hit the front of the FIFO, after that
                                  we can just read. We should check XFCNT here and
                                  if the FIFO is full there is no need to wait.
				*/
                                udelay (1);
                                for(j=0;j<bc;j++) {
                                        ptr[tran+j] = in8(IIC_MDBUF);
                                        __asm__ volatile("eieio");
                                }
                        } else
                                result = IIC_NOK_DATA;
                }
                creg = 0;
                tran+=bc;
                if( ptr == addr && tran == cnt ) {
                        ptr = data;
                        cnt = data_len;
                        tran = 0;
                        reading = cmd_type;
                        if( reading )
                                creg = IIC_CNTL_RPST;
                }
        }
        return (result);
}

int i2c_probe (uchar chip)
{
	uchar buf[1];

	buf[0] = 0;

        /*
         * What is needed is to send the chip address and verify that the
         * address was <ACK>ed (i.e. there was a chip at that address which
         * drove the data line low).
         */
        return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
}


int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
        uchar xaddr[4];
        int ret;

	if ( alen > 4 ) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

        if ( alen > 0 ) {
                xaddr[0] = (addr >> 24) & 0xFF;
                xaddr[1] = (addr >> 16) & 0xFF;
                xaddr[2] = (addr >> 8) & 0xFF;
                xaddr[3] = addr & 0xFF;
        }


#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
         * EEPROM chips that implement "address overflow" are ones
         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
         * address and the extra bits end up in the "chip address"
         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
         * four 256 byte chips.
	 *
         * Note that we consider the length of the address field to
         * still be one byte because the extra address bits are
         * hidden in the chip address.
	 */
        if( alen > 0 )
                chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif
        if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
                printf( "I2c read: failed %d\n", ret);
                return 1;
        }
        return 0;
}

int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
        uchar xaddr[4];

	if ( alen > 4 ) {
		printf ("I2C write: addr len %d not supported\n", alen);
		return 1;

	}
        if ( alen > 0 ) {
                xaddr[0] = (addr >> 24) & 0xFF;
                xaddr[1] = (addr >> 16) & 0xFF;
                xaddr[2] = (addr >> 8) & 0xFF;
                xaddr[3] = addr & 0xFF;
        }

#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
         * EEPROM chips that implement "address overflow" are ones
         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
         * address and the extra bits end up in the "chip address"
         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
         * four 256 byte chips.
	 *
         * Note that we consider the length of the address field to
         * still be one byte because the extra address bits are
         * hidden in the chip address.
	 */
        if( alen > 0 )
                chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif

        return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
}

/*-----------------------------------------------------------------------
 * Read a register
 */
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
	char buf;

	i2c_read(i2c_addr, reg, 1, &buf, 1);

	return(buf);
}

/*-----------------------------------------------------------------------
 * Write a register
 */
void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
	i2c_write(i2c_addr, reg, 1, &val, 1);
}
#endif	/* CONFIG_HARD_I2C */
Commit	Line	Data
c609719b WD	1	/*****************************************************************************/
	2	/* I2C Bus interface initialisation and I2C Commands */
	3	/* for PPC405GP */
	4	/* Author : AS HARNOIS */
	5	/* Date : 13.Dec.00 */
	6	/*****************************************************************************/
	7
	8	#include <common.h>
	9	#include <ppc4xx.h>
	10	#if defined(CONFIG_440)
	11	# include <440_i2c.h>
	12	#else
	13	# include <405gp_i2c.h>
	14	#endif
	15	#include <i2c.h>
	16
	17	#ifdef CONFIG_HARD_I2C
	18
	19	#define IIC_OK 0
	20	#define IIC_NOK 1
	21	#define IIC_NOK_LA 2 /* Lost arbitration */
	22	#define IIC_NOK_ICT 3 /* Incomplete transfer */
	23	#define IIC_NOK_XFRA 4 /* Transfer aborted */
	24	#define IIC_NOK_DATA 5 /* No data in buffer */
	25	#define IIC_NOK_TOUT 6 /* Transfer timeout */
	26
	27	#define IIC_TIMEOUT 1 /* 1 seconde */
	28
	29
	30	static void _i2c_bus_reset (void)
	31	{
	32	int i, status;
	33
	34	/* Reset status register */
	35	/* write 1 in SCMP and IRQA to clear these fields */
	36	out8 (IIC_STS, 0x0A);
	37
	38	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	39	out8 (IIC_EXTSTS, 0x8F);
	40	__asm__ volatile ("eieio");
	41
	42	/*
	43	* Get current state, reset bus
	44	* only if no transfers are pending.
	45	*/
	46	i = 10;
	47	do {
	48	/* Get status */
	49	status = in8 (IIC_STS);
	50	udelay (500); /* 500us */
	51	i--;
	52	} while ((status & IIC_STS_PT) && (i > 0));
	53	/* Soft reset controller */
	54	status = in8 (IIC_XTCNTLSS);
	55	out8 (IIC_XTCNTLSS, (status \| IIC_XTCNTLSS_SRST));
	56	__asm__ volatile ("eieio");
	57
	58	/* make sure where in initial state, data hi, clock hi */
	59	out8 (IIC_DIRECTCNTL, 0xC);
	60	for (i = 0; i < 10; i++) {
	61	if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
	62	/* clock until we get to known state */
	63	out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */
	64	udelay (100); /* 100us */
65	out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */
66	udelay (100); /* 100us */
67	} else {
68	break;
69	}
70	}
71	/* send start condition */
72	out8 (IIC_DIRECTCNTL, 0x4);
73	udelay (1000); /* 1ms */
74	/* send stop condition */
75	out8 (IIC_DIRECTCNTL, 0xC);
76	udelay (1000); /* 1ms */
77	/* Unreset controller */
78	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
79	udelay (1000); /* 1ms */
80	}
81
82	void i2c_init (int speed, int slaveadd)
83	{
84	sys_info_t sysInfo;
85	unsigned long freqOPB;
86	int val, divisor;
87
47cd00fa WD	88	#ifdef CFG_I2C_INIT_BOARD
	89	/* call board specific i2c bus reset routine before accessing the */
	90	/* environment, which might be in a chip on that bus. For details */
	91	/* about this problem see doc/I2C_Edge_Conditions. */
	92	i2c_init_board();
	93	#endif
	94
c609719b	95	/* Handle possible failed I2C state */
47cd00fa	96	/* FIXME: put this into i2c_init_board()? */
c609719b WD	97	_i2c_bus_reset ();
	98
	99	/* clear lo master address */
	100	out8 (IIC_LMADR, 0);
	101
	102	/* clear hi master address */
	103	out8 (IIC_HMADR, 0);
	104
	105	/* clear lo slave address */
	106	out8 (IIC_LSADR, 0);
	107
	108	/* clear hi slave address */
	109	out8 (IIC_HSADR, 0);
	110
	111	/* Clock divide Register */
	112	/* get OPB frequency */
	113	get_sys_info (&sysInfo);
	114	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	115	/* set divisor according to freqOPB */
	116	divisor = (freqOPB - 1) / 10000000;
	117	if (divisor == 0)
	118	divisor = 1;
	119	out8 (IIC_CLKDIV, divisor);
	120
	121	/* no interrupts */
	122	out8 (IIC_INTRMSK, 0);
	123
	124	/* clear transfer count */
	125	out8 (IIC_XFRCNT, 0);
	126
	127	/* clear extended control & stat */
	128	/* write 1 in SRC SRS SWC SWS to clear these fields */
	129	out8 (IIC_XTCNTLSS, 0xF0);
	130
	131	/* Mode Control Register
	132	Flush Slave/Master data buffer */
	133	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB \| IIC_MDCNTL_FMDB);
	134	__asm__ volatile ("eieio");
	135
	136
	137	val = in8(IIC_MDCNTL);
	138	__asm__ volatile ("eieio");
	139
	140	/* Ignore General Call, slave transfers are ignored,
	141	disable interrupts, exit unknown bus state, enable hold
	142	SCL
	143	100kHz normaly or FastMode for 400kHz and above
	144	*/
	145
	146	val \|= IIC_MDCNTL_EUBS\|IIC_MDCNTL_HSCL;
	147	if( speed >= 400000 ){
	148	val \|= IIC_MDCNTL_FSM;
	149	}
	150	out8 (IIC_MDCNTL, val);
	151
	152	/* clear control reg */
	153	out8 (IIC_CNTL, 0x00);
	154	__asm__ volatile ("eieio");
	155
	156	}
	157
	158	/*
	159	This code tries to use the features of the 405GP i2c
	160	controller. It will transfer up to 4 bytes in one pass
161	on the loop. It only does out8(lbz) to the buffer when it
162	is possible to do out16(lhz) transfers.
163
164	cmd_type is 0 for write 1 for read.
165
166	addr_len can take any value from 0-255, it is only limited
167	by the char, we could make it larger if needed. If it is
168	0 we skip the address write cycle.
169
170	Typical case is a Write of an addr followd by a Read. The
171	IBM FAQ does not cover this. On the last byte of the write
172	we don't set the creg CHT bit, and on the first bytes of the
173	read we set the RPST bit.
174
175	It does not support address only transfers, there must be
176	a data part. If you want to write the address yourself, put
177	it in the data pointer.
178
179	It does not support transfer to/from address 0.
180
181	It does not check XFRCNT.
182	*/
183	static
184	int i2c_transfer(unsigned char cmd_type,
185	unsigned char chip,
186	unsigned char addr[],
187	unsigned char addr_len,
188	unsigned char data[],
189	unsigned short data_len )
190	{
191	unsigned char* ptr;
192	int reading;
193	int tran,cnt;
194	int result;
195	int status;
196	int i;
197	uchar creg;
198
199	if( data == 0 \|\| data_len == 0 ){
200	/Don't support data transfer of no length or to address 0/
201	printf( "i2c_transfer: bad call\n" );
202	return IIC_NOK;
203	}
204	if( addr && addr_len ){
205	ptr = addr;
206	cnt = addr_len;
207	reading = 0;
208	}else{
209	ptr = data;
210	cnt = data_len;
211	reading = cmd_type;
212	}
213
214	/Clear Stop Complete Bit/
215	out8(IIC_STS,IIC_STS_SCMP);
216	/* Check init */
217	i=10;
218	do {
219	/* Get status */
220	status = in8(IIC_STS);
221	__asm__ volatile("eieio");
222	i--;
223	} while ((status & IIC_STS_PT) && (i>0));
224
225	if (status & IIC_STS_PT) {
226	result = IIC_NOK_TOUT;
227	return(result);
228	}
229	/flush the Master/Slave Databuffers/
230	out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))\|IIC_MDCNTL_FMDB\|IIC_MDCNTL_FSDB));
231	/need to wait 4 OPB clocks? code below should take that long/
232
233	/* 7-bit adressing */
234	out8(IIC_HMADR,0);
235	out8(IIC_LMADR, chip);
236	__asm__ volatile("eieio");
237
238	tran = 0;
239	result = IIC_OK;
240	creg = 0;
241
242	while ( tran != cnt && (result == IIC_OK)) {
243	int bc,j;
244
245	/* Control register =
246	Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
247	Transfer is a sequence of transfers
248	*/
249	creg \|= IIC_CNTL_PT;
250
251	bc = (cnt - tran) > 4 ? 4 :
252	cnt - tran;
253	creg \|= (bc-1)<<4;
254	/* if the real cmd type is write continue trans*/
255	if ( (!cmd_type && (ptr == addr)) \|\| ((tran+bc) != cnt) )
256	creg \|= IIC_CNTL_CHT;
257
258	if (reading)
259	creg \|= IIC_CNTL_READ;
260	else {
261	for(j=0; j<bc; j++) {
262	/* Set buffer */
263	out8(IIC_MDBUF,ptr[tran+j]);
264	__asm__ volatile("eieio");
265	}
266	}
267	out8(IIC_CNTL, creg );
268	__asm__ volatile("eieio");
269
270	/* Transfer is in progress
271	we have to wait for upto 5 bytes of data
272	1 byte chip address+r/w bit then bc bytes
273	of data.
274	udelay(10) is 1 bit time at 100khz
275	Doubled for slop. 20 is too small.
276	*/
277	i=258;
278	do {
279	/* Get status */
280	status = in8(IIC_STS);
281	__asm__ volatile("eieio");
282	udelay (10);
283	i--;
284	} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
285	&& (i>0));
286
287	if (status & IIC_STS_ERR) {
288	result = IIC_NOK;
289	status = in8 (IIC_EXTSTS);
290	/* Lost arbitration? */
291	if (status & IIC_EXTSTS_LA)
292	result = IIC_NOK_LA;
293	/* Incomplete transfer? */
294	if (status & IIC_EXTSTS_ICT)
295	result = IIC_NOK_ICT;
296	/* Transfer aborted? */
297	if (status & IIC_EXTSTS_XFRA)
298	result = IIC_NOK_XFRA;
299	} else if ( status & IIC_STS_PT) {
300	result = IIC_NOK_TOUT;
301	}
302	/* Command is reading => get buffer */
303	if ((reading) && (result == IIC_OK)) {
304	/* Are there data in buffer */
305	if (status & IIC_STS_MDBS) {
306	/*
307	even if we have data we have to wait 4OPB clocks
308	for it to hit the front of the FIFO, after that
309	we can just read. We should check XFCNT here and
310	if the FIFO is full there is no need to wait.
311	*/
312	udelay (1);
313	for(j=0;j<bc;j++) {
314	ptr[tran+j] = in8(IIC_MDBUF);
315	__asm__ volatile("eieio");
316	}
317	} else
318	result = IIC_NOK_DATA;
319	}
320	creg = 0;
321	tran+=bc;
322	if( ptr == addr && tran == cnt ) {
323	ptr = data;
324	cnt = data_len;
325	tran = 0;
326	reading = cmd_type;
327	if( reading )
328	creg = IIC_CNTL_RPST;
329	}
330	}
331	return (result);
332	}
333
334	int i2c_probe (uchar chip)
335	{
336	uchar buf[1];
337
338	buf[0] = 0;
339
340	/*
341	* What is needed is to send the chip address and verify that the
342	* address was <ACK>ed (i.e. there was a chip at that address which
343	* drove the data line low).
344	*/
345	return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
346	}
347
348
349
350	int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
351	{
352	uchar xaddr[4];
353	int ret;
354
355	if ( alen > 4 ) {
356	printf ("I2C read: addr len %d not supported\n", alen);
357	return 1;
358	}
359
360	if ( alen > 0 ) {
361	xaddr[0] = (addr >> 24) & 0xFF;
362	xaddr[1] = (addr >> 16) & 0xFF;
363	xaddr[2] = (addr >> 8) & 0xFF;
364	xaddr[3] = addr & 0xFF;
365	}
366
367
368	#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
369	/*
370	* EEPROM chips that implement "address overflow" are ones
371	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
372	* address and the extra bits end up in the "chip address"
373	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
374	* four 256 byte chips.
375	*
376	* Note that we consider the length of the address field to
377	* still be one byte because the extra address bits are
378	* hidden in the chip address.
379	*/
380	if( alen > 0 )
381	chip \|= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
382	#endif
383	if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
384	printf( "I2c read: failed %d\n", ret);
385	return 1;
386	}
387	return 0;
388	}
389
390	int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
391	{
392	uchar xaddr[4];
393
394	if ( alen > 4 ) {
395	printf ("I2C write: addr len %d not supported\n", alen);
396	return 1;
397
398	}
399	if ( alen > 0 ) {
400	xaddr[0] = (addr >> 24) & 0xFF;
401	xaddr[1] = (addr >> 16) & 0xFF;
402	xaddr[2] = (addr >> 8) & 0xFF;
403	xaddr[3] = addr & 0xFF;
404	}
405
406	#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
407	/*
408	* EEPROM chips that implement "address overflow" are ones
409	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
410	* address and the extra bits end up in the "chip address"
411	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
412	* four 256 byte chips.
413	*
414	* Note that we consider the length of the address field to
415	* still be one byte because the extra address bits are
416	* hidden in the chip address.
417	*/
418	if( alen > 0 )
419	chip \|= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
420	#endif
421
422	return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
423	}
424
1cb8e980 WD	425	/*-----------------------------------------------------------------------
	426	* Read a register
	427	*/
	428	uchar i2c_reg_read(uchar i2c_addr, uchar reg)
	429	{
	430	char buf;
	431
	432	i2c_read(i2c_addr, reg, 1, &buf, 1);
	433
	434	return(buf);
	435	}
	436
	437	/*-----------------------------------------------------------------------
	438	* Write a register
	439	*/
	440	void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
	441	{
	442	i2c_write(i2c_addr, reg, 1, &val, 1);
	443	}
c609719b	444	#endif /* CONFIG_HARD_I2C */