[people/ms/u-boot.git] / cpu / ppc4xx / interrupts.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2002 (440 port)
 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
#include "vecnum.h"

/****************************************************************************/

unsigned decrementer_count;		/* count value for 1e6/HZ microseconds */

/****************************************************************************/

/*
 * CPM interrupt vector functions.
 */
struct	irq_action {
	interrupt_handler_t *handler;
	void *arg;
	int count;
};

static struct irq_action irq_vecs[32];

#if defined(CONFIG_440)
static struct irq_action irq_vecs1[32]; /* For UIC1 */

void uic1_interrupt( void * parms); /* UIC1 handler */
#endif

/****************************************************************************/

static __inline__ unsigned long get_msr(void)
{
	unsigned long msr;

	asm volatile("mfmsr %0" : "=r" (msr) :);
	return msr;
}

static __inline__ void set_msr(unsigned long msr)
{
	asm volatile("mtmsr %0" : : "r" (msr));
}

#if defined(CONFIG_440)

/* SPRN changed in 440 */
static __inline__ void set_evpr(unsigned long val)
{
	asm volatile("mtspr 0x03f,%0" : : "r" (val));
}

#else /* !defined(CONFIG_440) */

static __inline__ unsigned long get_dec(void)
{
	unsigned long val;

	asm volatile("mfdec %0" : "=r" (val) :);
	return val;
}


static __inline__ void set_dec(unsigned long val)
{
	asm volatile("mtdec %0" : : "r" (val));
}


static __inline__ void set_pit(unsigned long val)
{
	asm volatile("mtpit %0" : : "r" (val));
}


static __inline__ void set_tcr(unsigned long val)
{
	asm volatile("mttcr %0" : : "r" (val));
}


static __inline__ void set_evpr(unsigned long val)
{
	asm volatile("mtevpr %0" : : "r" (val));
}
#endif /* defined(CONFIG_440 */


void enable_interrupts (void)
{
	set_msr (get_msr() | MSR_EE);
}

/* returns flag if MSR_EE was set before */
int disable_interrupts (void)
{
	ulong msr = get_msr();
	set_msr (msr & ~MSR_EE);
	return ((msr & MSR_EE) != 0);
}

/****************************************************************************/

int interrupt_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;

	int vec;
	unsigned long val;

	/*
	 * Mark all irqs as free
	 */
	for (vec=0; vec<32; vec++) {
		irq_vecs[vec].handler = NULL;
		irq_vecs[vec].arg = NULL;
		irq_vecs[vec].count = 0;
#if defined(CONFIG_440)
		irq_vecs1[vec].handler = NULL;
		irq_vecs1[vec].arg = NULL;
		irq_vecs1[vec].count = 0;
#endif
	}

#ifdef CONFIG_4xx
	/*
	 * Init PIT
	 */
#if defined(CONFIG_440)
	val = mfspr( tcr );
	val &= (~0x04400000);		/* clear DIS & ARE */
	mtspr( tcr, val );
	mtspr( dec, 0 );		/* Prevent exception after TSR clear*/
	mtspr( decar, 0 );		/* clear reload */
	mtspr( tsr, 0x08000000 );	/* clear DEC status */
	val = gd->bd->bi_intfreq/100;	/* 10 msec */
	mtspr( decar, val );		/* Set auto-reload value */
	mtspr( dec, val );		/* Set inital val */
#else
	set_pit(gd->bd->bi_intfreq / 1000);
#endif
#endif  /* CONFIG_4xx */

#ifdef CONFIG_ADCIOP
	/*
	 * Init PIT
	 */
	set_pit(66000);
#endif

	/*
	 * Enable PIT
	 */
	val = mfspr(tcr);
	val |= 0x04400000;
	mtspr(tcr, val);

	/*
	 * Set EVPR to 0
	 */
	set_evpr(0x00000000);

#if defined(CONFIG_440)
	/* Install the UIC1 handlers */
	irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
	irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
#endif
	/*
	 * Enable external interrupts (including PIT)
	 */
	set_msr (get_msr() | MSR_EE);

	return (0);
}

/****************************************************************************/

/*
 * Handle external interrupts
 */
void external_interrupt(struct pt_regs *regs)
{
	ulong uic_msr;
	ulong msr_shift;
	int vec;

	/*
	 * Read masked interrupt status register to determine interrupt source
	 */
	uic_msr = mfdcr(uicmsr);
	msr_shift = uic_msr;
	vec = 0;

	while (msr_shift != 0) {
		if (msr_shift & 0x80000000) {
			/*
			 * Increment irq counter (for debug purpose only)
			 */
			irq_vecs[vec].count++;

			if (irq_vecs[vec].handler != NULL) {
				/* call isr */
				(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
			} else {
				mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
				printf ("Masking bogus interrupt vector 0x%x\n", vec);
			}

			/*
			 * After servicing the interrupt, we have to remove the status indicator.
			 */
			mtdcr(uicsr, (0x80000000 >> vec));
		}

		/*
		 * Shift msr to next position and increment vector
		 */
		msr_shift <<= 1;
		vec++;
	}
}

#if defined(CONFIG_440)
/* Handler for UIC1 interrupt */
void uic1_interrupt( void * parms)
{
	ulong uic1_msr;
	ulong msr_shift;
	int vec;

	/*
	 * Read masked interrupt status register to determine interrupt source
	 */
	uic1_msr = mfdcr(uic1msr);
	msr_shift = uic1_msr;
	vec = 0;

	while (msr_shift != 0) {
		if (msr_shift & 0x80000000) {
			/*
			 * Increment irq counter (for debug purpose only)
			 */
			irq_vecs1[vec].count++;

			if (irq_vecs1[vec].handler != NULL) {
				/* call isr */
				(*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
			} else {
				mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
				printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
			}

			/*
			 * After servicing the interrupt, we have to remove the status indicator.
			 */
			mtdcr(uic1sr, (0x80000000 >> vec));
		}

		/*
		 * Shift msr to next position and increment vector
		 */
		msr_shift <<= 1;
		vec++;
	}
}
#endif /* defined(CONFIG_440) */

/****************************************************************************/

/*
 * Install and free a interrupt handler.
 */

void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
	struct irq_action *irqa = irq_vecs;
	int   i = vec;

#if defined(CONFIG_440)
	if (vec > 31) {
		i = vec - 32;
		irqa = irq_vecs1;
	}
#endif

	if (irqa[i].handler != NULL) {
		printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
			vec, (uint)handler, (uint)irqa[i].handler);
	}
	irqa[i].handler = handler;
	irqa[i].arg     = arg;

#if defined(CONFIG_440)
	if( vec > 31 )
		mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
	else
#endif
		mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
#if 0
	printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
#endif
}

void
irq_free_handler(int vec)
{
	struct irq_action *irqa = irq_vecs;
	int   i = vec;

#if defined(CONFIG_440)
	if (vec > 31) {
		irqa = irq_vecs1;
		i = vec - 32;
	}
#endif

#if 0
	printf ("Free interrupt for vector %d ==> %p\n",
		vec, irq_vecs[vec].handler);
#endif

#if defined(CONFIG_440)
	if (vec > 31)
		mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
	else
#endif
		mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));

	irqa[i].handler = NULL;
	irqa[i].arg     = NULL;
}

/****************************************************************************/


volatile ulong timestamp = 0;

/*
 * timer_interrupt - gets called when the decrementer overflows,
 * with interrupts disabled.
 * Trivial implementation - no need to be really accurate.
 */
void timer_interrupt(struct pt_regs *regs)
{
#if 0
	printf ("*** Timer Interrupt *** ");
#endif
	timestamp++;

#if defined(CONFIG_WATCHDOG)
	if ((timestamp % 1000) == 0)
		reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
}

/****************************************************************************/

void reset_timer (void)
{
	timestamp = 0;
}

ulong get_timer (ulong base)
{
	return (timestamp - base);
}

void set_timer (ulong t)
{
	timestamp = t;
}

/****************************************************************************/


#if (CONFIG_COMMANDS & CFG_CMD_IRQ)

/*******************************************************************************
 *
 * irqinfo - print information about PCI devices
 *
 */
int
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int vec;

	printf ("\nInterrupt-Information:\n");
#if defined(CONFIG_440)
	printf ("\nUIC 0\n");
#endif
	printf ("Nr  Routine   Arg       Count\n");

	for (vec=0; vec<32; vec++) {
		if (irq_vecs[vec].handler != NULL) {
			printf ("%02d  %08lx  %08lx  %d\n",
				vec,
				(ulong)irq_vecs[vec].handler,
				(ulong)irq_vecs[vec].arg,
				irq_vecs[vec].count);
		}
	}

#if defined(CONFIG_440)
	printf ("\nUIC 1\n");
	printf ("Nr  Routine   Arg       Count\n");

	for (vec=0; vec<32; vec++)
	{
		if (irq_vecs1[vec].handler != NULL)
			printf ("%02d  %08lx  %08lx  %d\n",
				vec+31, (ulong)irq_vecs1[vec].handler,
				(ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
	}
	printf("\n");
#endif
	return 0;
}


#endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */
Commit	Line	Data
f780aa2a WD	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2002 (440 port)
	6	* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <watchdog.h>
	29	#include <command.h>
f780aa2a WD	30	#include <asm/processor.h>
	31	#include <ppc4xx.h>
	32	#include <ppc_asm.tmpl>
	33	#include <commproc.h>
	34	#include "vecnum.h"
	35
	36	/****************************************************************************/
	37
	38	unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
	39
	40	/****************************************************************************/
	41
	42	/*
	43	* CPM interrupt vector functions.
	44	*/
	45	struct irq_action {
	46	interrupt_handler_t *handler;
	47	void *arg;
	48	int count;
	49	};
	50
	51	static struct irq_action irq_vecs[32];
	52
	53	#if defined(CONFIG_440)
	54	static struct irq_action irq_vecs1[32]; /* For UIC1 */
	55
	56	void uic1_interrupt( void * parms); /* UIC1 handler */
	57	#endif
	58
	59	/****************************************************************************/
	60
	61	static __inline__ unsigned long get_msr(void)
	62	{
	63	unsigned long msr;
	64
	65	asm volatile("mfmsr %0" : "=r" (msr) :);
	66	return msr;
	67	}
	68
	69	static __inline__ void set_msr(unsigned long msr)
	70	{
	71	asm volatile("mtmsr %0" : : "r" (msr));
	72	}
	73
	74	#if defined(CONFIG_440)
	75
	76	/* SPRN changed in 440 */
	77	static __inline__ void set_evpr(unsigned long val)
	78	{
	79	asm volatile("mtspr 0x03f,%0" : : "r" (val));
	80	}
	81
	82	#else /* !defined(CONFIG_440) */
	83
	84	static __inline__ unsigned long get_dec(void)
	85	{
	86	unsigned long val;
	87
	88	asm volatile("mfdec %0" : "=r" (val) :);
	89	return val;
	90	}
	91
	92
	93	static __inline__ void set_dec(unsigned long val)
94	{
95	asm volatile("mtdec %0" : : "r" (val));
96	}
97
98
99	static __inline__ void set_pit(unsigned long val)
100	{
101	asm volatile("mtpit %0" : : "r" (val));
102	}
103
104
105	static __inline__ void set_tcr(unsigned long val)
106	{
107	asm volatile("mttcr %0" : : "r" (val));
108	}
109
110
111	static __inline__ void set_evpr(unsigned long val)
112	{
113	asm volatile("mtevpr %0" : : "r" (val));
114	}
115	#endif /* defined(CONFIG_440 */
116
117
118	void enable_interrupts (void)
119	{
120	set_msr (get_msr() \| MSR_EE);
121	}
122
123	/* returns flag if MSR_EE was set before */
124	int disable_interrupts (void)
125	{
126	ulong msr = get_msr();
127	set_msr (msr & ~MSR_EE);
128	return ((msr & MSR_EE) != 0);
129	}
130
131	/****************************************************************************/
132
133	int interrupt_init(void)
134	{
135	DECLARE_GLOBAL_DATA_PTR;
136
137	int vec;
138	unsigned long val;
139
140	/*
141	* Mark all irqs as free
142	*/
143	for (vec=0; vec<32; vec++) {
144	irq_vecs[vec].handler = NULL;
145	irq_vecs[vec].arg = NULL;
146	irq_vecs[vec].count = 0;
147	#if defined(CONFIG_440)
148	irq_vecs1[vec].handler = NULL;
149	irq_vecs1[vec].arg = NULL;
150	irq_vecs1[vec].count = 0;
151	#endif
152	}
153
154	#ifdef CONFIG_4xx
155	/*
156	* Init PIT
157	*/
158	#if defined(CONFIG_440)
159	val = mfspr( tcr );
160	val &= (~0x04400000); /* clear DIS & ARE */
161	mtspr( tcr, val );
162	mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
163	mtspr( decar, 0 ); /* clear reload */
164	mtspr( tsr, 0x08000000 ); /* clear DEC status */
165	val = gd->bd->bi_intfreq/100; /* 10 msec */
166	mtspr( decar, val ); /* Set auto-reload value */
167	mtspr( dec, val ); /* Set inital val */
168	#else
169	set_pit(gd->bd->bi_intfreq / 1000);
170	#endif
171	#endif /* CONFIG_4xx */
172
173	#ifdef CONFIG_ADCIOP
174	/*
175	* Init PIT
176	*/
177	set_pit(66000);
178	#endif
179
180	/*
181	* Enable PIT
182	*/
183	val = mfspr(tcr);
184	val \|= 0x04400000;
185	mtspr(tcr, val);
186
187	/*
188	* Set EVPR to 0
189	*/
190	set_evpr(0x00000000);
191
192	#if defined(CONFIG_440)
193	/* Install the UIC1 handlers */
194	irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
195	irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
196	#endif
197	/*
198	* Enable external interrupts (including PIT)
199	*/
200	set_msr (get_msr() \| MSR_EE);
201
202	return (0);
203	}
204
205	/****************************************************************************/
206
207	/*
208	* Handle external interrupts
209	*/
210	void external_interrupt(struct pt_regs *regs)
211	{
212	ulong uic_msr;
213	ulong msr_shift;
214	int vec;
215
216	/*
217	* Read masked interrupt status register to determine interrupt source
218	*/
219	uic_msr = mfdcr(uicmsr);
220	msr_shift = uic_msr;
221	vec = 0;
222
223	while (msr_shift != 0) {
224	if (msr_shift & 0x80000000) {
225	/*
226	* Increment irq counter (for debug purpose only)
227	*/
228	irq_vecs[vec].count++;
229
230	if (irq_vecs[vec].handler != NULL) {
231	/* call isr */
232	(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
233	} else {
234	mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
235	printf ("Masking bogus interrupt vector 0x%x\n", vec);
236	}
237
238	/*
239	* After servicing the interrupt, we have to remove the status indicator.
240	*/
241	mtdcr(uicsr, (0x80000000 >> vec));
242	}
243
244	/*
245	* Shift msr to next position and increment vector
246	*/
247	msr_shift <<= 1;
248	vec++;
249	}
250	}
251
252	#if defined(CONFIG_440)
253	/* Handler for UIC1 interrupt */
254	void uic1_interrupt( void * parms)
255	{
256	ulong uic1_msr;
257	ulong msr_shift;
258	int vec;
259
260	/*
261	* Read masked interrupt status register to determine interrupt source
262	*/
263	uic1_msr = mfdcr(uic1msr);
264	msr_shift = uic1_msr;
265	vec = 0;
266
267	while (msr_shift != 0) {
268	if (msr_shift & 0x80000000) {
269	/*
270	* Increment irq counter (for debug purpose only)
271	*/
272	irq_vecs1[vec].count++;
273
274	if (irq_vecs1[vec].handler != NULL) {
275	/* call isr */
276	(*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
277	} else {
278	mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
279	printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
280	}
281
282	/*
283	* After servicing the interrupt, we have to remove the status indicator.
284	*/
285	mtdcr(uic1sr, (0x80000000 >> vec));
286	}
287
288	/*
289	* Shift msr to next position and increment vector
290	*/
291	msr_shift <<= 1;
292	vec++;
293	}
294	}
295	#endif /* defined(CONFIG_440) */
296
297	/****************************************************************************/
298
299	/*
300	* Install and free a interrupt handler.
301	*/
302
303	void
304	irq_install_handler(int vec, interrupt_handler_t handler, void arg)
305	{
306	struct irq_action *irqa = irq_vecs;
307	int i = vec;
308
309	#if defined(CONFIG_440)
310	if (vec > 31) {
311	i = vec - 32;
312	irqa = irq_vecs1;
313	}
314	#endif
315
316	if (irqa[i].handler != NULL) {
317	printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
318	vec, (uint)handler, (uint)irqa[i].handler);
319	}
320	irqa[i].handler = handler;
321	irqa[i].arg = arg;
322
323	#if defined(CONFIG_440)
324	if( vec > 31 )
325	mtdcr(uic1er, mfdcr(uic1er) \| (0x80000000 >> i));
326	else
327	#endif
328	mtdcr(uicer, mfdcr(uicer) \| (0x80000000 >> i));
329	#if 0
330	printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
331	#endif
332	}
333
334	void
335	irq_free_handler(int vec)
336	{
337	struct irq_action *irqa = irq_vecs;
338	int i = vec;
339
340	#if defined(CONFIG_440)
341	if (vec > 31) {
342	irqa = irq_vecs1;
343	i = vec - 32;
344	}
345	#endif
346
347	#if 0
348	printf ("Free interrupt for vector %d ==> %p\n",
349	vec, irq_vecs[vec].handler);
350	#endif
351
352	#if defined(CONFIG_440)
353	if (vec > 31)
354	mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
355	else
356	#endif
357	mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
358
359	irqa[i].handler = NULL;
360	irqa[i].arg = NULL;
361	}
362
363	/****************************************************************************/
364
365
366	volatile ulong timestamp = 0;
367
368	/*
369	* timer_interrupt - gets called when the decrementer overflows,
370	* with interrupts disabled.
371	* Trivial implementation - no need to be really accurate.
372	*/
373	void timer_interrupt(struct pt_regs *regs)
374	{
375	#if 0
376	printf ("* Timer Interrupt * ");
377	#endif
378	timestamp++;
379
380	#if defined(CONFIG_WATCHDOG)
381	if ((timestamp % 1000) == 0)
382	reset_4xx_watchdog();
383	#endif /* CONFIG_WATCHDOG */
384	}
385
386	/****************************************************************************/
387
388	void reset_timer (void)
389	{
390	timestamp = 0;
391	}
392
393	ulong get_timer (ulong base)
394	{
395	return (timestamp - base);
396	}
397
398	void set_timer (ulong t)
399	{
400	timestamp = t;
401	}
402
403	/****************************************************************************/
404
405
406	#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
407
408	/*******************************************************************************
409	*
410	* irqinfo - print information about PCI devices
411	*
412	*/
413	int
414	do_irqinfo(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
415	{
416	int vec;
417
418	printf ("\nInterrupt-Information:\n");
419	#if defined(CONFIG_440)
420	printf ("\nUIC 0\n");
421	#endif
422	printf ("Nr Routine Arg Count\n");
423
424	for (vec=0; vec<32; vec++) {
425	if (irq_vecs[vec].handler != NULL) {
426	printf ("%02d %08lx %08lx %d\n",
427	vec,
428	(ulong)irq_vecs[vec].handler,
429	(ulong)irq_vecs[vec].arg,
430	irq_vecs[vec].count);
431	}
432	}
433
434	#if defined(CONFIG_440)
435	printf ("\nUIC 1\n");
436	printf ("Nr Routine Arg Count\n");
437
438	for (vec=0; vec<32; vec++)
439	{
440	if (irq_vecs1[vec].handler != NULL)
441	printf ("%02d %08lx %08lx %d\n",
442	vec+31, (ulong)irq_vecs1[vec].handler,
443	(ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
444	}
445	printf("\n");
446	#endif
447	return 0;
448	}
449
450
451	#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */