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Patches by David Snowdon, 07 Sep 2004:
[people/ms/u-boot.git] / cpu / ppc4xx / serial.c
CommitLineData
fe8c2806
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23/*------------------------------------------------------------------------------+ */
24/*
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
31 *
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
35 *
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
39 *
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 */
43/*------------------------------------------------------------------------------- */
44
45#include <common.h>
46#include <commproc.h>
47#include <asm/processor.h>
48#include <watchdog.h>
49#include "vecnum.h"
50
42dfe7a1 51#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 52#include <malloc.h>
53#endif
54
55/*****************************************************************************/
56#ifdef CONFIG_IOP480
57
58#define SPU_BASE 0x40000000
59
60#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
61#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
62#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
63#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
64#define spu_BRateDivh 0x10 /* Baud rate divisor high */
65#define spu_BRateDivl 0x14 /* Baud rate divisor low */
66#define spu_CtlReg 0x18 /* Control Register */
67#define spu_RxCmd 0x1c /* Rx Command Register */
68#define spu_TxCmd 0x20 /* Tx Command Register */
69#define spu_RxBuff 0x24 /* Rx data buffer */
70#define spu_TxBuff 0x24 /* Tx data buffer */
71
72/*-----------------------------------------------------------------------------+
73 | Line Status Register.
74 +-----------------------------------------------------------------------------*/
75#define asyncLSRport1 0x40000000
76#define asyncLSRport1set 0x40000004
77#define asyncLSRDataReady 0x80
78#define asyncLSRFramingError 0x40
79#define asyncLSROverrunError 0x20
80#define asyncLSRParityError 0x10
81#define asyncLSRBreakInterrupt 0x08
82#define asyncLSRTxHoldEmpty 0x04
83#define asyncLSRTxShiftEmpty 0x02
84
85/*-----------------------------------------------------------------------------+
86 | Handshake Status Register.
87 +-----------------------------------------------------------------------------*/
88#define asyncHSRport1 0x40000008
89#define asyncHSRport1set 0x4000000c
90#define asyncHSRDsr 0x80
91#define asyncLSRCts 0x40
92
93/*-----------------------------------------------------------------------------+
94 | Control Register.
95 +-----------------------------------------------------------------------------*/
96#define asyncCRport1 0x40000018
97#define asyncCRNormal 0x00
98#define asyncCRLoopback 0x40
99#define asyncCRAutoEcho 0x80
100#define asyncCRDtr 0x20
101#define asyncCRRts 0x10
102#define asyncCRWordLength7 0x00
103#define asyncCRWordLength8 0x08
104#define asyncCRParityDisable 0x00
105#define asyncCRParityEnable 0x04
106#define asyncCREvenParity 0x00
107#define asyncCROddParity 0x02
108#define asyncCRStopBitsOne 0x00
109#define asyncCRStopBitsTwo 0x01
110#define asyncCRDisableDtrRts 0x00
111
112/*-----------------------------------------------------------------------------+
113 | Receiver Command Register.
114 +-----------------------------------------------------------------------------*/
115#define asyncRCRport1 0x4000001c
116#define asyncRCRDisable 0x00
117#define asyncRCREnable 0x80
118#define asyncRCRIntDisable 0x00
119#define asyncRCRIntEnabled 0x20
120#define asyncRCRDMACh2 0x40
121#define asyncRCRDMACh3 0x60
122#define asyncRCRErrorInt 0x10
123#define asyncRCRPauseEnable 0x08
124
125/*-----------------------------------------------------------------------------+
126 | Transmitter Command Register.
127 +-----------------------------------------------------------------------------*/
128#define asyncTCRport1 0x40000020
129#define asyncTCRDisable 0x00
130#define asyncTCREnable 0x80
131#define asyncTCRIntDisable 0x00
132#define asyncTCRIntEnabled 0x20
133#define asyncTCRDMACh2 0x40
134#define asyncTCRDMACh3 0x60
135#define asyncTCRTxEmpty 0x10
136#define asyncTCRErrorInt 0x08
137#define asyncTCRStopPause 0x04
138#define asyncTCRBreakGen 0x02
139
140/*-----------------------------------------------------------------------------+
141 | Miscellanies defines.
142 +-----------------------------------------------------------------------------*/
143#define asyncTxBufferport1 0x40000024
144#define asyncRxBufferport1 0x40000024
145#define asyncDLABLsbport1 0x40000014
146#define asyncDLABMsbport1 0x40000010
147#define asyncXOFFchar 0x13
148#define asyncXONchar 0x11
149
150
151/*
152 * Minimal serial functions needed to use one of the SMC ports
153 * as serial console interface.
154 */
155
156int serial_init (void)
157{
158 DECLARE_GLOBAL_DATA_PTR;
159
160 volatile char val;
161 unsigned short br_reg;
162
163 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
164
165 /*
166 * Init onboard UART
167 */
168 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
169 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
170 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
171 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
172 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
173 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
174 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
175 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
176
177 return (0);
178}
179
180
181void serial_setbrg (void)
182{
183 DECLARE_GLOBAL_DATA_PTR;
184
185 unsigned short br_reg;
186
187 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
188
189 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
190 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
191}
192
193
194void serial_putc (const char c)
195{
196 if (c == '\n')
197 serial_putc ('\r');
198
199 /* load status from handshake register */
200 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
201 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
202
203 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
204
205 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
206 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
207 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
208 }
209}
210
211
212void serial_puts (const char *s)
213{
214 while (*s) {
215 serial_putc (*s++);
216 }
217}
218
219
220int serial_getc ()
221{
222 unsigned char status = 0;
223
224 while (1) {
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
227 break;
228 }
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
238 }
239 }
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
241}
242
243
244int serial_tstc ()
245{
246 unsigned char status;
247
248 status = in8 (asyncLSRport1);
249 if ((status & asyncLSRDataReady) != 0x0) {
250 return (1);
251 }
252 if ((status & ( asyncLSRFramingError |
253 asyncLSROverrunError |
254 asyncLSRParityError |
255 asyncLSRBreakInterrupt )) != 0) {
256 (void) out8 (asyncLSRport1,
257 asyncLSRFramingError |
258 asyncLSROverrunError |
259 asyncLSRParityError |
260 asyncLSRBreakInterrupt);
261 }
262 return 0;
263}
264
265#endif /* CONFIG_IOP480 */
266
267
268/*****************************************************************************/
8749cfb4 269#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
fe8c2806
WD		 270
271#if defined(CONFIG_440)
272#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
273#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
ba56f625
WD		 274#if defined(CONFIG_440_GX)
275#define CR0_MASK 0xdfffffff
276#define CR0_EXTCLK_ENA 0x00800000
277#define CR0_UDIV_POS 0
278#else
fe8c2806
WD		 279#define CR0_MASK 0x3fff0000
280#define CR0_EXTCLK_ENA 0x00600000
281#define CR0_UDIV_POS 16
ba56f625 282#endif /* CONFIG_440_GX */
8749cfb4
SR		 283#elif defined(CONFIG_405EP)
284#define UART0_BASE 0xef600300
285#define UART1_BASE 0xef600400
286#define UCR0_MASK 0x0000007f
287#define UCR1_MASK 0x00007f00
288#define UCR0_UDIV_POS 0
289#define UCR1_UDIV_POS 8
290#define UDIV_MAX 127
291#else /* CONFIG_405GP || CONFIG_405CR */
fe8c2806
WD		 292#define UART0_BASE 0xef600300
293#define UART1_BASE 0xef600400
294#define CR0_MASK 0x00001fff
d7787c6e 295#define CR0_EXTCLK_ENA 0x000000c0
fe8c2806 296#define CR0_UDIV_POS 1
8749cfb4
SR		 297#define UDIV_MAX 32
298#endif
299
300/* using serial port 0 or 1 as U-Boot console ? */
301#if defined(CONFIG_UART1_CONSOLE)
302#define ACTING_UART0_BASE UART1_BASE
303#define ACTING_UART1_BASE UART0_BASE
ba56f625
WD		 304#if defined(CONFIG_440_GX)
305#define UART0_SDR sdr_uart1
306#define UART1_SDR sdr_uart0
307#endif /* CONFIG_440_GX */
8749cfb4
SR		 308#else
309#define ACTING_UART0_BASE UART0_BASE
310#define ACTING_UART1_BASE UART1_BASE
ba56f625
WD		 311#if defined(CONFIG_440_GX)
312#define UART0_SDR sdr_uart0
313#define UART1_SDR sdr_uart1
314#endif /* CONFIG_440_GX */
8749cfb4
SR		 315#endif
316
317#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
318#error "External serial clock not supported on IBM PPC405EP!"
fe8c2806
WD		 319#endif
320
321#define UART_RBR 0x00
322#define UART_THR 0x00
323#define UART_IER 0x01
324#define UART_IIR 0x02
325#define UART_FCR 0x02
326#define UART_LCR 0x03
327#define UART_MCR 0x04
328#define UART_LSR 0x05
329#define UART_MSR 0x06
330#define UART_SCR 0x07
331#define UART_DLL 0x00
332#define UART_DLM 0x01
333
334/*-----------------------------------------------------------------------------+
335 | Line Status Register.
336 +-----------------------------------------------------------------------------*/
8749cfb4 337/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
fe8c2806
WD		 338#define asyncLSRDataReady1 0x01
339#define asyncLSROverrunError1 0x02
340#define asyncLSRParityError1 0x04
341#define asyncLSRFramingError1 0x08
342#define asyncLSRBreakInterrupt1 0x10
343#define asyncLSRTxHoldEmpty1 0x20
344#define asyncLSRTxShiftEmpty1 0x40
345#define asyncLSRRxFifoError1 0x80
346
347/*-----------------------------------------------------------------------------+
348 | Miscellanies defines.
349 +-----------------------------------------------------------------------------*/
8749cfb4
SR		 350/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
351/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
fe8c2806
WD		 352
353
42dfe7a1 354#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 355/*-----------------------------------------------------------------------------+
356 | Fifo
357 +-----------------------------------------------------------------------------*/
358typedef struct {
359 char *rx_buffer;
360 ulong rx_put;
361 ulong rx_get;
362} serial_buffer_t;
363
364volatile static serial_buffer_t buf_info;
365#endif
366
367
368#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
369static void serial_divs (int baudrate, unsigned long *pudiv,
370 unsigned short *pbdiv )
371{
372 sys_info_t sysinfo;
373 unsigned long div; /* total divisor udiv * bdiv */
374 unsigned long umin; /* minimum udiv */
375 unsigned short diff; /* smallest diff */
376 unsigned long udiv; /* best udiv */
377
378 unsigned short idiff; /* current diff */
379 unsigned short ibdiv; /* current bdiv */
380 unsigned long i;
381 unsigned long est; /* current estimate */
382
383 get_sys_info( &sysinfo );
384
385 udiv = 32; /* Assume lowest possible serial clk */
386 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
387 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
388 diff = 32; /* highest possible */
389
390 /* i is the test udiv value -- start with the largest
391 * possible (32) to minimize serial clock and constrain
392 * search to umin.
393 */
394 for( i = 32; i > umin; i-- ){
395 ibdiv = div/i;
396 est = i * ibdiv;
397 idiff = (est > div) ? (est-div) : (div-est);
398 if( idiff == 0 ){
399 udiv = i;
400 break; /* can't do better */
401 }
402 else if( idiff < diff ){
403 udiv = i; /* best so far */
404 diff = idiff; /* update lowest diff*/
405 }
406 }
407
408 *pudiv = udiv;
409 *pbdiv = div/udiv;
410
411}
412#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
413
414
415/*
416 * Minimal serial functions needed to use one of the SMC ports
417 * as serial console interface.
418 */
419
420#if defined(CONFIG_440)
421int serial_init (void)
422{
423 DECLARE_GLOBAL_DATA_PTR;
424
425 unsigned long reg;
426 unsigned long udiv;
427 unsigned short bdiv;
428 volatile char val;
429#ifdef CFG_EXT_SERIAL_CLOCK
430 unsigned long tmp;
431#endif
432
ba56f625
WD		 433#if defined(CONFIG_440_GX)
434 mfsdr(UART0_SDR,reg);
435 reg &= ~CR0_MASK;
436#else
fe8c2806 437 reg = mfdcr(cntrl0) & ~CR0_MASK;
ba56f625 438#endif /* CONFIG_440_GX */
fe8c2806
WD		 439#ifdef CFG_EXT_SERIAL_CLOCK
440 reg |= CR0_EXTCLK_ENA;
441 udiv = 1;
442 tmp = gd->baudrate * 16;
443 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
444#else
445 /* For 440, the cpu clock is on divider chain A, UART on divider
446 * chain B ... so cpu clock is irrelevant. Get the "optimized"
447 * values that are subject to the 1/2 opb clock constraint
448 */
449 serial_divs (gd->baudrate, &udiv, &bdiv);
450#endif
451
ba56f625
WD		 452#if defined(CONFIG_440_GX)
453 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
454 mtsdr (UART0_SDR,reg);
455#else
fe8c2806
WD		 456 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
457 mtdcr (cntrl0, reg);
ba56f625 458#endif
8749cfb4
SR		 459 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
460 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
461 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
462 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
463 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
464 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
465 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
466 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
467 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
468 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 469
470 return (0);
471}
472
473#else /* !defined(CONFIG_440) */
474
475int serial_init (void)
476{
477 DECLARE_GLOBAL_DATA_PTR;
478
479 unsigned long reg;
480 unsigned long tmp;
481 unsigned long clk;
482 unsigned long udiv;
483 unsigned short bdiv;
484 volatile char val;
485
8749cfb4
SR		 486#ifdef CONFIG_405EP
487 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
488 clk = gd->cpu_clk;
489 tmp = CFG_BASE_BAUD * 16;
490 udiv = (clk + tmp / 2) / tmp;
491 if (udiv > UDIV_MAX) /* max. n bits for udiv */
492 udiv = UDIV_MAX;
493 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
494 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
495 mtdcr (cpc0_ucr, reg);
496#else /* CONFIG_405EP */
fe8c2806
WD		 497 reg = mfdcr(cntrl0) & ~CR0_MASK;
498#ifdef CFG_EXT_SERIAL_CLOCK
499 clk = CFG_EXT_SERIAL_CLOCK;
500 udiv = 1;
501 reg |= CR0_EXTCLK_ENA;
502#else
503 clk = gd->cpu_clk;
504#ifdef CFG_405_UART_ERRATA_59
505 udiv = 31; /* Errata 59: stuck at 31 */
506#else
507 tmp = CFG_BASE_BAUD * 16;
508 udiv = (clk + tmp / 2) / tmp;
8749cfb4
SR		 509 if (udiv > UDIV_MAX) /* max. n bits for udiv */
510 udiv = UDIV_MAX;
fe8c2806
WD		 511#endif
512#endif
fe8c2806
WD		 513 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
514 mtdcr (cntrl0, reg);
8749cfb4 515#endif /* CONFIG_405EP */
fe8c2806
WD		 516
517 tmp = gd->baudrate * udiv * 16;
518 bdiv = (clk + tmp / 2) / tmp;
519
8749cfb4
SR		 520 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
521 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
522 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
523 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
524 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
525 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
526 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
527 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
528 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
529 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 530
531 return (0);
532}
533
534#endif /* if defined(CONFIG_440) */
535
536void serial_setbrg (void)
537{
538 DECLARE_GLOBAL_DATA_PTR;
539
540 unsigned long tmp;
541 unsigned long clk;
542 unsigned long udiv;
543 unsigned short bdiv;
544
545#ifdef CFG_EXT_SERIAL_CLOCK
546 clk = CFG_EXT_SERIAL_CLOCK;
547#else
548 clk = gd->cpu_clk;
549#endif
8749cfb4
SR		 550
551#ifdef CONFIG_405EP
552 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
553#else
fe8c2806 554 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
8749cfb4 555#endif /* CONFIG_405EP */
fe8c2806
WD		 556 tmp = gd->baudrate * udiv * 16;
557 bdiv = (clk + tmp / 2) / tmp;
558
8749cfb4
SR		 559 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
560 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
561 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
562 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
fe8c2806
WD		 563}
564
565
566void serial_putc (const char c)
567{
568 int i;
569
570 if (c == '\n')
571 serial_putc ('\r');
572
573 /* check THRE bit, wait for transmiter available */
574 for (i = 1; i < 3500; i++) {
8749cfb4 575 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
fe8c2806
WD		 576 break;
577 udelay (100);
578 }
8749cfb4 579 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 580}
581
582
583void serial_puts (const char *s)
584{
585 while (*s) {
586 serial_putc (*s++);
587 }
588}
589
590
591int serial_getc ()
592{
593 unsigned char status = 0;
594
595 while (1) {
596#if defined(CONFIG_HW_WATCHDOG)
597 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
598#endif /* CONFIG_HW_WATCHDOG */
8749cfb4 599 status = in8 (ACTING_UART0_BASE + UART_LSR);
fe8c2806
WD		 600 if ((status & asyncLSRDataReady1) != 0x0) {
601 break;
602 }
603 if ((status & ( asyncLSRFramingError1 |
604 asyncLSROverrunError1 |
605 asyncLSRParityError1 |
606 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 607 out8 (ACTING_UART0_BASE + UART_LSR,
fe8c2806
WD		 608 asyncLSRFramingError1 |
609 asyncLSROverrunError1 |
610 asyncLSRParityError1 |
611 asyncLSRBreakInterrupt1);
612 }
613 }
8749cfb4 614 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
fe8c2806
WD		 615}
616
617
618int serial_tstc ()
619{
620 unsigned char status;
621
8749cfb4 622 status = in8 (ACTING_UART0_BASE + UART_LSR);
fe8c2806
WD		 623 if ((status & asyncLSRDataReady1) != 0x0) {
624 return (1);
625 }
626 if ((status & ( asyncLSRFramingError1 |
627 asyncLSROverrunError1 |
628 asyncLSRParityError1 |
629 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 630 out8 (ACTING_UART0_BASE + UART_LSR,
fe8c2806
WD		 631 asyncLSRFramingError1 |
632 asyncLSROverrunError1 |
633 asyncLSRParityError1 |
634 asyncLSRBreakInterrupt1);
635 }
636 return 0;
637}
638
639
42dfe7a1 640#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD		 641
642void serial_isr (void *arg)
643{
644 int space;
645 int c;
646 const int rx_get = buf_info.rx_get;
647 int rx_put = buf_info.rx_put;
648
649 if (rx_get <= rx_put) {
650 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
651 } else {
652 space = rx_get - rx_put;
653 }
654 while (serial_tstc ()) {
655 c = serial_getc ();
656 if (space) {
657 buf_info.rx_buffer[rx_put++] = c;
658 space--;
659 }
660 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
661 rx_put = 0;
662 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
663 /* Stop flow by setting RTS inactive */
8749cfb4
SR		 664 out8 (ACTING_UART0_BASE + UART_MCR,
665 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
fe8c2806
WD		 666 }
667 }
668 buf_info.rx_put = rx_put;
669}
670
671void serial_buffered_init (void)
672{
673 serial_puts ("Switching to interrupt driven serial input mode.\n");
674 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
675 buf_info.rx_put = 0;
676 buf_info.rx_get = 0;
677
8749cfb4 678 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
fe8c2806
WD		 679 serial_puts ("Check CTS signal present on serial port: OK.\n");
680 } else {
681 serial_puts ("WARNING: CTS signal not present on serial port.\n");
682 }
683
684 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
685 serial_isr /*interrupt_handler_t *handler */ ,
686 (void *) &buf_info /*void *arg */ );
687
688 /* Enable "RX Data Available" Interrupt on UART */
8749cfb4
SR		 689 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
690 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
fe8c2806 691 /* Set DTR active */
8749cfb4 692 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
fe8c2806 693 /* Start flow by setting RTS active */
8749cfb4 694 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806 695 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
8749cfb4 696 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
fe8c2806
WD		 697}
698
699void serial_buffered_putc (const char c)
700{
701 /* Wait for CTS */
702#if defined(CONFIG_HW_WATCHDOG)
8749cfb4 703 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
fe8c2806
WD		 704 WATCHDOG_RESET ();
705#else
8749cfb4 706 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
fe8c2806
WD		 707#endif
708 serial_putc (c);
709}
710
711void serial_buffered_puts (const char *s)
712{
713 serial_puts (s);
714}
715
716int serial_buffered_getc (void)
717{
718 int space;
719 int c;
720 int rx_get = buf_info.rx_get;
721 int rx_put;
722
723#if defined(CONFIG_HW_WATCHDOG)
724 while (rx_get == buf_info.rx_put)
725 WATCHDOG_RESET ();
726#else
727 while (rx_get == buf_info.rx_put);
728#endif
729 c = buf_info.rx_buffer[rx_get++];
730 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
731 rx_get = 0;
732 buf_info.rx_get = rx_get;
733
734 rx_put = buf_info.rx_put;
735 if (rx_get <= rx_put) {
736 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
737 } else {
738 space = rx_get - rx_put;
739 }
740 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
741 /* Start flow by setting RTS active */
8749cfb4 742 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
fe8c2806
WD		 743 }
744
745 return c;
746}
747
748int serial_buffered_tstc (void)
749{
750 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
751}
752
753#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
754
755
756#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
757/*
758 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
759 number 0 or number 1
760 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
761 configuration has been already done
762 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
763 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
764*/
765#if (CONFIG_KGDB_SER_INDEX & 2)
766void kgdb_serial_init (void)
767{
768 DECLARE_GLOBAL_DATA_PTR;
769
770 volatile char val;
771 unsigned short br_reg;
772
773 get_clocks ();
774 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
775 5) / 10;
776 /*
777 * Init onboard 16550 UART
778 */
8749cfb4
SR		 779 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
780 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
781 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
782 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
783 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
784 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
785 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
786 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
787 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
788 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
fe8c2806
WD		 789}
790
791
792void putDebugChar (const char c)
793{
794 if (c == '\n')
795 serial_putc ('\r');
796
8749cfb4 797 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
fe8c2806
WD		 798
799 /* check THRE bit, wait for transfer done */
8749cfb4 800 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
fe8c2806
WD		 801}
802
803
804void putDebugStr (const char *s)
805{
806 while (*s) {
807 serial_putc (*s++);
808 }
809}
810
811
812int getDebugChar (void)
813{
814 unsigned char status = 0;
815
816 while (1) {
8749cfb4 817 status = in8 (ACTING_UART1_BASE + UART_LSR);
fe8c2806
WD		 818 if ((status & asyncLSRDataReady1) != 0x0) {
819 break;
820 }
821 if ((status & ( asyncLSRFramingError1 |
822 asyncLSROverrunError1 |
823 asyncLSRParityError1 |
824 asyncLSRBreakInterrupt1 )) != 0) {
8749cfb4 825 out8 (ACTING_UART1_BASE + UART_LSR,
fe8c2806
WD		 826 asyncLSRFramingError1 |
827 asyncLSROverrunError1 |
828 asyncLSRParityError1 |
829 asyncLSRBreakInterrupt1);
830 }
831 }
8749cfb4 832 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
fe8c2806
WD		 833}
834
835
836void kgdb_interruptible (int yes)
837{
838 return;
839}
840
841#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
842
843void kgdb_serial_init (void)
844{
845 serial_printf ("[on serial] ");
846}
847
848void putDebugChar (int c)
849{
850 serial_putc (c);
851}
852
853void putDebugStr (const char *str)
854{
855 serial_puts (str);
856}
857
858int getDebugChar (void)
859{
860 return serial_getc ();
861}
862
863void kgdb_interruptible (int yes)
864{
865 return;
866}
867#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
868#endif /* CFG_CMD_KGDB */
869
870#endif /* CONFIG_405GP || CONFIG_405CR */
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