[people/ms/u-boot.git] / cpu / ppc4xx / speed.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <ppc4xx.h>
#include <asm/processor.h>

/* ------------------------------------------------------------------------- */

#define ONE_BILLION        1000000000


#if defined(CONFIG_405GP) || defined(CONFIG_405CR)

void get_sys_info (PPC405_SYS_INFO * sysInfo)
{
	unsigned long pllmr;
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	uint pvr = get_pvr();
	unsigned long psr;
	unsigned long m;

	/*
	 * Read PLL Mode register
	 */
	pllmr = mfdcr (pllmd);

	/*
	 * Read Pin Strapping register
	 */
	psr = mfdcr (strap);

	/*
	 * Determine FWD_DIV.
	 */
	sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
	if (sysInfo->pllFbkDiv == 0) {
		sysInfo->pllFbkDiv = 16;
	}

	/*
	 * Determine PLB_DIV.
	 */
	sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;

	/*
	 * Determine PCI_DIV.
	 */
	sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;

	/*
	 * Determine EXTBUS_DIV.
	 */
	sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;

	/*
	 * Determine OPB_DIV.
	 */
	sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;

	/*
	 * Check if PPC405GPr used (mask minor revision field)
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		/*
		 * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
		 */
		sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);

		/*
		 * Determine factor m depending on PLL feedback clock source
		 */
		if (!(psr & PSR_PCI_ASYNC_EN)) {
			if (psr & PSR_NEW_MODE_EN) {
				/*
				 * sync pci clock used as feedback (new mode)
				 */
				m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
			} else {
				/*
				 * sync pci clock used as feedback (legacy mode)
				 */
				m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
			}
		} else if (psr & PSR_NEW_MODE_EN) {
			if (psr & PSR_PERCLK_SYNC_MODE_EN) {
				/*
				 * PerClk used as feedback (new mode)
				 */
				m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
			} else {
				/*
				 * CPU clock used as feedback (new mode)
				 */
				m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
			}
		} else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
			/*
			 * PerClk used as feedback (legacy mode)
			 */
			m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
		} else {
			/*
			 * PLB clock used as feedback (legacy mode)
			 */
			m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
		}

		sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
		sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv;
		sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) /
			(sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
	} else {
		/*
		 * Check pllFwdDiv to see if running in bypass mode where the CPU speed
		 * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
		 * to make sure it is within the proper range.
		 *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
		 * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
		 */
		if (sysInfo->pllFwdDiv == 1) {
			sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
			sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
		} else {
			sysInfo->freqVCOMhz = ( 1000000 *
						sysInfo->pllFwdDiv *
						sysInfo->pllFbkDiv *
						sysInfo->pllPlbDiv
				) / sysClkPeriodPs;
			if (sysInfo->freqVCOMhz >= VCO_MIN
			    && sysInfo->freqVCOMhz <= VCO_MAX) {
				sysInfo->freqPLB = (ONE_BILLION /
						    ((sysClkPeriodPs * 10) /
						     sysInfo->pllFbkDiv)) * 10000;
				sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
			} else {
				printf ("\nInvalid VCO frequency calculated :  %ld MHz \a\n",
					sysInfo->freqVCOMhz);
				printf ("It must be between %d-%d MHz \a\n",
					VCO_MIN, VCO_MAX);
				printf ("PLL Mode reg           :  %8.8lx\a\n",
					pllmr);
				hang ();
			}
		}
	}
}


/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllOpbDiv;

	return val;
}


/********************************************
 * get_PCI_freq
 * return PCI bus freq in Hz
 *********************************************/
ulong get_PCI_freq (void)
{
	ulong val;
	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllPciDiv;
	return val;
}


#elif defined(CONFIG_440)
#if !defined(CONFIG_440_GX)
void get_sys_info (sys_info_t * sysInfo)
{
	unsigned long strp0;
	unsigned long temp;
	unsigned long m;

	/* Extract configured divisors */
	strp0 = mfdcr( cpc0_strp0 );
	sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
	sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
	sysInfo->pllFbkDiv = temp ? temp : 16;
	sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
	sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);

	/* Calculate 'M' based on feedback source */
	if( strp0 & PLLSYS0_EXTSL_MASK )
		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
	else
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;

	/* Now calculate the individual clocks */
	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
    if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
	sysInfo->freqPLB >>= 1;
	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;

}
#else
void get_sys_info (sys_info_t * sysInfo)
{
	unsigned long strp0;
	unsigned long strp1;
	unsigned long temp;
	unsigned long temp1;
	unsigned long lfdiv;
	unsigned long m;
	unsigned long prbdv0;

	/* Extract configured divisors */
	mfsdr( sdr_sdstp0,strp0 );
	mfsdr( sdr_sdstp1,strp1 );

	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
	sysInfo->pllFwdDivA = temp ? temp : 16 ;
	temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
	sysInfo->pllFwdDivB = temp ? temp: 8 ;
	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
	sysInfo->pllFbkDiv = temp ? temp : 32;
	temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
	sysInfo->pllOpbDiv = temp ? temp : 4;
	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
	sysInfo->pllExtBusDiv = temp ? temp : 4;
	prbdv0 = (strp0 >> 2) & 0x7;

	/* Calculate 'M' based on feedback source */
	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
	temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
	lfdiv = temp1 ? temp1 : 64;
	if (temp == 0) { /* PLL output */
		/* Figure which pll to use */
		temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
		if (!temp)
			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
		else
			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
	}
	else if (temp == 1) /* CPU output */
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
	else /* PerClk */
		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;

	/* Now calculate the individual clocks */
	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;

}
#endif

ulong get_OPB_freq (void)
{

	sys_info_t sys_info;
	get_sys_info (&sys_info);
	return sys_info.freqOPB;
}

#elif defined(CONFIG_XILINX_ML300)
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);

#elif defined(CONFIG_405)

void get_sys_info (sys_info_t * sysInfo) {

	sysInfo->freqVCOMhz=3125000;
	sysInfo->freqProcessor=12*1000*1000;
	sysInfo->freqPLB=50*1000*1000;
	sysInfo->freqPCI=66*1000*1000;

}

#elif defined(CONFIG_405EP)
void get_sys_info (PPC405_SYS_INFO * sysInfo)
{
	unsigned long pllmr0;
	unsigned long pllmr1;
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	unsigned long m;
	unsigned long pllmr0_ccdv;

	/*
	 * Read PLL Mode registers
	 */
	pllmr0 = mfdcr (cpc0_pllmr0);
	pllmr1 = mfdcr (cpc0_pllmr1);

	/*
	 * Determine forward divider A
	 */
	sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);

	/*
	 * Determine forward divider B (should be equal to A)
	 */
	sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
	if (sysInfo->pllFbkDiv == 0) {
		sysInfo->pllFbkDiv = 16;
	}

	/*
	 * Determine PLB_DIV.
	 */
	sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;

	/*
	 * Determine PCI_DIV.
	 */
	sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;

	/*
	 * Determine EXTBUS_DIV.
	 */
	sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;

	/*
	 * Determine OPB_DIV.
	 */
	sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;

	/*
	 * Determine the M factor
	 */
	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;

	/*
	 * Determine VCO clock frequency
	 */
	sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;

	/*
	 * Determine CPU clock frequency
	 */
	pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
	if (pllmr1 & PLLMR1_SSCS_MASK) {
		sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
			/ pllmr0_ccdv;
	} else {
		sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
	}

	/*
	 * Determine PLB clock frequency
	 */
	sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;

	if (!((sysInfo->freqVCOMhz >= VCO_MIN) && (sysInfo->freqVCOMhz <= VCO_MAX))) {
		printf ("\nInvalid VCO frequency calculated :  %ld MHz \a\n",
			sysInfo->freqVCOMhz);
		printf ("It must be between %d-%d MHz \a\n", VCO_MIN, VCO_MAX);
		printf ("PLL Mode reg 0           :  %8.8lx\a\n", pllmr0);
		printf ("PLL Mode reg 1           :  %8.8lx\a\n", pllmr1);
		hang ();
	}
}


/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllOpbDiv;

	return val;
}


/********************************************
 * get_PCI_freq
 * return PCI bus freq in Hz
 *********************************************/
ulong get_PCI_freq (void)
{
	ulong val;
	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllPciDiv;
	return val;
}

#endif

int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
	DECLARE_GLOBAL_DATA_PTR;

	sys_info_t sys_info;

	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor;
	gd->bus_clk = sys_info.freqPLB;

#endif	/* defined(CONFIG_405GP) || defined(CONFIG_405CR) */

#ifdef CONFIG_IOP480
	DECLARE_GLOBAL_DATA_PTR;

	gd->cpu_clk = 66000000;
	gd->bus_clk = 66000000;
#endif
	return (0);
}


/********************************************
 * get_bus_freq
 * return PLB bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	ulong val;

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
	sys_info_t sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB;

#elif defined(CONFIG_IOP480)

	val = 66;

#else
# error get_bus_freq() not implemented
#endif

	return val;
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <ppc_asm.tmpl>
	26	#include <ppc4xx.h>
	27	#include <asm/processor.h>
	28
	29	/* ------------------------------------------------------------------------- */
	30
	31	#define ONE_BILLION 1000000000
	32
	33
	34	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR)
	35
	36	void get_sys_info (PPC405_SYS_INFO * sysInfo)
	37	{
	38	unsigned long pllmr;
	39	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	40	uint pvr = get_pvr();
	41	unsigned long psr;
	42	unsigned long m;
	43
	44	/*
	45	* Read PLL Mode register
	46	*/
	47	pllmr = mfdcr (pllmd);
	48
	49	/*
	50	* Read Pin Strapping register
	51	*/
	52	psr = mfdcr (strap);
	53
	54	/*
	55	* Determine FWD_DIV.
	56	*/
	57	sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
	58
	59	/*
	60	* Determine FBK_DIV.
	61	*/
	62	sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
	63	if (sysInfo->pllFbkDiv == 0) {
	64	sysInfo->pllFbkDiv = 16;
65	}
66
67	/*
68	* Determine PLB_DIV.
69	*/
70	sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
71
72	/*
73	* Determine PCI_DIV.
74	*/
75	sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
76
77	/*
78	* Determine EXTBUS_DIV.
79	*/
80	sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
81
82	/*
83	* Determine OPB_DIV.
84	*/
85	sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
86
87	/*
88	* Check if PPC405GPr used (mask minor revision field)
89	*/
baa3d528	90	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
c609719b WD	91	/*
	92	* Determine FWD_DIV B (only PPC405GPr with new mode strapping).
	93	*/
	94	sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
	95
	96	/*
	97	* Determine factor m depending on PLL feedback clock source
	98	*/
	99	if (!(psr & PSR_PCI_ASYNC_EN)) {
	100	if (psr & PSR_NEW_MODE_EN) {
	101	/*
	102	* sync pci clock used as feedback (new mode)
	103	*/
	104	m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
	105	} else {
	106	/*
	107	* sync pci clock used as feedback (legacy mode)
	108	*/
	109	m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
	110	}
	111	} else if (psr & PSR_NEW_MODE_EN) {
	112	if (psr & PSR_PERCLK_SYNC_MODE_EN) {
	113	/*
	114	* PerClk used as feedback (new mode)
	115	*/
	116	m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
	117	} else {
	118	/*
	119	* CPU clock used as feedback (new mode)
	120	*/
	121	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
	122	}
	123	} else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
	124	/*
	125	* PerClk used as feedback (legacy mode)
	126	*/
	127	m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
	128	} else {
	129	/*
	130	* PLB clock used as feedback (legacy mode)
	131	*/
	132	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
	133	}
	134
	135	sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
	136	sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv;
	137	sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) /
	138	(sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
	139	} else {
	140	/*
	141	* Check pllFwdDiv to see if running in bypass mode where the CPU speed
	142	* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
	143	* to make sure it is within the proper range.
	144	* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
	145	* Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
	146	*/
	147	if (sysInfo->pllFwdDiv == 1) {
	148	sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
	149	sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
	150	} else {
	151	sysInfo->freqVCOMhz = ( 1000000 *
	152	sysInfo->pllFwdDiv *
	153	sysInfo->pllFbkDiv *
	154	sysInfo->pllPlbDiv
155	) / sysClkPeriodPs;
156	if (sysInfo->freqVCOMhz >= VCO_MIN
157	&& sysInfo->freqVCOMhz <= VCO_MAX) {
158	sysInfo->freqPLB = (ONE_BILLION /
159	((sysClkPeriodPs * 10) /
160	sysInfo->pllFbkDiv)) * 10000;
161	sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
162	} else {
163	printf ("\nInvalid VCO frequency calculated : %ld MHz \a\n",
164	sysInfo->freqVCOMhz);
165	printf ("It must be between %d-%d MHz \a\n",
166	VCO_MIN, VCO_MAX);
167	printf ("PLL Mode reg : %8.8lx\a\n",
168	pllmr);
169	hang ();
170	}
171	}
172	}
173	}
174
175
176	/********************************************
177	* get_OPB_freq
178	* return OPB bus freq in Hz
179	*********************************************/
180	ulong get_OPB_freq (void)
181	{
182	ulong val = 0;
183
184	PPC405_SYS_INFO sys_info;
185
186	get_sys_info (&sys_info);
187	val = sys_info.freqPLB / sys_info.pllOpbDiv;
188
189	return val;
190	}
191
192
193	/********************************************
194	* get_PCI_freq
195	* return PCI bus freq in Hz
196	*********************************************/
197	ulong get_PCI_freq (void)
198	{
199	ulong val;
200	PPC405_SYS_INFO sys_info;
201
202	get_sys_info (&sys_info);
203	val = sys_info.freqPLB / sys_info.pllPciDiv;
204	return val;
205	}
206
207
208	#elif defined(CONFIG_440)
ba56f625	209	#if !defined(CONFIG_440_GX)
c609719b WD	210	void get_sys_info (sys_info_t * sysInfo)
	211	{
	212	unsigned long strp0;
	213	unsigned long temp;
	214	unsigned long m;
	215
	216	/* Extract configured divisors */
	217	strp0 = mfdcr( cpc0_strp0 );
	218	sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
	219	sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
	220	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
	221	sysInfo->pllFbkDiv = temp ? temp : 16;
	222	sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
	223	sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
	224
	225	/* Calculate 'M' based on feedback source */
	226	if( strp0 & PLLSYS0_EXTSL_MASK )
	227	m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
	228	else
	229	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
	230
	231	/* Now calculate the individual clocks */
	232	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
	233	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
	234	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
	235	if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
8bde7f77	236	sysInfo->freqPLB >>= 1;
c609719b WD	237	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	238	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
	239
	240	}
ba56f625 WD	241	#else
	242	void get_sys_info (sys_info_t * sysInfo)
	243	{
	244	unsigned long strp0;
	245	unsigned long strp1;
	246	unsigned long temp;
	247	unsigned long temp1;
	248	unsigned long lfdiv;
	249	unsigned long m;
42dfe7a1	250	unsigned long prbdv0;
ba56f625 WD	251
	252	/* Extract configured divisors */
	253	mfsdr( sdr_sdstp0,strp0 );
	254	mfsdr( sdr_sdstp1,strp1 );
	255
	256	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
	257	sysInfo->pllFwdDivA = temp ? temp : 16 ;
	258	temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
	259	sysInfo->pllFwdDivB = temp ? temp: 8 ;
	260	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
	261	sysInfo->pllFbkDiv = temp ? temp : 32;
	262	temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
	263	sysInfo->pllOpbDiv = temp ? temp : 4;
	264	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
	265	sysInfo->pllExtBusDiv = temp ? temp : 4;
0e6d798c	266	prbdv0 = (strp0 >> 2) & 0x7;
ba56f625 WD	267
	268	/* Calculate 'M' based on feedback source */
	269	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
	270	temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
	271	lfdiv = temp1 ? temp1 : 64;
	272	if (temp == 0) { /* PLL output */
	273	/* Figure which pll to use */
	274	temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
	275	if (!temp)
	276	m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
	277	else
	278	m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
	279	}
	280	else if (temp == 1) /* CPU output */
	281	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
	282	else /* PerClk */
	283	m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
	284
	285	/* Now calculate the individual clocks */
	286	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
	287	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
0e6d798c	288	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
ba56f625 WD	289	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	290	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
	291
	292	}
	293	#endif
c609719b WD	294
	295	ulong get_OPB_freq (void)
	296	{
	297
	298	sys_info_t sys_info;
	299	get_sys_info (&sys_info);
	300	return sys_info.freqOPB;
	301	}
	302
028ab6b5 WD	303	#elif defined(CONFIG_XILINX_ML300)
	304	extern void get_sys_info (sys_info_t * sysInfo);
	305	extern ulong get_PCI_freq (void);
	306
c609719b WD	307	#elif defined(CONFIG_405)
	308
	309	void get_sys_info (sys_info_t * sysInfo) {
	310
	311	sysInfo->freqVCOMhz=3125000;
	312	sysInfo->freqProcessor=1210001000;
	313	sysInfo->freqPLB=5010001000;
	314	sysInfo->freqPCI=6610001000;
	315
	316	}
	317
b867d705 SR	318	#elif defined(CONFIG_405EP)
	319	void get_sys_info (PPC405_SYS_INFO * sysInfo)
	320	{
	321	unsigned long pllmr0;
	322	unsigned long pllmr1;
	323	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	324	unsigned long m;
	325	unsigned long pllmr0_ccdv;
	326
	327	/*
	328	* Read PLL Mode registers
	329	*/
	330	pllmr0 = mfdcr (cpc0_pllmr0);
	331	pllmr1 = mfdcr (cpc0_pllmr1);
	332
	333	/*
	334	* Determine forward divider A
	335	*/
	336	sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
	337
	338	/*
	339	* Determine forward divider B (should be equal to A)
	340	*/
	341	sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
	342
	343	/*
	344	* Determine FBK_DIV.
	345	*/
	346	sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
	347	if (sysInfo->pllFbkDiv == 0) {
	348	sysInfo->pllFbkDiv = 16;
	349	}
	350
	351	/*
	352	* Determine PLB_DIV.
	353	*/
	354	sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
	355
	356	/*
	357	* Determine PCI_DIV.
	358	*/
	359	sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
	360
	361	/*
	362	* Determine EXTBUS_DIV.
	363	*/
	364	sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
	365
	366	/*
	367	* Determine OPB_DIV.
	368	*/
	369	sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
	370
	371	/*
	372	* Determine the M factor
	373	*/
	374	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
	375
	376	/*
	377	* Determine VCO clock frequency
	378	*/
	379	sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
	380
	381	/*
382	* Determine CPU clock frequency
383	*/
384	pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
385	if (pllmr1 & PLLMR1_SSCS_MASK) {
386	sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
387	/ pllmr0_ccdv;
388	} else {
389	sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
390	}
391
392	/*
393	* Determine PLB clock frequency
394	*/
395	sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
396
397	if (!((sysInfo->freqVCOMhz >= VCO_MIN) && (sysInfo->freqVCOMhz <= VCO_MAX))) {
398	printf ("\nInvalid VCO frequency calculated : %ld MHz \a\n",
399	sysInfo->freqVCOMhz);
400	printf ("It must be between %d-%d MHz \a\n", VCO_MIN, VCO_MAX);
401	printf ("PLL Mode reg 0 : %8.8lx\a\n", pllmr0);
402	printf ("PLL Mode reg 1 : %8.8lx\a\n", pllmr1);
403	hang ();
404	}
405	}
406
407
408	/********************************************
409	* get_OPB_freq
410	* return OPB bus freq in Hz
411	*********************************************/
412	ulong get_OPB_freq (void)
413	{
414	ulong val = 0;
415
416	PPC405_SYS_INFO sys_info;
417
418	get_sys_info (&sys_info);
419	val = sys_info.freqPLB / sys_info.pllOpbDiv;
420
421	return val;
422	}
423
424
425	/********************************************
426	* get_PCI_freq
427	* return PCI bus freq in Hz
428	*********************************************/
429	ulong get_PCI_freq (void)
430	{
431	ulong val;
432	PPC405_SYS_INFO sys_info;
433
434	get_sys_info (&sys_info);
435	val = sys_info.freqPLB / sys_info.pllPciDiv;
436	return val;
437	}
438
c609719b WD	439	#endif
	440
	441	int get_clocks (void)
	442	{
b867d705	443	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_440) \|\| defined(CONFIG_405) \|\| defined(CONFIG_405EP)
c609719b WD	444	DECLARE_GLOBAL_DATA_PTR;
	445
	446	sys_info_t sys_info;
	447
	448	get_sys_info (&sys_info);
	449	gd->cpu_clk = sys_info.freqProcessor;
	450	gd->bus_clk = sys_info.freqPLB;
	451
	452	#endif /* defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) */
	453
	454	#ifdef CONFIG_IOP480
	455	DECLARE_GLOBAL_DATA_PTR;
	456
	457	gd->cpu_clk = 66000000;
	458	gd->bus_clk = 66000000;
	459	#endif
	460	return (0);
	461	}
	462
	463
	464	/********************************************
	465	* get_bus_freq
	466	* return PLB bus freq in Hz
	467	*********************************************/
	468	ulong get_bus_freq (ulong dummy)
	469	{
	470	ulong val;
	471
b867d705	472	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405) \|\| defined(CONFIG_440) \|\| defined(CONFIG_405EP)
c609719b WD	473	sys_info_t sys_info;
	474
	475	get_sys_info (&sys_info);
	476	val = sys_info.freqPLB;
	477
	478	#elif defined(CONFIG_IOP480)
	479
	480	val = 66;
	481
	482	#else
	483	# error get_bus_freq() not implemented
	484	#endif
	485
	486	return val;
	487	}