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ARM: AT91RM9200 based boards config cleanup
[people/ms/u-boot.git] / cpu / ppc4xx / start.S
CommitLineData
0442ed86
WD		 1/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
3cb86f3e 5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
0442ed86
WD		 6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
83b4cfa3
WD		 25/*------------------------------------------------------------------------------+
26 *
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
33 *
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
37 *
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
41 *
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
45 */
0442ed86 46
0c8721a4 47/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
0442ed86
WD		 48 *
49 *
50 * The processor starts at 0xfffffffc and the code is executed
51 * from flash/rom.
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
58 *
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
61 */
62#include <config.h>
0442ed86
WD		 63#include <ppc4xx.h>
64#include <version.h>
65
66#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
67
68#include <ppc_asm.tmpl>
69#include <ppc_defs.h>
70
71#include <asm/cache.h>
72#include <asm/mmu.h>
73
74#ifndef CONFIG_IDENT_STRING
75#define CONFIG_IDENT_STRING ""
76#endif
77
78#ifdef CFG_INIT_DCACHE_CS
79# if (CFG_INIT_DCACHE_CS == 0)
80# define PBxAP pb0ap
81# define PBxCR pb0cr
82# endif
83# if (CFG_INIT_DCACHE_CS == 1)
84# define PBxAP pb1ap
85# define PBxCR pb1cr
86# endif
87# if (CFG_INIT_DCACHE_CS == 2)
88# define PBxAP pb2ap
89# define PBxCR pb2cr
90# endif
91# if (CFG_INIT_DCACHE_CS == 3)
92# define PBxAP pb3ap
93# define PBxCR pb3cr
94# endif
95# if (CFG_INIT_DCACHE_CS == 4)
96# define PBxAP pb4ap
97# define PBxCR pb4cr
98# endif
99# if (CFG_INIT_DCACHE_CS == 5)
100# define PBxAP pb5ap
101# define PBxCR pb5cr
102# endif
103# if (CFG_INIT_DCACHE_CS == 6)
104# define PBxAP pb6ap
105# define PBxCR pb6cr
106# endif
107# if (CFG_INIT_DCACHE_CS == 7)
108# define PBxAP pb7ap
109# define PBxCR pb7cr
110# endif
111#endif /* CFG_INIT_DCACHE_CS */
112
83b4cfa3 113#define function_prolog(func_name) .text; \
cf959c7d
SR		 114 .align 2; \
115 .globl func_name; \
116 func_name:
83b4cfa3 117#define function_epilog(func_name) .type func_name,@function; \
cf959c7d
SR		 118 .size func_name,.-func_name
119
0442ed86
WD		 120/* We don't want the MMU yet.
121*/
122#undef MSR_KERNEL
123#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
124
125
126 .extern ext_bus_cntlr_init
127 .extern sdram_init
887e2ec9
SR		 128#ifdef CONFIG_NAND_U_BOOT
129 .extern reconfig_tlb0
130#endif
0442ed86
WD		 131
132/*
133 * Set up GOT: Global Offset Table
134 *
135 * Use r14 to access the GOT
136 */
887e2ec9 137#if !defined(CONFIG_NAND_SPL)
0442ed86
WD		 138 START_GOT
139 GOT_ENTRY(_GOT2_TABLE_)
140 GOT_ENTRY(_FIXUP_TABLE_)
141
142 GOT_ENTRY(_start)
143 GOT_ENTRY(_start_of_vectors)
144 GOT_ENTRY(_end_of_vectors)
145 GOT_ENTRY(transfer_to_handler)
146
3b57fe0a 147 GOT_ENTRY(__init_end)
0442ed86 148 GOT_ENTRY(_end)
5d232d0e 149 GOT_ENTRY(__bss_start)
0442ed86 150 END_GOT
887e2ec9
SR		 151#endif /* CONFIG_NAND_SPL */
152
153#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
154 /*
155 * NAND U-Boot image is started from offset 0
156 */
157 .text
c440bfe6 158#if defined(CONFIG_440)
887e2ec9 159 bl reconfig_tlb0
c440bfe6 160#endif
887e2ec9
SR		 161 GET_GOT
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
163 bl board_init_f
164#endif
0442ed86
WD		 165
166/*
167 * 440 Startup -- on reset only the top 4k of the effective
168 * address space is mapped in by an entry in the instruction
169 * and data shadow TLB. The .bootpg section is located in the
170 * top 4k & does only what's necessary to map in the the rest
171 * of the boot rom. Once the boot rom is mapped in we can
172 * proceed with normal startup.
173 *
174 * NOTE: CS0 only covers the top 2MB of the effective address
175 * space after reset.
176 */
177
178#if defined(CONFIG_440)
887e2ec9 179#if !defined(CONFIG_NAND_SPL)
0442ed86 180 .section .bootpg,"ax"
887e2ec9 181#endif
0442ed86
WD		 182 .globl _start_440
183
184/**************************************************************************/
185_start_440:
511d0c72
WD		 186 /*--------------------------------------------------------------------+
187 | 440EPX BUP Change - Hardware team request
188 +--------------------------------------------------------------------*/
887e2ec9
SR		 189#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
190 sync
191 nop
192 nop
193#endif
6c5879f3
MB		 194 /*----------------------------------------------------------------+
195 | Core bug fix. Clear the esr
196 +-----------------------------------------------------------------*/
edd6cf20 197 li r0,0
b87dfd28 198 mtspr esr,r0
0442ed86
WD		 199 /*----------------------------------------------------------------*/
200 /* Clear and set up some registers. */
201 /*----------------------------------------------------------------*/
f901a83b
WD		 202 iccci r0,r0 /* NOTE: operands not used for 440 */
203 dccci r0,r0 /* NOTE: operands not used for 440 */
0442ed86
WD		 204 sync
205 li r0,0
206 mtspr srr0,r0
207 mtspr srr1,r0
208 mtspr csrr0,r0
209 mtspr csrr1,r0
887e2ec9
SR		 210 /* NOTE: 440GX adds machine check status regs */
211#if defined(CONFIG_440) && !defined(CONFIG_440GP)
f901a83b
WD		 212 mtspr mcsrr0,r0
213 mtspr mcsrr1,r0
887e2ec9 214 mfspr r1,mcsr
f901a83b 215 mtspr mcsr,r1
ba56f625 216#endif
20532833
SR		 217
218 /*----------------------------------------------------------------*/
219 /* CCR0 init */
220 /*----------------------------------------------------------------*/
221 /* Disable store gathering & broadcast, guarantee inst/data
222 * cache block touch, force load/store alignment
223 * (see errata 1.12: 440_33)
224 */
225 lis r1,0x0030 /* store gathering & broadcast disable */
226 ori r1,r1,0x6000 /* cache touch */
227 mtspr ccr0,r1
228
0442ed86
WD		 229 /*----------------------------------------------------------------*/
230 /* Initialize debug */
231 /*----------------------------------------------------------------*/
887e2ec9
SR		 232 mfspr r1,dbcr0
233 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
234 bne skip_debug_init /* if set, don't clear debug register */
0442ed86
WD		 235 mtspr dbcr0,r0
236 mtspr dbcr1,r0
237 mtspr dbcr2,r0
238 mtspr iac1,r0
239 mtspr iac2,r0
240 mtspr iac3,r0
241 mtspr dac1,r0
242 mtspr dac2,r0
243 mtspr dvc1,r0
244 mtspr dvc2,r0
245
246 mfspr r1,dbsr
247 mtspr dbsr,r1 /* Clear all valid bits */
887e2ec9 248skip_debug_init:
0442ed86 249
6c5879f3
MB		 250#if defined (CONFIG_440SPE)
251 /*----------------------------------------------------------------+
252 | Initialize Core Configuration Reg1.
253 | a. ICDPEI: Record even parity. Normal operation.
254 | b. ICTPEI: Record even parity. Normal operation.
255 | c. DCTPEI: Record even parity. Normal operation.
256 | d. DCDPEI: Record even parity. Normal operation.
257 | e. DCUPEI: Record even parity. Normal operation.
258 | f. DCMPEI: Record even parity. Normal operation.
259 | g. FCOM: Normal operation
260 | h. MMUPEI: Record even parity. Normal operation.
261 | i. FFF: Flush only as much data as necessary.
edd6cf20 262 | j. TCS: Timebase increments from CPU clock.
6c5879f3 263 +-----------------------------------------------------------------*/
edd6cf20 264 li r0,0
6c5879f3
MB		 265 mtspr ccr1, r0
266
267 /*----------------------------------------------------------------+
268 | Reset the timebase.
269 | The previous write to CCR1 sets the timebase source.
270 +-----------------------------------------------------------------*/
6c5879f3
MB		 271 mtspr tbl, r0
272 mtspr tbu, r0
273#endif
274
0442ed86
WD		 275 /*----------------------------------------------------------------*/
276 /* Setup interrupt vectors */
277 /*----------------------------------------------------------------*/
278 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
f901a83b 279 li r1,0x0100
0442ed86 280 mtspr ivor0,r1 /* Critical input */
f901a83b 281 li r1,0x0200
0442ed86 282 mtspr ivor1,r1 /* Machine check */
f901a83b 283 li r1,0x0300
0442ed86 284 mtspr ivor2,r1 /* Data storage */
f901a83b 285 li r1,0x0400
0442ed86
WD		 286 mtspr ivor3,r1 /* Instruction storage */
287 li r1,0x0500
288 mtspr ivor4,r1 /* External interrupt */
289 li r1,0x0600
290 mtspr ivor5,r1 /* Alignment */
291 li r1,0x0700
292 mtspr ivor6,r1 /* Program check */
293 li r1,0x0800
294 mtspr ivor7,r1 /* Floating point unavailable */
295 li r1,0x0c00
296 mtspr ivor8,r1 /* System call */
efa35cf1 297 li r1,0x0a00
83b4cfa3 298 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
efa35cf1
GB		 299 li r1,0x0900
300 mtspr ivor10,r1 /* Decrementer */
0442ed86 301 li r1,0x1300
efa35cf1
GB		 302 mtspr ivor13,r1 /* Data TLB error */
303 li r1,0x1400
0442ed86
WD		 304 mtspr ivor14,r1 /* Instr TLB error */
305 li r1,0x2000
306 mtspr ivor15,r1 /* Debug */
307
308 /*----------------------------------------------------------------*/
309 /* Configure cache regions */
310 /*----------------------------------------------------------------*/
311 mtspr inv0,r0
312 mtspr inv1,r0
313 mtspr inv2,r0
314 mtspr inv3,r0
315 mtspr dnv0,r0
316 mtspr dnv1,r0
317 mtspr dnv2,r0
318 mtspr dnv3,r0
319 mtspr itv0,r0
320 mtspr itv1,r0
321 mtspr itv2,r0
322 mtspr itv3,r0
323 mtspr dtv0,r0
324 mtspr dtv1,r0
325 mtspr dtv2,r0
326 mtspr dtv3,r0
327
328 /*----------------------------------------------------------------*/
329 /* Cache victim limits */
330 /*----------------------------------------------------------------*/
331 /* floors 0, ceiling max to use the entire cache -- nothing locked
332 */
333 lis r1,0x0001
334 ori r1,r1,0xf800
335 mtspr ivlim,r1
336 mtspr dvlim,r1
337
6c5879f3
MB		 338 /*----------------------------------------------------------------+
339 |Initialize MMUCR[STID] = 0.
340 +-----------------------------------------------------------------*/
341 mfspr r0,mmucr
342 addis r1,0,0xFFFF
343 ori r1,r1,0xFF00
344 and r0,r0,r1
345 mtspr mmucr,r0
346
0442ed86
WD		 347 /*----------------------------------------------------------------*/
348 /* Clear all TLB entries -- TID = 0, TS = 0 */
349 /*----------------------------------------------------------------*/
6c5879f3 350 addis r0,0,0x0000
0442ed86
WD		 351 li r1,0x003f /* 64 TLB entries */
352 mtctr r1
6c5879f3
MB		 353rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
354 tlbwe r0,r1,0x0001
355 tlbwe r0,r1,0x0002
0442ed86 356 subi r1,r1,0x0001
6c5879f3 357 bdnz rsttlb
0442ed86
WD		 358
359 /*----------------------------------------------------------------*/
360 /* TLB entry setup -- step thru tlbtab */
361 /*----------------------------------------------------------------*/
692519b1
RJ		 362#if defined(CONFIG_440SPE)
363 /*----------------------------------------------------------------*/
364 /* We have different TLB tables for revA and rev B of 440SPe */
365 /*----------------------------------------------------------------*/
366 mfspr r1, PVR
367 lis r0,0x5342
368 ori r0,r0,0x1891
369 cmpw r7,r1,r0
370 bne r7,..revA
371 bl tlbtabB
372 b ..goon
373..revA:
374 bl tlbtabA
375..goon:
376#else
0442ed86 377 bl tlbtab /* Get tlbtab pointer */
692519b1 378#endif
0442ed86
WD		 379 mr r5,r0
380 li r1,0x003f /* 64 TLB entries max */
381 mtctr r1
382 li r4,0 /* TLB # */
383
384 addi r5,r5,-4
3851: lwzu r0,4(r5)
386 cmpwi r0,0
387 beq 2f /* 0 marks end */
388 lwzu r1,4(r5)
389 lwzu r2,4(r5)
390 tlbwe r0,r4,0 /* TLB Word 0 */
391 tlbwe r1,r4,1 /* TLB Word 1 */
392 tlbwe r2,r4,2 /* TLB Word 2 */
393 addi r4,r4,1 /* Next TLB */
394 bdnz 1b
395
396 /*----------------------------------------------------------------*/
397 /* Continue from 'normal' start */
398 /*----------------------------------------------------------------*/
887e2ec9
SR		 3992:
400
401#if defined(CONFIG_NAND_SPL)
cf959c7d 402#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
887e2ec9 403 /*
cf959c7d 404 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
887e2ec9
SR		 405 */
406 lis r2,0x7fff
407 ori r2,r2,0xffff
408 mfdcr r1,isram0_dpc
409 and r1,r1,r2 /* Disable parity check */
410 mtdcr isram0_dpc,r1
411 mfdcr r1,isram0_pmeg
412 and r1,r1,r2 /* Disable pwr mgmt */
413 mtdcr isram0_pmeg,r1
cf959c7d
SR		 414#endif
415#if defined(CONFIG_440EP)
416 /*
417 * On 440EP with no internal SRAM, we setup SDRAM very early
418 * and copy the NAND_SPL to SDRAM and jump to it
419 */
420 /* Clear Dcache to use as RAM */
421 addis r3,r0,CFG_INIT_RAM_ADDR@h
422 ori r3,r3,CFG_INIT_RAM_ADDR@l
423 addis r4,r0,CFG_INIT_RAM_END@h
424 ori r4,r4,CFG_INIT_RAM_END@l
425 rlwinm. r5,r4,0,27,31
426 rlwinm r5,r4,27,5,31
427 beq ..d_ran3
428 addi r5,r5,0x0001
429..d_ran3:
430 mtctr r5
431..d_ag3:
432 dcbz r0,r3
433 addi r3,r3,32
434 bdnz ..d_ag3
435 /*----------------------------------------------------------------*/
436 /* Setup the stack in internal SRAM */
437 /*----------------------------------------------------------------*/
438 lis r1,CFG_INIT_RAM_ADDR@h
439 ori r1,r1,CFG_INIT_SP_OFFSET@l
440 li r0,0
441 stwu r0,-4(r1)
442 stwu r0,-4(r1) /* Terminate call chain */
443
444 stwu r1,-8(r1) /* Save back chain and move SP */
445 lis r0,RESET_VECTOR@h /* Address of reset vector */
446 ori r0,r0, RESET_VECTOR@l
447 stwu r1,-8(r1) /* Save back chain and move SP */
448 stw r0,+12(r1) /* Save return addr (underflow vect) */
449 sync
450 bl early_sdram_init
451 sync
452#endif /* CONFIG_440EP */
887e2ec9
SR		 453
454 /*
455 * Copy SPL from cache into internal SRAM
456 */
457 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
458 mtctr r4
459 lis r2,CFG_NAND_BOOT_SPL_SRC@h
460 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
461 lis r3,CFG_NAND_BOOT_SPL_DST@h
462 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
463spl_loop:
464 lwzu r4,4(r2)
465 stwu r4,4(r3)
466 bdnz spl_loop
467
468 /*
469 * Jump to code in RAM
470 */
471 bl 00f
47200: mflr r10
473 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
474 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
475 sub r10,r10,r3
476 addi r10,r10,28
477 mtlr r10
478 blr
479
480start_ram:
481 sync
482 isync
cf959c7d 483#endif /* CONFIG_NAND_SPL */
887e2ec9
SR		 484
485 bl 3f
0442ed86
WD		 486 b _start
487
4883: li r0,0
489 mtspr srr1,r0 /* Keep things disabled for now */
490 mflr r1
491 mtspr srr0,r1
492 rfi
b867d705 493#endif /* CONFIG_440 */
0442ed86
WD		 494
495/*
496 * r3 - 1st arg to board_init(): IMMP pointer
497 * r4 - 2nd arg to board_init(): boot flag
498 */
887e2ec9 499#ifndef CONFIG_NAND_SPL
0442ed86
WD		 500 .text
501 .long 0x27051956 /* U-Boot Magic Number */
502 .globl version_string
503version_string:
504 .ascii U_BOOT_VERSION
505 .ascii " (", __DATE__, " - ", __TIME__, ")"
506 .ascii CONFIG_IDENT_STRING, "\0"
507
0442ed86 508 . = EXC_OFF_SYS_RESET
efa35cf1
GB		 509 .globl _start_of_vectors
510_start_of_vectors:
511
512/* Critical input. */
513 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
514
515#ifdef CONFIG_440
516/* Machine check */
83b4cfa3 517 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
efa35cf1 518#else
83b4cfa3 519 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
efa35cf1
GB		 520#endif /* CONFIG_440 */
521
522/* Data Storage exception. */
523 STD_EXCEPTION(0x300, DataStorage, UnknownException)
524
525/* Instruction Storage exception. */
526 STD_EXCEPTION(0x400, InstStorage, UnknownException)
527
528/* External Interrupt exception. */
529 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
530
531/* Alignment exception. */
532 . = 0x600
533Alignment:
534 EXCEPTION_PROLOG(SRR0, SRR1)
535 mfspr r4,DAR
536 stw r4,_DAR(r21)
537 mfspr r5,DSISR
538 stw r5,_DSISR(r21)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 li r20,MSR_KERNEL
541 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
542 lwz r6,GOT(transfer_to_handler)
543 mtlr r6
544 blrl
545.L_Alignment:
546 .long AlignmentException - _start + _START_OFFSET
547 .long int_return - _start + _START_OFFSET
548
549/* Program check exception */
550 . = 0x700
551ProgramCheck:
552 EXCEPTION_PROLOG(SRR0, SRR1)
553 addi r3,r1,STACK_FRAME_OVERHEAD
554 li r20,MSR_KERNEL
555 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
556 lwz r6,GOT(transfer_to_handler)
557 mtlr r6
558 blrl
559.L_ProgramCheck:
560 .long ProgramCheckException - _start + _START_OFFSET
561 .long int_return - _start + _START_OFFSET
562
563#ifdef CONFIG_440
564 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
565 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
566 STD_EXCEPTION(0xa00, APU, UnknownException)
df8a24cd 567#endif
efa35cf1
GB		 568 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
569
570#ifdef CONFIG_440
571 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
572 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
573#else
574 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
575 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
576 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
577#endif
578 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
579
580 .globl _end_of_vectors
581_end_of_vectors:
582 . = _START_OFFSET
887e2ec9 583#endif
0442ed86
WD		 584 .globl _start
585_start:
586
587/*****************************************************************************/
588#if defined(CONFIG_440)
589
590 /*----------------------------------------------------------------*/
591 /* Clear and set up some registers. */
592 /*----------------------------------------------------------------*/
593 li r0,0x0000
594 lis r1,0xffff
595 mtspr dec,r0 /* prevent dec exceptions */
596 mtspr tbl,r0 /* prevent fit & wdt exceptions */
597 mtspr tbu,r0
598 mtspr tsr,r1 /* clear all timer exception status */
599 mtspr tcr,r0 /* disable all */
600 mtspr esr,r0 /* clear exception syndrome register */
601 mtxer r0 /* clear integer exception register */
0442ed86
WD		 602
603 /*----------------------------------------------------------------*/
604 /* Debug setup -- some (not very good) ice's need an event*/
605 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
606 /* value you need in this case 0x8cff 0000 should do the trick */
607 /*----------------------------------------------------------------*/
608#if defined(CFG_INIT_DBCR)
609 lis r1,0xffff
610 ori r1,r1,0xffff
611 mtspr dbsr,r1 /* Clear all status bits */
612 lis r0,CFG_INIT_DBCR@h
613 ori r0,r0,CFG_INIT_DBCR@l
614 mtspr dbcr0,r0
615 isync
616#endif
617
618 /*----------------------------------------------------------------*/
619 /* Setup the internal SRAM */
620 /*----------------------------------------------------------------*/
621 li r0,0
887e2ec9
SR		 622
623#ifdef CFG_INIT_RAM_DCACHE
c157d8e2 624 /* Clear Dcache to use as RAM */
f901a83b
WD		 625 addis r3,r0,CFG_INIT_RAM_ADDR@h
626 ori r3,r3,CFG_INIT_RAM_ADDR@l
627 addis r4,r0,CFG_INIT_RAM_END@h
628 ori r4,r4,CFG_INIT_RAM_END@l
c157d8e2 629 rlwinm. r5,r4,0,27,31
f901a83b
WD		 630 rlwinm r5,r4,27,5,31
631 beq ..d_ran
632 addi r5,r5,0x0001
c157d8e2 633..d_ran:
f901a83b 634 mtctr r5
c157d8e2 635..d_ag:
f901a83b
WD		 636 dcbz r0,r3
637 addi r3,r3,32
638 bdnz ..d_ag
e02c521d
SR		 639
640 /*
641 * Lock the init-ram/stack in d-cache, so that other regions
642 * may use d-cache as well
643 * Note, that this current implementation locks exactly 4k
644 * of d-cache, so please make sure that you don't define a
645 * bigger init-ram area. Take a look at the lwmon5 440EPx
646 * implementation as a reference.
647 */
648 msync
649 isync
650 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
651 lis r1,0x0201
652 ori r1,r1,0xf808
653 mtspr dvlim,r1
654 lis r1,0x0808
655 ori r1,r1,0x0808
656 mtspr dnv0,r1
657 mtspr dnv1,r1
658 mtspr dnv2,r1
659 mtspr dnv3,r1
660 mtspr dtv0,r1
661 mtspr dtv1,r1
662 mtspr dtv2,r1
663 mtspr dtv3,r1
664 msync
665 isync
887e2ec9
SR		 666#endif /* CFG_INIT_RAM_DCACHE */
667
668 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
669#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
670 /* not all PPC's have internal SRAM usable as L2-cache */
671#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
f901a83b 672 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
ba56f625 673#endif
0442ed86 674
887e2ec9 675 lis r2,0x7fff
0442ed86
WD		 676 ori r2,r2,0xffff
677 mfdcr r1,isram0_dpc
678 and r1,r1,r2 /* Disable parity check */
679 mtdcr isram0_dpc,r1
680 mfdcr r1,isram0_pmeg
887e2ec9 681 and r1,r1,r2 /* Disable pwr mgmt */
0442ed86
WD		 682 mtdcr isram0_pmeg,r1
683
684 lis r1,0x8000 /* BAS = 8000_0000 */
6e7fb6ea 685#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ba56f625 686 ori r1,r1,0x0980 /* first 64k */
f901a83b 687 mtdcr isram0_sb0cr,r1
ba56f625
WD		 688 lis r1,0x8001
689 ori r1,r1,0x0980 /* second 64k */
f901a83b 690 mtdcr isram0_sb1cr,r1
ba56f625
WD		 691 lis r1, 0x8002
692 ori r1,r1, 0x0980 /* third 64k */
f901a83b 693 mtdcr isram0_sb2cr,r1
ba56f625
WD		 694 lis r1, 0x8003
695 ori r1,r1, 0x0980 /* fourth 64k */
f901a83b 696 mtdcr isram0_sb3cr,r1
6c5879f3
MB		 697#elif defined(CONFIG_440SPE)
698 lis r1,0x0000 /* BAS = 0000_0000 */
699 ori r1,r1,0x0984 /* first 64k */
700 mtdcr isram0_sb0cr,r1
701 lis r1,0x0001
702 ori r1,r1,0x0984 /* second 64k */
703 mtdcr isram0_sb1cr,r1
704 lis r1, 0x0002
705 ori r1,r1, 0x0984 /* third 64k */
706 mtdcr isram0_sb2cr,r1
707 lis r1, 0x0003
708 ori r1,r1, 0x0984 /* fourth 64k */
709 mtdcr isram0_sb3cr,r1
887e2ec9 710#elif defined(CONFIG_440GP)
0442ed86
WD		 711 ori r1,r1,0x0380 /* 8k rw */
712 mtdcr isram0_sb0cr,r1
887e2ec9 713 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
c157d8e2 714#endif
887e2ec9 715#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
0442ed86
WD		 716
717 /*----------------------------------------------------------------*/
718 /* Setup the stack in internal SRAM */
719 /*----------------------------------------------------------------*/
720 lis r1,CFG_INIT_RAM_ADDR@h
721 ori r1,r1,CFG_INIT_SP_OFFSET@l
0442ed86
WD		 722 li r0,0
723 stwu r0,-4(r1)
724 stwu r0,-4(r1) /* Terminate call chain */
725
726 stwu r1,-8(r1) /* Save back chain and move SP */
727 lis r0,RESET_VECTOR@h /* Address of reset vector */
728 ori r0,r0, RESET_VECTOR@l
729 stwu r1,-8(r1) /* Save back chain and move SP */
730 stw r0,+12(r1) /* Save return addr (underflow vect) */
731
887e2ec9
SR		 732#ifdef CONFIG_NAND_SPL
733 bl nand_boot /* will not return */
734#else
0442ed86 735 GET_GOT
5568e613
SR		 736
737 bl cpu_init_f /* run low-level CPU init code (from Flash) */
0442ed86 738 bl board_init_f
887e2ec9 739#endif
0442ed86
WD		 740
741#endif /* CONFIG_440 */
742
743/*****************************************************************************/
744#ifdef CONFIG_IOP480
745 /*----------------------------------------------------------------------- */
746 /* Set up some machine state registers. */
747 /*----------------------------------------------------------------------- */
748 addi r0,r0,0x0000 /* initialize r0 to zero */
749 mtspr esr,r0 /* clear Exception Syndrome Reg */
750 mttcr r0 /* timer control register */
751 mtexier r0 /* disable all interrupts */
0442ed86
WD		 752 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
753 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
754 mtdbsr r4 /* clear/reset the dbsr */
755 mtexisr r4 /* clear all pending interrupts */
756 addis r4,r0,0x8000
757 mtexier r4 /* enable critical exceptions */
758 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
759 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
760 mtiocr r4 /* since bit not used) & DRC to latch */
761 /* data bus on rising edge of CAS */
762 /*----------------------------------------------------------------------- */
763 /* Clear XER. */
764 /*----------------------------------------------------------------------- */
765 mtxer r0
766 /*----------------------------------------------------------------------- */
767 /* Invalidate i-cache and d-cache TAG arrays. */
768 /*----------------------------------------------------------------------- */
769 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
770 addi r4,0,1024 /* 1/4 of I-cache */
771..cloop:
772 iccci 0,r3
773 iccci r4,r3
774 dccci 0,r3
775 addic. r3,r3,-16 /* move back one cache line */
776 bne ..cloop /* loop back to do rest until r3 = 0 */
777
778 /* */
779 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
780 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
781 /* */
782
783 /* first copy IOP480 register base address into r3 */
784 addis r3,0,0x5000 /* IOP480 register base address hi */
785/* ori r3,r3,0x0000 / IOP480 register base address lo */
786
787#ifdef CONFIG_ADCIOP
788 /* use r4 as the working variable */
789 /* turn on CS3 (LOCCTL.7) */
790 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
791 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
792 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
793#endif
794
795#ifdef CONFIG_DASA_SIM
796 /* use r4 as the working variable */
797 /* turn on MA17 (LOCCTL.7) */
798 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
799 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
800 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
801#endif
802
803 /* turn on MA16..13 (LCS0BRD.12 = 0) */
804 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
805 andi. r4,r4,0xefff /* make bit 12 = 0 */
806 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
807
808 /* make sure above stores all comlete before going on */
809 sync
810
811 /* last thing, set local init status done bit (DEVINIT.31) */
812 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
813 oris r4,r4,0x8000 /* make bit 31 = 1 */
814 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
815
816 /* clear all pending interrupts and disable all interrupts */
817 li r4,-1 /* set p1 to 0xffffffff */
818 stw r4,0x1b0(r3) /* clear all pending interrupts */
819 stw r4,0x1b8(r3) /* clear all pending interrupts */
820 li r4,0 /* set r4 to 0 */
821 stw r4,0x1b4(r3) /* disable all interrupts */
822 stw r4,0x1bc(r3) /* disable all interrupts */
823
824 /* make sure above stores all comlete before going on */
825 sync
826
827 /*----------------------------------------------------------------------- */
828 /* Enable two 128MB cachable regions. */
829 /*----------------------------------------------------------------------- */
dbbd1257 830 addis r1,r0,0xc000
0442ed86
WD		 831 addi r1,r1,0x0001
832 mticcr r1 /* instruction cache */
833
834 addis r1,r0,0x0000
835 addi r1,r1,0x0000
836 mtdccr r1 /* data cache */
837
838 addis r1,r0,CFG_INIT_RAM_ADDR@h
839 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
840 li r0, 0 /* Make room for stack frame header and */
841 stwu r0, -4(r1) /* clear final stack frame so that */
842 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
843
844 GET_GOT /* initialize GOT access */
845
846 bl board_init_f /* run first part of init code (from Flash) */
847
848#endif /* CONFIG_IOP480 */
849
850/*****************************************************************************/
e01bd218
SR		 851#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
852 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
dbbd1257 853 defined(CONFIG_405EX) || defined(CONFIG_405)
0442ed86
WD		 854 /*----------------------------------------------------------------------- */
855 /* Clear and set up some registers. */
856 /*----------------------------------------------------------------------- */
857 addi r4,r0,0x0000
dbbd1257 858#if !defined(CONFIG_405EX)
0442ed86 859 mtspr sgr,r4
dbbd1257
SR		 860#else
861 /*
862 * On 405EX, completely clearing the SGR leads to PPC hangup
863 * upon PCIe configuration access. The PCIe memory regions
864 * need to be guarded!
865 */
866 lis r3,0x0000
867 ori r3,r3,0x7FFC
868 mtspr sgr,r3
869#endif
0442ed86
WD		 870 mtspr dcwr,r4
871 mtesr r4 /* clear Exception Syndrome Reg */
872 mttcr r4 /* clear Timer Control Reg */
873 mtxer r4 /* clear Fixed-Point Exception Reg */
874 mtevpr r4 /* clear Exception Vector Prefix Reg */
0442ed86
WD		 875 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
876 /* dbsr is cleared by setting bits to 1) */
877 mtdbsr r4 /* clear/reset the dbsr */
878
879 /*----------------------------------------------------------------------- */
880 /* Invalidate I and D caches. Enable I cache for defined memory regions */
881 /* to speed things up. Leave the D cache disabled for now. It will be */
882 /* enabled/left disabled later based on user selected menu options. */
883 /* Be aware that the I cache may be disabled later based on the menu */
884 /* options as well. See miscLib/main.c. */
885 /*----------------------------------------------------------------------- */
886 bl invalidate_icache
887 bl invalidate_dcache
888
889 /*----------------------------------------------------------------------- */
890 /* Enable two 128MB cachable regions. */
891 /*----------------------------------------------------------------------- */
dbbd1257 892 lis r4,0xc000
e01bd218 893 ori r4,r4,0x0001
0442ed86
WD		 894 mticcr r4 /* instruction cache */
895 isync
896
e01bd218
SR		 897 lis r4,0x0000
898 ori r4,r4,0x0000
0442ed86
WD		 899 mtdccr r4 /* data cache */
900
dbbd1257 901#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
0442ed86
WD		 902 /*----------------------------------------------------------------------- */
903 /* Tune the speed and size for flash CS0 */
904 /*----------------------------------------------------------------------- */
905 bl ext_bus_cntlr_init
906#endif
dbbd1257
SR		 907#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
908 /*
909 * Boards like the Kilauea (405EX) don't have OCM and can't use
910 * DCache for init-ram. So setup stack here directly after the
911 * SDRAM is initialized.
912 */
913 lis r1, CFG_INIT_RAM_ADDR@h
914 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
915
916 li r0, 0 /* Make room for stack frame header and */
917 stwu r0, -4(r1) /* clear final stack frame so that */
918 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
919 /*
920 * Set up a dummy frame to store reset vector as return address.
921 * this causes stack underflow to reset board.
922 */
923 stwu r1, -8(r1) /* Save back chain and move SP */
924 lis r0, RESET_VECTOR@h /* Address of reset vector */
925 ori r0, r0, RESET_VECTOR@l
926 stwu r1, -8(r1) /* Save back chain and move SP */
927 stw r0, +12(r1) /* Save return addr (underflow vect) */
928#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
0442ed86 929
b867d705
SR		 930#if defined(CONFIG_405EP)
931 /*----------------------------------------------------------------------- */
932 /* DMA Status, clear to come up clean */
933 /*----------------------------------------------------------------------- */
f901a83b
WD		 934 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
935 ori r3,r3, 0xFFFF
936 mtdcr dmasr, r3
b867d705 937
f901a83b 938 bl ppc405ep_init /* do ppc405ep specific init */
b867d705
SR		 939#endif /* CONFIG_405EP */
940
0442ed86 941#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
e01bd218
SR		 942#if defined(CONFIG_405EZ)
943 /********************************************************************
944 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
945 *******************************************************************/
946 /*
947 * We can map the OCM on the PLB3, so map it at
948 * CFG_OCM_DATA_ADDR + 0x8000
949 */
950 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
951 ori r3,r3,CFG_OCM_DATA_ADDR@l
df8a24cd 952 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
e01bd218
SR		 953 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
954 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
955 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
956 isync
957
83b4cfa3 958 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
e01bd218 959 ori r3,r3,CFG_OCM_DATA_ADDR@l
83b4cfa3
WD		 960 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
961 mtdcr ocmdscr1, r3 /* Set Data Side */
962 mtdcr ocmiscr1, r3 /* Set Instruction Side */
e01bd218 963 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
83b4cfa3
WD		 964 mtdcr ocmdscr2, r3 /* Set Data Side */
965 mtdcr ocmiscr2, r3 /* Set Instruction Side */
966 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
d7568947 967 mtdcr ocmdsisdpc,r3
e01bd218
SR		 968
969 isync
3cb86f3e 970#else /* CONFIG_405EZ */
0442ed86
WD		 971 /********************************************************************
972 * Setup OCM - On Chip Memory
973 *******************************************************************/
974 /* Setup OCM */
8bde7f77
WD		 975 lis r0, 0x7FFF
976 ori r0, r0, 0xFFFF
f901a83b 977 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
3cb86f3e
SR		 978 mfdcr r4, ocmdscntl /* get data-side IRAM config */
979 and r3, r3, r0 /* disable data-side IRAM */
980 and r4, r4, r0 /* disable data-side IRAM */
981 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
982 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
8bde7f77 983 isync
0442ed86 984
83b4cfa3 985 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
3cb86f3e 986 ori r3,r3,CFG_OCM_DATA_ADDR@l
0442ed86
WD		 987 mtdcr ocmdsarc, r3
988 addis r4, 0, 0xC000 /* OCM data area enabled */
989 mtdcr ocmdscntl, r4
8bde7f77 990 isync
e01bd218 991#endif /* CONFIG_405EZ */
0442ed86
WD		 992#endif
993
c440bfe6
SR		 994#ifdef CONFIG_NAND_SPL
995 /*
996 * Copy SPL from cache into internal SRAM
997 */
998 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
999 mtctr r4
1000 lis r2,CFG_NAND_BOOT_SPL_SRC@h
1001 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
1002 lis r3,CFG_NAND_BOOT_SPL_DST@h
1003 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
1004spl_loop:
1005 lwzu r4,4(r2)
1006 stwu r4,4(r3)
1007 bdnz spl_loop
1008
1009 /*
1010 * Jump to code in RAM
1011 */
1012 bl 00f
101300: mflr r10
1014 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
1015 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
1016 sub r10,r10,r3
1017 addi r10,r10,28
1018 mtlr r10
1019 blr
1020
1021start_ram:
1022 sync
1023 isync
1024#endif /* CONFIG_NAND_SPL */
1025
0442ed86
WD		 1026 /*----------------------------------------------------------------------- */
1027 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1028 /*----------------------------------------------------------------------- */
1029#ifdef CFG_INIT_DCACHE_CS
1030 /*----------------------------------------------------------------------- */
1031 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
1032 /* used as temporary stack pointer for stage0 */
1033 /*----------------------------------------------------------------------- */
1034 li r4,PBxAP
1035 mtdcr ebccfga,r4
1036 lis r4,0x0380
1037 ori r4,r4,0x0480
1038 mtdcr ebccfgd,r4
1039
1040 addi r4,0,PBxCR
1041 mtdcr ebccfga,r4
1042 lis r4,0x400D
1043 ori r4,r4,0xa000
1044 mtdcr ebccfgd,r4
1045
dbbd1257 1046 /* turn on data cache for this region */
0442ed86
WD		 1047 lis r4,0x0080
1048 mtdccr r4
1049
1050 /* set stack pointer and clear stack to known value */
1051
1052 lis r1,CFG_INIT_RAM_ADDR@h
f901a83b 1053 ori r1,r1,CFG_INIT_SP_OFFSET@l
0442ed86
WD		 1054
1055 li r4,2048 /* we store 2048 words to stack */
1056 mtctr r4
1057
1058 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
f901a83b 1059 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
0442ed86
WD		 1060
1061 lis r4,0xdead /* we store 0xdeaddead in the stack */
1062 ori r4,r4,0xdead
1063
1064..stackloop:
1065 stwu r4,-4(r2)
1066 bdnz ..stackloop
1067
1068 li r0, 0 /* Make room for stack frame header and */
1069 stwu r0, -4(r1) /* clear final stack frame so that */
1070 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1071 /*
1072 * Set up a dummy frame to store reset vector as return address.
1073 * this causes stack underflow to reset board.
1074 */
1075 stwu r1, -8(r1) /* Save back chain and move SP */
1076 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1077 ori r0, r0, RESET_VECTOR@l
1078 stwu r1, -8(r1) /* Save back chain and move SP */
1079 stw r0, +12(r1) /* Save return addr (underflow vect) */
1080
1081#elif defined(CFG_TEMP_STACK_OCM) && \
1082 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1083 /*
1084 * Stack in OCM.
1085 */
1086
1087 /* Set up Stack at top of OCM */
1088 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1089 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1090
1091 /* Set up a zeroized stack frame so that backtrace works right */
1092 li r0, 0
1093 stwu r0, -4(r1)
1094 stwu r0, -4(r1)
1095
1096 /*
1097 * Set up a dummy frame to store reset vector as return address.
1098 * this causes stack underflow to reset board.
1099 */
1100 stwu r1, -8(r1) /* Save back chain and move SP */
1101 lis r0, RESET_VECTOR@h /* Address of reset vector */
1102 ori r0, r0, RESET_VECTOR@l
1103 stwu r1, -8(r1) /* Save back chain and move SP */
1104 stw r0, +12(r1) /* Save return addr (underflow vect) */
1105#endif /* CFG_INIT_DCACHE_CS */
1106
1107 /*----------------------------------------------------------------------- */
f901a83b 1108 /* Initialize SDRAM Controller */
0442ed86
WD		 1109 /*----------------------------------------------------------------------- */
1110 bl sdram_init
1111
c440bfe6
SR		 1112#ifdef CONFIG_NAND_SPL
1113 bl nand_boot /* will not return */
1114#else
0442ed86
WD		 1115 GET_GOT /* initialize GOT access */
1116
f901a83b 1117 bl cpu_init_f /* run low-level CPU init code (from Flash) */
0442ed86
WD		 1118
1119 /* NEVER RETURNS! */
1120 bl board_init_f /* run first part of init code (from Flash) */
c440bfe6 1121#endif /* CONFIG_NAND_SPL */
0442ed86 1122
12f34241
WD		 1123#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1124 /*----------------------------------------------------------------------- */
0442ed86
WD		 1125
1126
887e2ec9 1127#ifndef CONFIG_NAND_SPL
0442ed86
WD		 1128/*
1129 * This code finishes saving the registers to the exception frame
1130 * and jumps to the appropriate handler for the exception.
1131 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1132 */
1133 .globl transfer_to_handler
1134transfer_to_handler:
1135 stw r22,_NIP(r21)
1136 lis r22,MSR_POW@h
1137 andc r23,r23,r22
1138 stw r23,_MSR(r21)
1139 SAVE_GPR(7, r21)
1140 SAVE_4GPRS(8, r21)
1141 SAVE_8GPRS(12, r21)
1142 SAVE_8GPRS(24, r21)
0442ed86
WD		 1143 mflr r23
1144 andi. r24,r23,0x3f00 /* get vector offset */
1145 stw r24,TRAP(r21)
1146 li r22,0
1147 stw r22,RESULT(r21)
1148 mtspr SPRG2,r22 /* r1 is now kernel sp */
0442ed86
WD		 1149 lwz r24,0(r23) /* virtual address of handler */
1150 lwz r23,4(r23) /* where to go when done */
1151 mtspr SRR0,r24
1152 mtspr SRR1,r20
1153 mtlr r23
1154 SYNC
1155 rfi /* jump to handler, enable MMU */
1156
1157int_return:
1158 mfmsr r28 /* Disable interrupts */
1159 li r4,0
1160 ori r4,r4,MSR_EE
1161 andc r28,r28,r4
1162 SYNC /* Some chip revs need this... */
1163 mtmsr r28
1164 SYNC
1165 lwz r2,_CTR(r1)
1166 lwz r0,_LINK(r1)
1167 mtctr r2
1168 mtlr r0
1169 lwz r2,_XER(r1)
1170 lwz r0,_CCR(r1)
1171 mtspr XER,r2
1172 mtcrf 0xFF,r0
1173 REST_10GPRS(3, r1)
1174 REST_10GPRS(13, r1)
1175 REST_8GPRS(23, r1)
1176 REST_GPR(31, r1)
1177 lwz r2,_NIP(r1) /* Restore environment */
1178 lwz r0,_MSR(r1)
1179 mtspr SRR0,r2
1180 mtspr SRR1,r0
1181 lwz r0,GPR0(r1)
1182 lwz r2,GPR2(r1)
1183 lwz r1,GPR1(r1)
1184 SYNC
1185 rfi
1186
1187crit_return:
1188 mfmsr r28 /* Disable interrupts */
1189 li r4,0
1190 ori r4,r4,MSR_EE
1191 andc r28,r28,r4
1192 SYNC /* Some chip revs need this... */
1193 mtmsr r28
1194 SYNC
1195 lwz r2,_CTR(r1)
1196 lwz r0,_LINK(r1)
1197 mtctr r2
1198 mtlr r0
1199 lwz r2,_XER(r1)
1200 lwz r0,_CCR(r1)
1201 mtspr XER,r2
1202 mtcrf 0xFF,r0
1203 REST_10GPRS(3, r1)
1204 REST_10GPRS(13, r1)
1205 REST_8GPRS(23, r1)
1206 REST_GPR(31, r1)
1207 lwz r2,_NIP(r1) /* Restore environment */
1208 lwz r0,_MSR(r1)
83b4cfa3
WD		 1209 mtspr csrr0,r2
1210 mtspr csrr1,r0
0442ed86
WD		 1211 lwz r0,GPR0(r1)
1212 lwz r2,GPR2(r1)
1213 lwz r1,GPR1(r1)
1214 SYNC
1215 rfci
1216
efa35cf1
GB		 1217#ifdef CONFIG_440
1218mck_return:
83b4cfa3
WD		 1219 mfmsr r28 /* Disable interrupts */
1220 li r4,0
1221 ori r4,r4,MSR_EE
1222 andc r28,r28,r4
1223 SYNC /* Some chip revs need this... */
1224 mtmsr r28
1225 SYNC
1226 lwz r2,_CTR(r1)
1227 lwz r0,_LINK(r1)
1228 mtctr r2
1229 mtlr r0
1230 lwz r2,_XER(r1)
1231 lwz r0,_CCR(r1)
1232 mtspr XER,r2
1233 mtcrf 0xFF,r0
1234 REST_10GPRS(3, r1)
1235 REST_10GPRS(13, r1)
1236 REST_8GPRS(23, r1)
1237 REST_GPR(31, r1)
1238 lwz r2,_NIP(r1) /* Restore environment */
1239 lwz r0,_MSR(r1)
1240 mtspr mcsrr0,r2
1241 mtspr mcsrr1,r0
1242 lwz r0,GPR0(r1)
1243 lwz r2,GPR2(r1)
1244 lwz r1,GPR1(r1)
1245 SYNC
1246 rfmci
efa35cf1
GB		 1247#endif /* CONFIG_440 */
1248
1249
0442ed86
WD		 1250 .globl get_pvr
1251get_pvr:
1252 mfspr r3, PVR
1253 blr
1254
0442ed86
WD		 1255/*------------------------------------------------------------------------------- */
1256/* Function: out16 */
1257/* Description: Output 16 bits */
1258/*------------------------------------------------------------------------------- */
1259 .globl out16
1260out16:
1261 sth r4,0x0000(r3)
1262 blr
1263
1264/*------------------------------------------------------------------------------- */
1265/* Function: out16r */
1266/* Description: Byte reverse and output 16 bits */
1267/*------------------------------------------------------------------------------- */
1268 .globl out16r
1269out16r:
1270 sthbrx r4,r0,r3
1271 blr
1272
0442ed86
WD		 1273/*------------------------------------------------------------------------------- */
1274/* Function: out32r */
1275/* Description: Byte reverse and output 32 bits */
1276/*------------------------------------------------------------------------------- */
1277 .globl out32r
1278out32r:
1279 stwbrx r4,r0,r3
1280 blr
1281
1282/*------------------------------------------------------------------------------- */
1283/* Function: in16 */
1284/* Description: Input 16 bits */
1285/*------------------------------------------------------------------------------- */
1286 .globl in16
1287in16:
1288 lhz r3,0x0000(r3)
1289 blr
1290
1291/*------------------------------------------------------------------------------- */
1292/* Function: in16r */
1293/* Description: Input 16 bits and byte reverse */
1294/*------------------------------------------------------------------------------- */
1295 .globl in16r
1296in16r:
1297 lhbrx r3,r0,r3
1298 blr
1299
0442ed86
WD		 1300/*------------------------------------------------------------------------------- */
1301/* Function: in32r */
1302/* Description: Input 32 bits and byte reverse */
1303/*------------------------------------------------------------------------------- */
1304 .globl in32r
1305in32r:
1306 lwbrx r3,r0,r3
1307 blr
1308
1309/*------------------------------------------------------------------------------- */
1310/* Function: ppcDcbf */
1311/* Description: Data Cache block flush */
1312/* Input: r3 = effective address */
1313/* Output: none. */
1314/*------------------------------------------------------------------------------- */
1315 .globl ppcDcbf
1316ppcDcbf:
1317 dcbf r0,r3
1318 blr
1319
1320/*------------------------------------------------------------------------------- */
1321/* Function: ppcDcbi */
1322/* Description: Data Cache block Invalidate */
1323/* Input: r3 = effective address */
1324/* Output: none. */
1325/*------------------------------------------------------------------------------- */
1326 .globl ppcDcbi
1327ppcDcbi:
1328 dcbi r0,r3
1329 blr
1330
1331/*------------------------------------------------------------------------------- */
1332/* Function: ppcSync */
1333/* Description: Processor Synchronize */
1334/* Input: none. */
1335/* Output: none. */
1336/*------------------------------------------------------------------------------- */
1337 .globl ppcSync
1338ppcSync:
1339 sync
1340 blr
1341
0442ed86
WD		 1342/*
1343 * void relocate_code (addr_sp, gd, addr_moni)
1344 *
1345 * This "function" does not return, instead it continues in RAM
1346 * after relocating the monitor code.
1347 *
1348 * r3 = dest
1349 * r4 = src
1350 * r5 = length in bytes
1351 * r6 = cachelinesize
1352 */
1353 .globl relocate_code
1354relocate_code:
9b94ac61
SR		 1355#ifdef CONFIG_4xx_DCACHE
1356 /*
1357 * We need to flush the Init Data before the dcache will be
1358 * invalidated
1359 */
1360
1361 /* save regs */
1362 mr r9,r3
1363 mr r10,r4
1364 mr r11,r5
1365
1366 mr r3,r4
1367 addi r4,r4,0x200 /* should be enough for init data */
1368 bl flush_dcache_range
1369
1370 /* restore regs */
1371 mr r3,r9
1372 mr r4,r10
1373 mr r5,r11
1374#endif
e02c521d
SR		 1375
1376#ifdef CFG_INIT_RAM_DCACHE
1377 /*
1378 * Unlock the previously locked d-cache
1379 */
1380 msync
1381 isync
1382 /* set TFLOOR/NFLOOR to 0 again */
1383 lis r6,0x0001
1384 ori r6,r6,0xf800
1385 mtspr dvlim,r6
1386 lis r6,0x0000
1387 ori r6,r6,0x0000
1388 mtspr dnv0,r6
1389 mtspr dnv1,r6
1390 mtspr dnv2,r6
1391 mtspr dnv3,r6
1392 mtspr dtv0,r6
1393 mtspr dtv1,r6
1394 mtspr dtv2,r6
1395 mtspr dtv3,r6
1396 msync
1397 isync
1398#endif /* CFG_INIT_RAM_DCACHE */
1399
887e2ec9
SR		 1400#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1401 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
00cdb4ce 1402 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
a4c8d138
SR		 1403 /*
1404 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1405 * to speed up the boot process. Now this cache needs to be disabled.
1406 */
1407 iccci 0,0 /* Invalidate inst cache */
1408 dccci 0,0 /* Invalidate data cache, now no longer our stack */
c157d8e2 1409 sync
a4c8d138 1410 isync
85dc2a7f
NG		 1411#ifdef CFG_TLB_FOR_BOOT_FLASH
1412 addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1413#else
1414 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1415#endif
c157d8e2 1416 tlbre r0,r1,0x0002 /* Read contents */
6e7fb6ea 1417 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
f901a83b 1418 tlbwe r0,r1,0x0002 /* Save it out */
a4c8d138 1419 sync
c157d8e2
SR		 1420 isync
1421#endif
0442ed86
WD		 1422 mr r1, r3 /* Set new stack pointer */
1423 mr r9, r4 /* Save copy of Init Data pointer */
1424 mr r10, r5 /* Save copy of Destination Address */
1425
1426 mr r3, r5 /* Destination Address */
1427 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1428 ori r4, r4, CFG_MONITOR_BASE@l
3b57fe0a
WD		 1429 lwz r5, GOT(__init_end)
1430 sub r5, r5, r4
9b94ac61 1431 li r6, L1_CACHE_BYTES /* Cache Line Size */
0442ed86
WD		 1432
1433 /*
1434 * Fix GOT pointer:
1435 *
1436 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1437 *
1438 * Offset:
1439 */
1440 sub r15, r10, r4
1441
1442 /* First our own GOT */
1443 add r14, r14, r15
1444 /* the the one used by the C code */
1445 add r30, r30, r15
1446
1447 /*
1448 * Now relocate code
1449 */
1450
1451 cmplw cr1,r3,r4
1452 addi r0,r5,3
1453 srwi. r0,r0,2
1454 beq cr1,4f /* In place copy is not necessary */
1455 beq 7f /* Protect against 0 count */
1456 mtctr r0
1457 bge cr1,2f
1458
1459 la r8,-4(r4)
1460 la r7,-4(r3)
14611: lwzu r0,4(r8)
1462 stwu r0,4(r7)
1463 bdnz 1b
1464 b 4f
1465
14662: slwi r0,r0,2
1467 add r8,r4,r0
1468 add r7,r3,r0
14693: lwzu r0,-4(r8)
1470 stwu r0,-4(r7)
1471 bdnz 3b
1472
1473/*
1474 * Now flush the cache: note that we must start from a cache aligned
1475 * address. Otherwise we might miss one cache line.
1476 */
14774: cmpwi r6,0
1478 add r5,r3,r5
1479 beq 7f /* Always flush prefetch queue in any case */
1480 subi r0,r6,1
1481 andc r3,r3,r0
1482 mr r4,r3
14835: dcbst 0,r4
1484 add r4,r4,r6
1485 cmplw r4,r5
1486 blt 5b
1487 sync /* Wait for all dcbst to complete on bus */
1488 mr r4,r3
14896: icbi 0,r4
1490 add r4,r4,r6
1491 cmplw r4,r5
1492 blt 6b
14937: sync /* Wait for all icbi to complete on bus */
1494 isync
1495
1496/*
1497 * We are done. Do not return, instead branch to second part of board
1498 * initialization, now running from RAM.
1499 */
1500
efa35cf1 1501 addi r0, r10, in_ram - _start + _START_OFFSET
0442ed86
WD		 1502 mtlr r0
1503 blr /* NEVER RETURNS! */
1504
1505in_ram:
1506
1507 /*
1508 * Relocation Function, r14 point to got2+0x8000
1509 *
1510 * Adjust got2 pointers, no need to check for 0, this code
1511 * already puts a few entries in the table.
1512 */
1513 li r0,__got2_entries@sectoff@l
1514 la r3,GOT(_GOT2_TABLE_)
1515 lwz r11,GOT(_GOT2_TABLE_)
1516 mtctr r0
1517 sub r11,r3,r11
1518 addi r3,r3,-4
15191: lwzu r0,4(r3)
1520 add r0,r0,r11
1521 stw r0,0(r3)
1522 bdnz 1b
1523
1524 /*
1525 * Now adjust the fixups and the pointers to the fixups
1526 * in case we need to move ourselves again.
1527 */
15282: li r0,__fixup_entries@sectoff@l
1529 lwz r3,GOT(_FIXUP_TABLE_)
1530 cmpwi r0,0
1531 mtctr r0
1532 addi r3,r3,-4
1533 beq 4f
15343: lwzu r4,4(r3)
1535 lwzux r0,r4,r11
1536 add r0,r0,r11
1537 stw r10,0(r3)
1538 stw r0,0(r4)
1539 bdnz 3b
15404:
1541clear_bss:
1542 /*
1543 * Now clear BSS segment
1544 */
5d232d0e 1545 lwz r3,GOT(__bss_start)
0442ed86
WD		 1546 lwz r4,GOT(_end)
1547
1548 cmplw 0, r3, r4
42ed33ff 1549 beq 7f
0442ed86
WD		 1550
1551 li r0, 0
42ed33ff
AG		 1552
1553 andi. r5, r4, 3
1554 beq 6f
1555 sub r4, r4, r5
1556 mtctr r5
1557 mr r5, r4
15585: stb r0, 0(r5)
1559 addi r5, r5, 1
1560 bdnz 5b
15616:
0442ed86
WD		 1562 stw r0, 0(r3)
1563 addi r3, r3, 4
1564 cmplw 0, r3, r4
42ed33ff 1565 bne 6b
0442ed86 1566
42ed33ff 15677:
0442ed86
WD		 1568 mr r3, r9 /* Init Data pointer */
1569 mr r4, r10 /* Destination Address */
1570 bl board_init_r
1571
0442ed86
WD		 1572 /*
1573 * Copy exception vector code to low memory
1574 *
1575 * r3: dest_addr
1576 * r7: source address, r8: end address, r9: target address
1577 */
1578 .globl trap_init
1579trap_init:
efa35cf1 1580 lwz r7, GOT(_start_of_vectors)
0442ed86
WD		 1581 lwz r8, GOT(_end_of_vectors)
1582
682011ff 1583 li r9, 0x100 /* reset vector always at 0x100 */
0442ed86
WD		 1584
1585 cmplw 0, r7, r8
1586 bgelr /* return if r7>=r8 - just in case */
1587
1588 mflr r4 /* save link register */
15891:
1590 lwz r0, 0(r7)
1591 stw r0, 0(r9)
1592 addi r7, r7, 4
1593 addi r9, r9, 4
1594 cmplw 0, r7, r8
1595 bne 1b
1596
1597 /*
1598 * relocate `hdlr' and `int_return' entries
1599 */
efa35cf1
GB		 1600 li r7, .L_MachineCheck - _start + _START_OFFSET
1601 li r8, Alignment - _start + _START_OFFSET
0442ed86
WD		 16022:
1603 bl trap_reloc
efa35cf1 1604 addi r7, r7, 0x100 /* next exception vector */
0442ed86
WD		 1605 cmplw 0, r7, r8
1606 blt 2b
1607
efa35cf1 1608 li r7, .L_Alignment - _start + _START_OFFSET
0442ed86
WD		 1609 bl trap_reloc
1610
efa35cf1 1611 li r7, .L_ProgramCheck - _start + _START_OFFSET
0442ed86
WD		 1612 bl trap_reloc
1613
efa35cf1
GB		 1614#ifdef CONFIG_440
1615 li r7, .L_FPUnavailable - _start + _START_OFFSET
83b4cfa3 1616 bl trap_reloc
0442ed86 1617
efa35cf1 1618 li r7, .L_Decrementer - _start + _START_OFFSET
83b4cfa3 1619 bl trap_reloc
efa35cf1
GB		 1620
1621 li r7, .L_APU - _start + _START_OFFSET
83b4cfa3 1622 bl trap_reloc
df8a24cd 1623
83b4cfa3
WD		 1624 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1625 bl trap_reloc
efa35cf1 1626
83b4cfa3
WD		 1627 li r7, .L_DataTLBError - _start + _START_OFFSET
1628 bl trap_reloc
efa35cf1
GB		 1629#else /* CONFIG_440 */
1630 li r7, .L_PIT - _start + _START_OFFSET
83b4cfa3 1631 bl trap_reloc
efa35cf1
GB		 1632
1633 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
83b4cfa3 1634 bl trap_reloc
efa35cf1
GB		 1635
1636 li r7, .L_DataTLBMiss - _start + _START_OFFSET
83b4cfa3 1637 bl trap_reloc
efa35cf1
GB		 1638#endif /* CONFIG_440 */
1639
83b4cfa3
WD		 1640 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1641 bl trap_reloc
0442ed86 1642
887e2ec9 1643#if !defined(CONFIG_440)
9a7b408c
SR		 1644 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1645 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1646 mtmsr r7 /* change MSR */
1647#else
887e2ec9
SR		 1648 bl __440_msr_set
1649 b __440_msr_continue
9a7b408c 1650
887e2ec9 1651__440_msr_set:
9a7b408c
SR		 1652 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1653 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1654 mtspr srr1,r7
1655 mflr r7
1656 mtspr srr0,r7
1657 rfi
887e2ec9 1658__440_msr_continue:
9a7b408c
SR		 1659#endif
1660
0442ed86
WD		 1661 mtlr r4 /* restore link register */
1662 blr
1663
1664 /*
1665 * Function: relocate entries for one exception vector
1666 */
1667trap_reloc:
1668 lwz r0, 0(r7) /* hdlr ... */
1669 add r0, r0, r3 /* ... += dest_addr */
1670 stw r0, 0(r7)
1671
1672 lwz r0, 4(r7) /* int_return ... */
1673 add r0, r0, r3 /* ... += dest_addr */
1674 stw r0, 4(r7)
1675
1676 blr
cf959c7d
SR		 1677
1678#if defined(CONFIG_440)
1679/*----------------------------------------------------------------------------+
1680| dcbz_area.
1681+----------------------------------------------------------------------------*/
1682 function_prolog(dcbz_area)
1683 rlwinm. r5,r4,0,27,31
83b4cfa3
WD		 1684 rlwinm r5,r4,27,5,31
1685 beq ..d_ra2
1686 addi r5,r5,0x0001
1687..d_ra2:mtctr r5
1688..d_ag2:dcbz r0,r3
1689 addi r3,r3,32
1690 bdnz ..d_ag2
cf959c7d
SR		 1691 sync
1692 blr
1693 function_epilog(dcbz_area)
1694
1695/*----------------------------------------------------------------------------+
1696| dflush. Assume 32K at vector address is cachable.
1697+----------------------------------------------------------------------------*/
1698 function_prolog(dflush)
83b4cfa3
WD		 1699 mfmsr r9
1700 rlwinm r8,r9,0,15,13
1701 rlwinm r8,r8,0,17,15
1702 mtmsr r8
6d8184b0 1703 mfspr r8,dvlim
83b4cfa3
WD		 1704 addi r3,r0,0x0000
1705 mtspr dvlim,r3
1706 mfspr r3,ivpr
1707 addi r4,r0,1024
1708 mtctr r4
cf959c7d 1709..dflush_loop:
83b4cfa3
WD		 1710 lwz r6,0x0(r3)
1711 addi r3,r3,32
1712 bdnz ..dflush_loop
1713 addi r3,r3,-32
1714 mtctr r4
1715..ag: dcbf r0,r3
1716 addi r3,r3,-32
1717 bdnz ..ag
6d8184b0 1718 mtspr dvlim,r8
cf959c7d 1719 sync
83b4cfa3 1720 mtmsr r9
cf959c7d
SR		 1721 blr
1722 function_epilog(dflush)
1723#endif /* CONFIG_440 */
887e2ec9 1724#endif /* CONFIG_NAND_SPL */
b867d705 1725
cf959c7d
SR		 1726/*------------------------------------------------------------------------------- */
1727/* Function: in8 */
1728/* Description: Input 8 bits */
1729/*------------------------------------------------------------------------------- */
1730 .globl in8
1731in8:
1732 lbz r3,0x0000(r3)
1733 blr
1734
1735/*------------------------------------------------------------------------------- */
1736/* Function: out8 */
1737/* Description: Output 8 bits */
1738/*------------------------------------------------------------------------------- */
1739 .globl out8
1740out8:
1741 stb r4,0x0000(r3)
1742 blr
1743
1744/*------------------------------------------------------------------------------- */
1745/* Function: out32 */
1746/* Description: Output 32 bits */
1747/*------------------------------------------------------------------------------- */
1748 .globl out32
1749out32:
1750 stw r4,0x0000(r3)
1751 blr
1752
1753/*------------------------------------------------------------------------------- */
1754/* Function: in32 */
1755/* Description: Input 32 bits */
1756/*------------------------------------------------------------------------------- */
1757 .globl in32
1758in32:
1759 lwz 3,0x0000(3)
1760 blr
b867d705
SR		 1761
1762/**************************************************************************/
f901a83b 1763/* PPC405EP specific stuff */
b867d705
SR		 1764/**************************************************************************/
1765#ifdef CONFIG_405EP
1766ppc405ep_init:
b828dda6 1767
c157d8e2 1768#ifdef CONFIG_BUBINGA
b828dda6
SR		 1769 /*
1770 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1771 * function) to support FPGA and NVRAM accesses below.
1772 */
1773
1774 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1775 ori r3,r3,GPIO0_OSRH@l
1776 lis r4,CFG_GPIO0_OSRH@h
1777 ori r4,r4,CFG_GPIO0_OSRH@l
1778 stw r4,0(r3)
1779 lis r3,GPIO0_OSRL@h
1780 ori r3,r3,GPIO0_OSRL@l
1781 lis r4,CFG_GPIO0_OSRL@h
1782 ori r4,r4,CFG_GPIO0_OSRL@l
1783 stw r4,0(r3)
1784
1785 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1786 ori r3,r3,GPIO0_ISR1H@l
1787 lis r4,CFG_GPIO0_ISR1H@h
1788 ori r4,r4,CFG_GPIO0_ISR1H@l
1789 stw r4,0(r3)
1790 lis r3,GPIO0_ISR1L@h
1791 ori r3,r3,GPIO0_ISR1L@l
1792 lis r4,CFG_GPIO0_ISR1L@h
1793 ori r4,r4,CFG_GPIO0_ISR1L@l
1794 stw r4,0(r3)
1795
1796 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1797 ori r3,r3,GPIO0_TSRH@l
1798 lis r4,CFG_GPIO0_TSRH@h
1799 ori r4,r4,CFG_GPIO0_TSRH@l
1800 stw r4,0(r3)
1801 lis r3,GPIO0_TSRL@h
1802 ori r3,r3,GPIO0_TSRL@l
1803 lis r4,CFG_GPIO0_TSRL@h
1804 ori r4,r4,CFG_GPIO0_TSRL@l
1805 stw r4,0(r3)
1806
1807 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1808 ori r3,r3,GPIO0_TCR@l
1809 lis r4,CFG_GPIO0_TCR@h
1810 ori r4,r4,CFG_GPIO0_TCR@l
1811 stw r4,0(r3)
1812
1813 li r3,pb1ap /* program EBC bank 1 for RTC access */
1814 mtdcr ebccfga,r3
1815 lis r3,CFG_EBC_PB1AP@h
1816 ori r3,r3,CFG_EBC_PB1AP@l
1817 mtdcr ebccfgd,r3
1818 li r3,pb1cr
1819 mtdcr ebccfga,r3
1820 lis r3,CFG_EBC_PB1CR@h
1821 ori r3,r3,CFG_EBC_PB1CR@l
1822 mtdcr ebccfgd,r3
1823
1824 li r3,pb1ap /* program EBC bank 1 for RTC access */
1825 mtdcr ebccfga,r3
1826 lis r3,CFG_EBC_PB1AP@h
1827 ori r3,r3,CFG_EBC_PB1AP@l
1828 mtdcr ebccfgd,r3
1829 li r3,pb1cr
1830 mtdcr ebccfga,r3
1831 lis r3,CFG_EBC_PB1CR@h
1832 ori r3,r3,CFG_EBC_PB1CR@l
1833 mtdcr ebccfgd,r3
1834
1835 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1836 mtdcr ebccfga,r3
1837 lis r3,CFG_EBC_PB4AP@h
1838 ori r3,r3,CFG_EBC_PB4AP@l
1839 mtdcr ebccfgd,r3
1840 li r3,pb4cr
1841 mtdcr ebccfga,r3
1842 lis r3,CFG_EBC_PB4CR@h
1843 ori r3,r3,CFG_EBC_PB4CR@l
1844 mtdcr ebccfgd,r3
1845#endif
8bde7f77
WD		 1846
1847 /*
1848 !-----------------------------------------------------------------------
1849 ! Check to see if chip is in bypass mode.
1850 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1851 ! CPU reset Otherwise, skip this step and keep going.
f901a83b
WD		 1852 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1853 ! will not be fast enough for the SDRAM (min 66MHz)
8bde7f77 1854 !-----------------------------------------------------------------------
b867d705 1855 */
f901a83b
WD		 1856 mfdcr r5, CPC0_PLLMR1
1857 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1858 cmpi cr0,0,r4,0x1
b867d705 1859
f901a83b 1860 beq pll_done /* if SSCS =b'1' then PLL has */
8bde7f77
WD		 1861 /* already been set */
1862 /* and CPU has been reset */
1863 /* so skip to next section */
b867d705 1864
c157d8e2 1865#ifdef CONFIG_BUBINGA
b867d705 1866 /*
8bde7f77
WD		 1867 !-----------------------------------------------------------------------
1868 ! Read NVRAM to get value to write in PLLMR.
1869 ! If value has not been correctly saved, write default value
1870 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1871 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1872 !
1873 ! WARNING: This code assumes the first three words in the nvram_t
f901a83b
WD		 1874 ! structure in openbios.h. Changing the beginning of
1875 ! the structure will break this code.
8bde7f77
WD		 1876 !
1877 !-----------------------------------------------------------------------
b867d705 1878 */
f901a83b
WD		 1879 addis r3,0,NVRAM_BASE@h
1880 addi r3,r3,NVRAM_BASE@l
1881
1882 lwz r4, 0(r3)
1883 addis r5,0,NVRVFY1@h
1884 addi r5,r5,NVRVFY1@l
1885 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1886 bne ..no_pllset
1887 addi r3,r3,4
1888 lwz r4, 0(r3)
1889 addis r5,0,NVRVFY2@h
1890 addi r5,r5,NVRVFY2@l
1891 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1892 bne ..no_pllset
1893 addi r3,r3,8 /* Skip over conf_size */
1894 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1895 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1896 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1897 cmpi cr0,0,r5,1 /* See if PLL is locked */
1898 beq pll_write
b867d705 1899..no_pllset:
c157d8e2 1900#endif /* CONFIG_BUBINGA */
b867d705 1901
d4024bb7
JO		 1902#ifdef CONFIG_TAIHU
1903 mfdcr r4, CPC0_BOOT
1904 andi. r5, r4, CPC0_BOOT_SEP@l
1905 bne strap_1 /* serial eeprom present */
1906 addis r5,0,CPLD_REG0_ADDR@h
1907 ori r5,r5,CPLD_REG0_ADDR@l
1908 andi. r5, r5, 0x10
1909 bne _pci_66mhz
1910#endif /* CONFIG_TAIHU */
1911
779e9751
SR		 1912#if defined(CONFIG_ZEUS)
1913 mfdcr r4, CPC0_BOOT
1914 andi. r5, r4, CPC0_BOOT_SEP@l
1915 bne strap_1 /* serial eeprom present */
1916 lis r3,0x0000
1917 addi r3,r3,0x3030
1918 lis r4,0x8042
1919 addi r4,r4,0x223e
1920 b 1f
1921strap_1:
1922 mfdcr r3, CPC0_PLLMR0
1923 mfdcr r4, CPC0_PLLMR1
1924 b 1f
1925#endif
1926
f901a83b
WD		 1927 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1928 ori r3,r3,PLLMR0_DEFAULT@l /* */
1929 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1930 ori r4,r4,PLLMR1_DEFAULT@l /* */
b867d705 1931
d4024bb7
JO		 1932#ifdef CONFIG_TAIHU
1933 b 1f
1934_pci_66mhz:
1935 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1936 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1937 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1938 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1939 b 1f
1940strap_1:
1941 mfdcr r3, CPC0_PLLMR0
1942 mfdcr r4, CPC0_PLLMR1
d4024bb7
JO		 1943#endif /* CONFIG_TAIHU */
1944
779e9751 19451:
f901a83b 1946 b pll_write /* Write the CPC0_PLLMR with new value */
b867d705
SR		 1947
1948pll_done:
8bde7f77
WD		 1949 /*
1950 !-----------------------------------------------------------------------
1951 ! Clear Soft Reset Register
1952 ! This is needed to enable PCI if not booting from serial EPROM
1953 !-----------------------------------------------------------------------
b867d705 1954 */
f901a83b
WD		 1955 addi r3, 0, 0x0
1956 mtdcr CPC0_SRR, r3
b867d705 1957
f901a83b
WD		 1958 addis r3,0,0x0010
1959 mtctr r3
b867d705 1960pci_wait:
f901a83b 1961 bdnz pci_wait
b867d705
SR		 1962
1963 blr /* return to main code */
1964
1965/*
1966!-----------------------------------------------------------------------------
f901a83b
WD		 1967! Function: pll_write
1968! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1969! That is:
1970! 1. Pll is first disabled (de-activated by putting in bypass mode)
1971! 2. PLL is reset
1972! 3. Clock dividers are set while PLL is held in reset and bypassed
1973! 4. PLL Reset is cleared
1974! 5. Wait 100us for PLL to lock
1975! 6. A core reset is performed
b867d705
SR		 1976! Input: r3 = Value to write to CPC0_PLLMR0
1977! Input: r4 = Value to write to CPC0_PLLMR1
1978! Output r3 = none
1979!-----------------------------------------------------------------------------
1980*/
1981pll_write:
8bde7f77
WD		 1982 mfdcr r5, CPC0_UCR
1983 andis. r5,r5,0xFFFF
f901a83b
WD		 1984 ori r5,r5,0x0101 /* Stop the UART clocks */
1985 mtdcr CPC0_UCR,r5 /* Before changing PLL */
8bde7f77
WD		 1986
1987 mfdcr r5, CPC0_PLLMR1
f901a83b
WD		 1988 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1989 mtdcr CPC0_PLLMR1,r5
1990 oris r5,r5,0x4000 /* Set PLL Reset */
1991 mtdcr CPC0_PLLMR1,r5
1992
1993 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1994 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1995 oris r5,r5,0x4000 /* Set PLL Reset */
1996 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1997 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1998 mtdcr CPC0_PLLMR1,r5
b867d705
SR		 1999
2000 /*
8bde7f77
WD		 2001 ! Wait min of 100us for PLL to lock.
2002 ! See CMOS 27E databook for more info.
2003 ! At 200MHz, that means waiting 20,000 instructions
b867d705 2004 */
f901a83b
WD		 2005 addi r3,0,20000 /* 2000 = 0x4e20 */
2006 mtctr r3
b867d705 2007pll_wait:
f901a83b 2008 bdnz pll_wait
8bde7f77 2009
f901a83b
WD		 2010 oris r5,r5,0x8000 /* Enable PLL */
2011 mtdcr CPC0_PLLMR1,r5 /* Engage */
8bde7f77
WD		 2012
2013 /*
2014 * Reset CPU to guarantee timings are OK
2015 * Not sure if this is needed...
2016 */
2017 addis r3,0,0x1000
f901a83b 2018 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
8bde7f77
WD		 2019 /* execution will continue from the poweron */
2020 /* vector of 0xfffffffc */
b867d705 2021#endif /* CONFIG_405EP */
4745acaa
SR		 2022
2023#if defined(CONFIG_440)
4745acaa
SR		 2024/*----------------------------------------------------------------------------+
2025| mttlb3.
2026+----------------------------------------------------------------------------*/
2027 function_prolog(mttlb3)
2028 TLBWE(4,3,2)
2029 blr
2030 function_epilog(mttlb3)
2031
2032/*----------------------------------------------------------------------------+
2033| mftlb3.
2034+----------------------------------------------------------------------------*/
2035 function_prolog(mftlb3)
74357114 2036 TLBRE(3,3,2)
4745acaa
SR		 2037 blr
2038 function_epilog(mftlb3)
2039
2040/*----------------------------------------------------------------------------+
2041| mttlb2.
2042+----------------------------------------------------------------------------*/
2043 function_prolog(mttlb2)
2044 TLBWE(4,3,1)
2045 blr
2046 function_epilog(mttlb2)
2047
2048/*----------------------------------------------------------------------------+
2049| mftlb2.
2050+----------------------------------------------------------------------------*/
2051 function_prolog(mftlb2)
74357114 2052 TLBRE(3,3,1)
4745acaa
SR		 2053 blr
2054 function_epilog(mftlb2)
2055
2056/*----------------------------------------------------------------------------+
2057| mttlb1.
2058+----------------------------------------------------------------------------*/
2059 function_prolog(mttlb1)
2060 TLBWE(4,3,0)
2061 blr
2062 function_epilog(mttlb1)
2063
2064/*----------------------------------------------------------------------------+
2065| mftlb1.
2066+----------------------------------------------------------------------------*/
2067 function_prolog(mftlb1)
74357114 2068 TLBRE(3,3,0)
4745acaa
SR		 2069 blr
2070 function_epilog(mftlb1)
2071#endif /* CONFIG_440 */
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