]>
Commit | Line | Data |
---|---|---|
c157d8e2 | 1 | /* |
7770ce47 | 2 | * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP. |
c157d8e2 SR |
3 | * |
4 | * (C) Copyright 2003-2004 | |
5 | * Gary Jennejohn, DENX Software Engineering <gj@denx.de> | |
6 | * | |
7 | * (C) Copyright 2004 | |
8 | * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com> | |
9 | * | |
10 | * Note: Much of this code has been derived from Linux 2.4 | |
11 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
12 | * (C) Copyright 2000-2002 David Brownell | |
13 | * | |
14 | * See file CREDITS for list of people who contributed to this | |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | * | |
32 | */ | |
33 | /* | |
34 | * IMPORTANT NOTES | |
35 | * 1 - this driver is intended for use with USB Mass Storage Devices | |
36 | * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! | |
37 | */ | |
38 | ||
39 | #include <common.h> | |
40 | ||
41 | #ifdef CONFIG_USB_OHCI | |
42 | ||
43 | #include <malloc.h> | |
44 | #include <usb.h> | |
45 | #include "usb_ohci.h" | |
7770ce47 | 46 | |
c157d8e2 SR |
47 | #include "usbdev.h" |
48 | ||
49 | #define OHCI_USE_NPS /* force NoPowerSwitching mode */ | |
50 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ | |
51 | #undef DEBUG | |
52 | #undef SHOW_INFO | |
53 | #undef OHCI_FILL_TRACE | |
54 | ||
55 | /* For initializing controller (mask in an HCFS mode too) */ | |
56 | #define OHCI_CONTROL_INIT \ | |
57 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
58 | ||
d00ce090 WD |
59 | #define readl(a) (*((volatile u32 *)(a))) |
60 | #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) | |
c157d8e2 SR |
61 | |
62 | #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) | |
63 | ||
64 | #ifdef DEBUG | |
65 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
66 | #else | |
67 | #define dbg(format, arg...) do {} while(0) | |
7770ce47 | 68 | #endif /* DEBUG */ |
c157d8e2 SR |
69 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) |
70 | #ifdef SHOW_INFO | |
71 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
72 | #else | |
73 | #define info(format, arg...) do {} while(0) | |
74 | #endif | |
75 | ||
76 | #define m16_swap(x) swap_16(x) | |
77 | #define m32_swap(x) swap_32(x) | |
78 | ||
e01bd218 | 79 | #if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX) |
c157d8e2 SR |
80 | #define ohci_cpu_to_le16(x) (x) |
81 | #define ohci_cpu_to_le32(x) (x) | |
82 | #else | |
83 | #define ohci_cpu_to_le16(x) swap_16(x) | |
84 | #define ohci_cpu_to_le32(x) swap_32(x) | |
85 | #endif | |
86 | ||
87 | /* global ohci_t */ | |
88 | static ohci_t gohci; | |
89 | /* this must be aligned to a 256 byte boundary */ | |
90 | struct ohci_hcca ghcca[1]; | |
91 | /* a pointer to the aligned storage */ | |
92 | struct ohci_hcca *phcca; | |
93 | /* this allocates EDs for all possible endpoints */ | |
94 | struct ohci_device ohci_dev; | |
95 | /* urb_priv */ | |
96 | urb_priv_t urb_priv; | |
97 | /* RHSC flag */ | |
98 | int got_rhsc; | |
99 | /* device which was disconnected */ | |
100 | struct usb_device *devgone; | |
7770ce47 SR |
101 | /* flag guarding URB transation */ |
102 | int urb_finished = 0; | |
c157d8e2 SR |
103 | |
104 | /*-------------------------------------------------------------------------*/ | |
105 | ||
106 | /* AMD-756 (D2 rev) reports corrupt register contents in some cases. | |
107 | * The erratum (#4) description is incorrect. AMD's workaround waits | |
108 | * till some bits (mostly reserved) are clear; ok for all revs. | |
109 | */ | |
110 | #define OHCI_QUIRK_AMD756 0xabcd | |
111 | #define read_roothub(hc, register, mask) ({ \ | |
112 | u32 temp = readl (&hc->regs->roothub.register); \ | |
113 | if (hc->flags & OHCI_QUIRK_AMD756) \ | |
114 | while (temp & mask) \ | |
115 | temp = readl (&hc->regs->roothub.register); \ | |
116 | temp; }) | |
117 | ||
7770ce47 SR |
118 | static u32 roothub_a (struct ohci *hc) |
119 | { return read_roothub (hc, a, 0xfc0fe000); } | |
120 | static inline u32 roothub_b (struct ohci *hc) | |
121 | { return readl (&hc->regs->roothub.b); } | |
122 | static inline u32 roothub_status (struct ohci *hc) | |
123 | { return readl (&hc->regs->roothub.status); } | |
124 | static u32 roothub_portstatus (struct ohci *hc, int i) | |
125 | { return read_roothub (hc, portstatus [i], 0xffe0fce0); } | |
126 | ||
c157d8e2 SR |
127 | |
128 | /* forward declaration */ | |
7770ce47 | 129 | static int hc_interrupt (void); |
c157d8e2 | 130 | static void |
7770ce47 SR |
131 | td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, |
132 | int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); | |
c157d8e2 SR |
133 | |
134 | /*-------------------------------------------------------------------------* | |
135 | * URB support functions | |
136 | *-------------------------------------------------------------------------*/ | |
137 | ||
138 | /* free HCD-private data associated with this URB */ | |
139 | ||
7770ce47 | 140 | static void urb_free_priv (urb_priv_t * urb) |
c157d8e2 | 141 | { |
7770ce47 SR |
142 | int i; |
143 | int last; | |
144 | struct td * td; | |
c157d8e2 SR |
145 | |
146 | last = urb->length - 1; | |
147 | if (last >= 0) { | |
148 | for (i = 0; i <= last; i++) { | |
149 | td = urb->td[i]; | |
150 | if (td) { | |
151 | td->usb_dev = NULL; | |
152 | urb->td[i] = NULL; | |
153 | } | |
154 | } | |
155 | } | |
156 | } | |
157 | ||
158 | /*-------------------------------------------------------------------------*/ | |
159 | ||
160 | #ifdef DEBUG | |
7770ce47 | 161 | static int sohci_get_current_frame_number (struct usb_device * dev); |
c157d8e2 SR |
162 | |
163 | /* debug| print the main components of an URB | |
164 | * small: 0) header + data packets 1) just header */ | |
165 | ||
7770ce47 SR |
166 | static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, |
167 | int transfer_len, struct devrequest * setup, char * str, int small) | |
c157d8e2 | 168 | { |
7770ce47 | 169 | urb_priv_t * purb = &urb_priv; |
c157d8e2 SR |
170 | |
171 | dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", | |
7770ce47 SR |
172 | str, |
173 | sohci_get_current_frame_number (dev), | |
174 | usb_pipedevice (pipe), | |
175 | usb_pipeendpoint (pipe), | |
176 | usb_pipeout (pipe)? 'O': 'I', | |
177 | usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): | |
178 | (usb_pipecontrol (pipe)? "CTRL": "BULK"), | |
179 | purb->actual_length, | |
180 | transfer_len, dev->status); | |
c157d8e2 SR |
181 | #ifdef OHCI_VERBOSE_DEBUG |
182 | if (!small) { | |
183 | int i, len; | |
184 | ||
7770ce47 SR |
185 | if (usb_pipecontrol (pipe)) { |
186 | printf (__FILE__ ": cmd(8):"); | |
187 | for (i = 0; i < 8 ; i++) | |
188 | printf (" %02x", ((__u8 *) setup) [i]); | |
189 | printf ("\n"); | |
c157d8e2 SR |
190 | } |
191 | if (transfer_len > 0 && buffer) { | |
7770ce47 SR |
192 | printf (__FILE__ ": data(%d/%d):", |
193 | purb->actual_length, | |
194 | transfer_len); | |
195 | len = usb_pipeout (pipe)? | |
196 | transfer_len: purb->actual_length; | |
c157d8e2 | 197 | for (i = 0; i < 16 && i < len; i++) |
7770ce47 SR |
198 | printf (" %02x", ((__u8 *) buffer) [i]); |
199 | printf ("%s\n", i < len? "...": ""); | |
c157d8e2 SR |
200 | } |
201 | } | |
202 | #endif | |
203 | } | |
204 | ||
205 | /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ | |
7770ce47 | 206 | void ep_print_int_eds (ohci_t *ohci, char * str) { |
c157d8e2 | 207 | int i, j; |
7770ce47 SR |
208 | __u32 * ed_p; |
209 | for (i= 0; i < 32; i++) { | |
c157d8e2 | 210 | j = 5; |
7770ce47 | 211 | ed_p = &(ohci->hcca->int_table [i]); |
c157d8e2 | 212 | if (*ed_p == 0) |
7770ce47 SR |
213 | continue; |
214 | printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); | |
c157d8e2 | 215 | while (*ed_p != 0 && j--) { |
7770ce47 SR |
216 | ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); |
217 | printf (" ed: %4x;", ed->hwINFO); | |
c157d8e2 SR |
218 | ed_p = &ed->hwNextED; |
219 | } | |
7770ce47 | 220 | printf ("\n"); |
c157d8e2 SR |
221 | } |
222 | } | |
223 | ||
7770ce47 | 224 | static void ohci_dump_intr_mask (char *label, __u32 mask) |
c157d8e2 | 225 | { |
7770ce47 SR |
226 | dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
227 | label, | |
228 | mask, | |
229 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
230 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
231 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
232 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
233 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
234 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
235 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
236 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
237 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
238 | ); | |
c157d8e2 SR |
239 | } |
240 | ||
7770ce47 | 241 | static void maybe_print_eds (char *label, __u32 value) |
c157d8e2 | 242 | { |
7770ce47 | 243 | ed_t *edp = (ed_t *)value; |
c157d8e2 SR |
244 | |
245 | if (value) { | |
7770ce47 SR |
246 | dbg ("%s %08x", label, value); |
247 | dbg ("%08x", edp->hwINFO); | |
248 | dbg ("%08x", edp->hwTailP); | |
249 | dbg ("%08x", edp->hwHeadP); | |
250 | dbg ("%08x", edp->hwNextED); | |
c157d8e2 SR |
251 | } |
252 | } | |
253 | ||
7770ce47 | 254 | static char * hcfs2string (int state) |
c157d8e2 SR |
255 | { |
256 | switch (state) { | |
7770ce47 SR |
257 | case OHCI_USB_RESET: return "reset"; |
258 | case OHCI_USB_RESUME: return "resume"; | |
259 | case OHCI_USB_OPER: return "operational"; | |
260 | case OHCI_USB_SUSPEND: return "suspend"; | |
c157d8e2 SR |
261 | } |
262 | return "?"; | |
263 | } | |
264 | ||
265 | /* dump control and status registers */ | |
7770ce47 | 266 | static void ohci_dump_status (ohci_t *controller) |
c157d8e2 | 267 | { |
7770ce47 SR |
268 | struct ohci_regs *regs = controller->regs; |
269 | __u32 temp; | |
c157d8e2 | 270 | |
7770ce47 | 271 | temp = readl (®s->revision) & 0xff; |
c157d8e2 | 272 | if (temp != 0x10) |
7770ce47 SR |
273 | dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
274 | ||
275 | temp = readl (®s->control); | |
276 | dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, | |
277 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", | |
278 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
279 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
280 | hcfs2string (temp & OHCI_CTRL_HCFS), | |
281 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", | |
282 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
283 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
284 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
285 | temp & OHCI_CTRL_CBSR | |
286 | ); | |
287 | ||
288 | temp = readl (®s->cmdstatus); | |
289 | dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, | |
290 | (temp & OHCI_SOC) >> 16, | |
291 | (temp & OHCI_OCR) ? " OCR" : "", | |
292 | (temp & OHCI_BLF) ? " BLF" : "", | |
293 | (temp & OHCI_CLF) ? " CLF" : "", | |
294 | (temp & OHCI_HCR) ? " HCR" : "" | |
295 | ); | |
296 | ||
297 | ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); | |
298 | ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); | |
299 | ||
300 | maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); | |
301 | ||
302 | maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); | |
303 | maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); | |
304 | ||
305 | maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); | |
306 | maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); | |
307 | ||
308 | maybe_print_eds ("donehead", readl (®s->donehead)); | |
c157d8e2 SR |
309 | } |
310 | ||
7770ce47 | 311 | static void ohci_dump_roothub (ohci_t *controller, int verbose) |
c157d8e2 | 312 | { |
7770ce47 | 313 | __u32 temp, ndp, i; |
c157d8e2 | 314 | |
7770ce47 | 315 | temp = roothub_a (controller); |
c157d8e2 SR |
316 | ndp = (temp & RH_A_NDP); |
317 | ||
318 | if (verbose) { | |
7770ce47 SR |
319 | dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
320 | ((temp & RH_A_POTPGT) >> 24) & 0xff, | |
321 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
322 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
323 | (temp & RH_A_DT) ? " DT" : "", | |
324 | (temp & RH_A_NPS) ? " NPS" : "", | |
325 | (temp & RH_A_PSM) ? " PSM" : "", | |
326 | ndp | |
327 | ); | |
328 | temp = roothub_b (controller); | |
329 | dbg ("roothub.b: %08x PPCM=%04x DR=%04x", | |
330 | temp, | |
331 | (temp & RH_B_PPCM) >> 16, | |
332 | (temp & RH_B_DR) | |
333 | ); | |
334 | temp = roothub_status (controller); | |
335 | dbg ("roothub.status: %08x%s%s%s%s%s%s", | |
336 | temp, | |
337 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
338 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
339 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
340 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
341 | (temp & RH_HS_OCI) ? " OCI" : "", | |
342 | (temp & RH_HS_LPS) ? " LPS" : "" | |
343 | ); | |
c157d8e2 SR |
344 | } |
345 | ||
346 | for (i = 0; i < ndp; i++) { | |
7770ce47 SR |
347 | temp = roothub_portstatus (controller, i); |
348 | dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
349 | i, | |
350 | temp, | |
351 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
352 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
353 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
354 | (temp & RH_PS_PESC) ? " PESC" : "", | |
355 | (temp & RH_PS_CSC) ? " CSC" : "", | |
356 | ||
357 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
358 | (temp & RH_PS_PPS) ? " PPS" : "", | |
359 | (temp & RH_PS_PRS) ? " PRS" : "", | |
360 | (temp & RH_PS_POCI) ? " POCI" : "", | |
361 | (temp & RH_PS_PSS) ? " PSS" : "", | |
362 | ||
363 | (temp & RH_PS_PES) ? " PES" : "", | |
364 | (temp & RH_PS_CCS) ? " CCS" : "" | |
365 | ); | |
c157d8e2 SR |
366 | } |
367 | } | |
368 | ||
7770ce47 | 369 | static void ohci_dump (ohci_t *controller, int verbose) |
c157d8e2 | 370 | { |
7770ce47 | 371 | dbg ("OHCI controller usb-%s state", controller->slot_name); |
c157d8e2 SR |
372 | |
373 | /* dumps some of the state we know about */ | |
7770ce47 | 374 | ohci_dump_status (controller); |
c157d8e2 | 375 | if (verbose) |
7770ce47 SR |
376 | ep_print_int_eds (controller, "hcca"); |
377 | dbg ("hcca frame #%04x", controller->hcca->frame_no); | |
378 | ohci_dump_roothub (controller, 1); | |
c157d8e2 SR |
379 | } |
380 | ||
7770ce47 SR |
381 | |
382 | #endif /* DEBUG */ | |
c157d8e2 SR |
383 | |
384 | /*-------------------------------------------------------------------------* | |
385 | * Interface functions (URB) | |
386 | *-------------------------------------------------------------------------*/ | |
387 | ||
388 | /* get a transfer request */ | |
389 | ||
390 | int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 391 | int transfer_len, struct devrequest *setup, int interval) |
c157d8e2 SR |
392 | { |
393 | ohci_t *ohci; | |
7770ce47 | 394 | ed_t * ed; |
c157d8e2 SR |
395 | urb_priv_t *purb_priv; |
396 | int i, size = 0; | |
397 | ||
398 | ohci = &gohci; | |
399 | ||
400 | /* when controller's hung, permit only roothub cleanup attempts | |
401 | * such as powering down ports */ | |
402 | if (ohci->disabled) { | |
403 | err("sohci_submit_job: EPIPE"); | |
404 | return -1; | |
405 | } | |
406 | ||
7770ce47 SR |
407 | /* if we have an unfinished URB from previous transaction let's |
408 | * fail and scream as quickly as possible so as not to corrupt | |
409 | * further communication */ | |
410 | if (!urb_finished) { | |
411 | err("sohci_submit_job: URB NOT FINISHED"); | |
412 | return -1; | |
413 | } | |
414 | /* we're about to begin a new transaction here so mark the URB unfinished */ | |
415 | urb_finished = 0; | |
416 | ||
c157d8e2 | 417 | /* every endpoint has a ed, locate and fill it */ |
7770ce47 | 418 | if (!(ed = ep_add_ed (dev, pipe))) { |
c157d8e2 SR |
419 | err("sohci_submit_job: ENOMEM"); |
420 | return -1; | |
421 | } | |
422 | ||
423 | /* for the private part of the URB we need the number of TDs (size) */ | |
7770ce47 SR |
424 | switch (usb_pipetype (pipe)) { |
425 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
426 | size = (transfer_len - 1) / 4096 + 1; | |
427 | break; | |
428 | case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
429 | size = (transfer_len == 0)? 2: | |
430 | (transfer_len - 1) / 4096 + 3; | |
431 | break; | |
c157d8e2 SR |
432 | } |
433 | ||
434 | if (size >= (N_URB_TD - 1)) { | |
435 | err("need %d TDs, only have %d", size, N_URB_TD); | |
436 | return -1; | |
437 | } | |
438 | purb_priv = &urb_priv; | |
439 | purb_priv->pipe = pipe; | |
440 | ||
441 | /* fill the private part of the URB */ | |
442 | purb_priv->length = size; | |
443 | purb_priv->ed = ed; | |
444 | purb_priv->actual_length = 0; | |
445 | ||
446 | /* allocate the TDs */ | |
447 | /* note that td[0] was allocated in ep_add_ed */ | |
448 | for (i = 0; i < size; i++) { | |
7770ce47 | 449 | purb_priv->td[i] = td_alloc (dev); |
c157d8e2 SR |
450 | if (!purb_priv->td[i]) { |
451 | purb_priv->length = i; | |
7770ce47 | 452 | urb_free_priv (purb_priv); |
c157d8e2 SR |
453 | err("sohci_submit_job: ENOMEM"); |
454 | return -1; | |
455 | } | |
456 | } | |
457 | ||
458 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
7770ce47 | 459 | urb_free_priv (purb_priv); |
c157d8e2 SR |
460 | err("sohci_submit_job: EINVAL"); |
461 | return -1; | |
462 | } | |
463 | ||
464 | /* link the ed into a chain if is not already */ | |
465 | if (ed->state != ED_OPER) | |
7770ce47 | 466 | ep_link (ohci, ed); |
c157d8e2 SR |
467 | |
468 | /* fill the TDs and link it to the ed */ | |
7770ce47 | 469 | td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); |
c157d8e2 SR |
470 | |
471 | return 0; | |
472 | } | |
473 | ||
474 | /*-------------------------------------------------------------------------*/ | |
475 | ||
476 | #ifdef DEBUG | |
477 | /* tell us the current USB frame number */ | |
478 | ||
7770ce47 | 479 | static int sohci_get_current_frame_number (struct usb_device *usb_dev) |
c157d8e2 SR |
480 | { |
481 | ohci_t *ohci = &gohci; | |
482 | ||
7770ce47 | 483 | return ohci_cpu_to_le16 (ohci->hcca->frame_no); |
c157d8e2 SR |
484 | } |
485 | #endif | |
486 | ||
487 | /*-------------------------------------------------------------------------* | |
488 | * ED handling functions | |
489 | *-------------------------------------------------------------------------*/ | |
490 | ||
491 | /* link an ed into one of the HC chains */ | |
492 | ||
7770ce47 | 493 | static int ep_link (ohci_t *ohci, ed_t *edi) |
c157d8e2 SR |
494 | { |
495 | volatile ed_t *ed = edi; | |
496 | ||
497 | ed->state = ED_OPER; | |
498 | ||
499 | switch (ed->type) { | |
500 | case PIPE_CONTROL: | |
501 | ed->hwNextED = 0; | |
502 | if (ohci->ed_controltail == NULL) { | |
7770ce47 | 503 | writel (ed, &ohci->regs->ed_controlhead); |
c157d8e2 | 504 | } else { |
7770ce47 | 505 | ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); |
c157d8e2 SR |
506 | } |
507 | ed->ed_prev = ohci->ed_controltail; | |
508 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
7770ce47 | 509 | !ohci->ed_rm_list[1] && !ohci->sleeping) { |
c157d8e2 | 510 | ohci->hc_control |= OHCI_CTRL_CLE; |
7770ce47 | 511 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
512 | } |
513 | ohci->ed_controltail = edi; | |
514 | break; | |
515 | ||
516 | case PIPE_BULK: | |
517 | ed->hwNextED = 0; | |
518 | if (ohci->ed_bulktail == NULL) { | |
7770ce47 | 519 | writel (ed, &ohci->regs->ed_bulkhead); |
c157d8e2 | 520 | } else { |
7770ce47 | 521 | ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); |
c157d8e2 SR |
522 | } |
523 | ed->ed_prev = ohci->ed_bulktail; | |
524 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
7770ce47 | 525 | !ohci->ed_rm_list[1] && !ohci->sleeping) { |
c157d8e2 | 526 | ohci->hc_control |= OHCI_CTRL_BLE; |
7770ce47 | 527 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
528 | } |
529 | ohci->ed_bulktail = edi; | |
530 | break; | |
531 | } | |
532 | return 0; | |
533 | } | |
534 | ||
535 | /*-------------------------------------------------------------------------*/ | |
536 | ||
537 | /* unlink an ed from one of the HC chains. | |
538 | * just the link to the ed is unlinked. | |
539 | * the link from the ed still points to another operational ed or 0 | |
540 | * so the HC can eventually finish the processing of the unlinked ed */ | |
541 | ||
7770ce47 | 542 | static int ep_unlink (ohci_t *ohci, ed_t *edi) |
c157d8e2 SR |
543 | { |
544 | volatile ed_t *ed = edi; | |
545 | ||
7770ce47 | 546 | ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); |
c157d8e2 SR |
547 | |
548 | switch (ed->type) { | |
549 | case PIPE_CONTROL: | |
550 | if (ed->ed_prev == NULL) { | |
551 | if (!ed->hwNextED) { | |
552 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
7770ce47 | 553 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 | 554 | } |
7770ce47 | 555 | writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); |
c157d8e2 SR |
556 | } else { |
557 | ed->ed_prev->hwNextED = ed->hwNextED; | |
558 | } | |
559 | if (ohci->ed_controltail == ed) { | |
560 | ohci->ed_controltail = ed->ed_prev; | |
561 | } else { | |
7770ce47 | 562 | ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; |
c157d8e2 SR |
563 | } |
564 | break; | |
565 | ||
566 | case PIPE_BULK: | |
567 | if (ed->ed_prev == NULL) { | |
568 | if (!ed->hwNextED) { | |
569 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
7770ce47 | 570 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 | 571 | } |
7770ce47 | 572 | writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); |
c157d8e2 SR |
573 | } else { |
574 | ed->ed_prev->hwNextED = ed->hwNextED; | |
575 | } | |
576 | if (ohci->ed_bulktail == ed) { | |
577 | ohci->ed_bulktail = ed->ed_prev; | |
578 | } else { | |
7770ce47 | 579 | ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; |
c157d8e2 SR |
580 | } |
581 | break; | |
582 | } | |
583 | ed->state = ED_UNLINK; | |
584 | return 0; | |
585 | } | |
586 | ||
7770ce47 | 587 | |
c157d8e2 SR |
588 | /*-------------------------------------------------------------------------*/ |
589 | ||
590 | /* add/reinit an endpoint; this should be done once at the usb_set_configuration command, | |
591 | * but the USB stack is a little bit stateless so we do it at every transaction | |
592 | * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK | |
593 | * in all other cases the state is left unchanged | |
594 | * the ed info fields are setted anyway even though most of them should not change */ | |
595 | ||
7770ce47 | 596 | static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) |
c157d8e2 SR |
597 | { |
598 | td_t *td; | |
599 | ed_t *ed_ret; | |
600 | volatile ed_t *ed; | |
601 | ||
7770ce47 SR |
602 | ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | |
603 | (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; | |
c157d8e2 SR |
604 | |
605 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
606 | err("ep_add_ed: pending delete"); | |
607 | /* pending delete request */ | |
608 | return NULL; | |
609 | } | |
610 | ||
611 | if (ed->state == ED_NEW) { | |
7770ce47 | 612 | ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ |
c157d8e2 | 613 | /* dummy td; end of td list for ed */ |
7770ce47 SR |
614 | td = td_alloc (usb_dev); |
615 | ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); | |
c157d8e2 SR |
616 | ed->hwHeadP = ed->hwTailP; |
617 | ed->state = ED_UNLINK; | |
7770ce47 | 618 | ed->type = usb_pipetype (pipe); |
c157d8e2 SR |
619 | ohci_dev.ed_cnt++; |
620 | } | |
621 | ||
7770ce47 SR |
622 | ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) |
623 | | usb_pipeendpoint (pipe) << 7 | |
624 | | (usb_pipeisoc (pipe)? 0x8000: 0) | |
625 | | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) | |
626 | | usb_pipeslow (pipe) << 13 | |
627 | | usb_maxpacket (usb_dev, pipe) << 16); | |
c157d8e2 SR |
628 | |
629 | return ed_ret; | |
630 | } | |
631 | ||
632 | /*-------------------------------------------------------------------------* | |
633 | * TD handling functions | |
634 | *-------------------------------------------------------------------------*/ | |
635 | ||
636 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
637 | ||
7770ce47 SR |
638 | static void td_fill (ohci_t *ohci, unsigned int info, |
639 | void *data, int len, | |
640 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
c157d8e2 | 641 | { |
7770ce47 | 642 | volatile td_t *td, *td_pt; |
c157d8e2 SR |
643 | #ifdef OHCI_FILL_TRACE |
644 | int i; | |
645 | #endif | |
646 | ||
647 | if (index > urb_priv->length) { | |
648 | err("index > length"); | |
649 | return; | |
650 | } | |
651 | /* use this td as the next dummy */ | |
7770ce47 | 652 | td_pt = urb_priv->td [index]; |
c157d8e2 SR |
653 | td_pt->hwNextTD = 0; |
654 | ||
655 | /* fill the old dummy TD */ | |
7770ce47 | 656 | td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); |
c157d8e2 SR |
657 | |
658 | td->ed = urb_priv->ed; | |
659 | td->next_dl_td = NULL; | |
660 | td->index = index; | |
7770ce47 | 661 | td->data = (__u32)data; |
c157d8e2 | 662 | #ifdef OHCI_FILL_TRACE |
7770ce47 | 663 | if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { |
c157d8e2 | 664 | for (i = 0; i < len; i++) |
7770ce47 | 665 | printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); |
c157d8e2 SR |
666 | printf("\n"); |
667 | } | |
668 | #endif | |
669 | if (!len) | |
670 | data = 0; | |
671 | ||
7770ce47 SR |
672 | td->hwINFO = ohci_cpu_to_le32 (info); |
673 | td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); | |
c157d8e2 | 674 | if (data) |
7770ce47 | 675 | td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); |
c157d8e2 SR |
676 | else |
677 | td->hwBE = 0; | |
7770ce47 | 678 | td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); |
c157d8e2 SR |
679 | |
680 | /* append to queue */ | |
681 | td->ed->hwTailP = td->hwNextTD; | |
682 | } | |
683 | ||
684 | /*-------------------------------------------------------------------------*/ | |
685 | ||
686 | /* prepare all TDs of a transfer */ | |
7770ce47 SR |
687 | static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, |
688 | int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) | |
c157d8e2 SR |
689 | { |
690 | ohci_t *ohci = &gohci; | |
691 | int data_len = transfer_len; | |
692 | void *data; | |
693 | int cnt = 0; | |
694 | __u32 info = 0; | |
695 | unsigned int toggle = 0; | |
696 | ||
697 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ | |
7770ce47 | 698 | if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { |
c157d8e2 SR |
699 | toggle = TD_T_TOGGLE; |
700 | } else { | |
701 | toggle = TD_T_DATA0; | |
7770ce47 | 702 | usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); |
c157d8e2 SR |
703 | } |
704 | urb->td_cnt = 0; | |
705 | if (data_len) | |
706 | data = buffer; | |
707 | else | |
708 | data = 0; | |
709 | ||
7770ce47 | 710 | switch (usb_pipetype (pipe)) { |
c157d8e2 | 711 | case PIPE_BULK: |
7770ce47 SR |
712 | info = usb_pipeout (pipe)? |
713 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; | |
714 | while(data_len > 4096) { | |
715 | td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); | |
716 | data += 4096; data_len -= 4096; cnt++; | |
c157d8e2 | 717 | } |
7770ce47 SR |
718 | info = usb_pipeout (pipe)? |
719 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; | |
720 | td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); | |
c157d8e2 SR |
721 | cnt++; |
722 | ||
723 | if (!ohci->sleeping) | |
7770ce47 | 724 | writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ |
c157d8e2 SR |
725 | break; |
726 | ||
727 | case PIPE_CONTROL: | |
728 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; | |
7770ce47 | 729 | td_fill (ohci, info, setup, 8, dev, cnt++, urb); |
c157d8e2 | 730 | if (data_len > 0) { |
7770ce47 SR |
731 | info = usb_pipeout (pipe)? |
732 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
c157d8e2 | 733 | /* NOTE: mishandles transfers >8K, some >4K */ |
7770ce47 | 734 | td_fill (ohci, info, data, data_len, dev, cnt++, urb); |
c157d8e2 | 735 | } |
7770ce47 SR |
736 | info = usb_pipeout (pipe)? |
737 | TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; | |
738 | td_fill (ohci, info, data, 0, dev, cnt++, urb); | |
c157d8e2 | 739 | if (!ohci->sleeping) |
7770ce47 | 740 | writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ |
c157d8e2 SR |
741 | break; |
742 | } | |
743 | if (urb->length != cnt) | |
744 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
745 | } | |
746 | ||
747 | /*-------------------------------------------------------------------------* | |
748 | * Done List handling functions | |
749 | *-------------------------------------------------------------------------*/ | |
750 | ||
7770ce47 | 751 | |
c157d8e2 SR |
752 | /* calculate the transfer length and update the urb */ |
753 | ||
754 | static void dl_transfer_length(td_t * td) | |
755 | { | |
756 | __u32 tdINFO, tdBE, tdCBP; | |
757 | urb_priv_t *lurb_priv = &urb_priv; | |
758 | ||
7770ce47 SR |
759 | tdINFO = ohci_cpu_to_le32 (td->hwINFO); |
760 | tdBE = ohci_cpu_to_le32 (td->hwBE); | |
761 | tdCBP = ohci_cpu_to_le32 (td->hwCBP); | |
c157d8e2 | 762 | |
7770ce47 SR |
763 | |
764 | if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && | |
765 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { | |
c157d8e2 SR |
766 | if (tdBE != 0) { |
767 | if (td->hwCBP == 0) | |
768 | lurb_priv->actual_length += tdBE - td->data + 1; | |
769 | else | |
770 | lurb_priv->actual_length += tdCBP - td->data; | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
775 | /*-------------------------------------------------------------------------*/ | |
776 | ||
777 | /* replies to the request have to be on a FIFO basis so | |
778 | * we reverse the reversed done-list */ | |
779 | ||
7770ce47 | 780 | static td_t * dl_reverse_done_list (ohci_t *ohci) |
c157d8e2 SR |
781 | { |
782 | __u32 td_list_hc; | |
783 | td_t *td_rev = NULL; | |
784 | td_t *td_list = NULL; | |
785 | urb_priv_t *lurb_priv = NULL; | |
786 | ||
7770ce47 | 787 | td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; |
c157d8e2 SR |
788 | ohci->hcca->done_head = 0; |
789 | ||
790 | while (td_list_hc) { | |
7770ce47 | 791 | td_list = (td_t *)td_list_hc; |
c157d8e2 | 792 | |
7770ce47 | 793 | if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { |
c157d8e2 SR |
794 | lurb_priv = &urb_priv; |
795 | dbg(" USB-error/status: %x : %p", | |
7770ce47 SR |
796 | TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); |
797 | if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { | |
798 | if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { | |
c157d8e2 | 799 | td_list->ed->hwHeadP = |
7770ce47 SR |
800 | (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | |
801 | (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); | |
802 | lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; | |
c157d8e2 | 803 | } else |
7770ce47 | 804 | td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); |
c157d8e2 SR |
805 | } |
806 | #ifdef CONFIG_MPC5200 | |
807 | td_list->hwNextTD = 0; | |
808 | #endif | |
809 | } | |
810 | ||
811 | td_list->next_dl_td = td_rev; | |
812 | td_rev = td_list; | |
7770ce47 | 813 | td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; |
c157d8e2 SR |
814 | } |
815 | return td_list; | |
816 | } | |
817 | ||
818 | /*-------------------------------------------------------------------------*/ | |
819 | ||
820 | /* td done list */ | |
7770ce47 | 821 | static int dl_done_list (ohci_t *ohci, td_t *td_list) |
c157d8e2 SR |
822 | { |
823 | td_t *td_list_next = NULL; | |
824 | ed_t *ed; | |
825 | int cc = 0; | |
7770ce47 | 826 | int stat = 0; |
c157d8e2 SR |
827 | /* urb_t *urb; */ |
828 | urb_priv_t *lurb_priv; | |
829 | __u32 tdINFO, edHeadP, edTailP; | |
830 | ||
831 | while (td_list) { | |
832 | td_list_next = td_list->next_dl_td; | |
833 | ||
834 | lurb_priv = &urb_priv; | |
7770ce47 | 835 | tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); |
c157d8e2 SR |
836 | |
837 | ed = td_list->ed; | |
838 | ||
839 | dl_transfer_length(td_list); | |
840 | ||
841 | /* error code of transfer */ | |
7770ce47 | 842 | cc = TD_CC_GET (tdINFO); |
c157d8e2 SR |
843 | if (++(lurb_priv->td_cnt) == lurb_priv->length) { |
844 | if ((ed->state & (ED_OPER | ED_UNLINK)) | |
7770ce47 | 845 | && (lurb_priv->state != URB_DEL)) { |
c157d8e2 SR |
846 | dbg("ConditionCode %#x", cc); |
847 | stat = cc_to_error[cc]; | |
7770ce47 | 848 | urb_finished = 1; |
c157d8e2 SR |
849 | } |
850 | } | |
851 | ||
852 | if (ed->state != ED_NEW) { | |
7770ce47 SR |
853 | edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; |
854 | edTailP = ohci_cpu_to_le32 (ed->hwTailP); | |
c157d8e2 SR |
855 | |
856 | /* unlink eds if they are not busy */ | |
857 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
7770ce47 | 858 | ep_unlink (ohci, ed); |
c157d8e2 SR |
859 | } |
860 | ||
861 | td_list = td_list_next; | |
862 | } | |
863 | return stat; | |
864 | } | |
865 | ||
866 | /*-------------------------------------------------------------------------* | |
867 | * Virtual Root Hub | |
868 | *-------------------------------------------------------------------------*/ | |
869 | ||
870 | /* Device descriptor */ | |
7770ce47 SR |
871 | static __u8 root_hub_dev_des[] = |
872 | { | |
873 | 0x12, /* __u8 bLength; */ | |
874 | 0x01, /* __u8 bDescriptorType; Device */ | |
875 | 0x10, /* __u16 bcdUSB; v1.1 */ | |
c157d8e2 | 876 | 0x01, |
7770ce47 SR |
877 | 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ |
878 | 0x00, /* __u8 bDeviceSubClass; */ | |
879 | 0x00, /* __u8 bDeviceProtocol; */ | |
880 | 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ | |
881 | 0x00, /* __u16 idVendor; */ | |
c157d8e2 | 882 | 0x00, |
7770ce47 | 883 | 0x00, /* __u16 idProduct; */ |
c157d8e2 | 884 | 0x00, |
7770ce47 | 885 | 0x00, /* __u16 bcdDevice; */ |
c157d8e2 | 886 | 0x00, |
7770ce47 SR |
887 | 0x00, /* __u8 iManufacturer; */ |
888 | 0x01, /* __u8 iProduct; */ | |
889 | 0x00, /* __u8 iSerialNumber; */ | |
890 | 0x01 /* __u8 bNumConfigurations; */ | |
c157d8e2 SR |
891 | }; |
892 | ||
7770ce47 | 893 | |
c157d8e2 | 894 | /* Configuration descriptor */ |
7770ce47 SR |
895 | static __u8 root_hub_config_des[] = |
896 | { | |
897 | 0x09, /* __u8 bLength; */ | |
898 | 0x02, /* __u8 bDescriptorType; Configuration */ | |
899 | 0x19, /* __u16 wTotalLength; */ | |
c157d8e2 | 900 | 0x00, |
7770ce47 SR |
901 | 0x01, /* __u8 bNumInterfaces; */ |
902 | 0x01, /* __u8 bConfigurationValue; */ | |
903 | 0x00, /* __u8 iConfiguration; */ | |
904 | 0x40, /* __u8 bmAttributes; | |
905 | Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ | |
906 | 0x00, /* __u8 MaxPower; */ | |
c157d8e2 SR |
907 | |
908 | /* interface */ | |
7770ce47 SR |
909 | 0x09, /* __u8 if_bLength; */ |
910 | 0x04, /* __u8 if_bDescriptorType; Interface */ | |
911 | 0x00, /* __u8 if_bInterfaceNumber; */ | |
912 | 0x00, /* __u8 if_bAlternateSetting; */ | |
913 | 0x01, /* __u8 if_bNumEndpoints; */ | |
914 | 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ | |
915 | 0x00, /* __u8 if_bInterfaceSubClass; */ | |
916 | 0x00, /* __u8 if_bInterfaceProtocol; */ | |
917 | 0x00, /* __u8 if_iInterface; */ | |
c157d8e2 SR |
918 | |
919 | /* endpoint */ | |
7770ce47 SR |
920 | 0x07, /* __u8 ep_bLength; */ |
921 | 0x05, /* __u8 ep_bDescriptorType; Endpoint */ | |
922 | 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ | |
923 | 0x03, /* __u8 ep_bmAttributes; Interrupt */ | |
924 | 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ | |
c157d8e2 | 925 | 0x00, |
7770ce47 | 926 | 0xff /* __u8 ep_bInterval; 255 ms */ |
c157d8e2 SR |
927 | }; |
928 | ||
7770ce47 SR |
929 | static unsigned char root_hub_str_index0[] = |
930 | { | |
c157d8e2 SR |
931 | 0x04, /* __u8 bLength; */ |
932 | 0x03, /* __u8 bDescriptorType; String-descriptor */ | |
933 | 0x09, /* __u8 lang ID */ | |
934 | 0x04, /* __u8 lang ID */ | |
935 | }; | |
936 | ||
7770ce47 SR |
937 | static unsigned char root_hub_str_index1[] = |
938 | { | |
c157d8e2 SR |
939 | 28, /* __u8 bLength; */ |
940 | 0x03, /* __u8 bDescriptorType; String-descriptor */ | |
941 | 'O', /* __u8 Unicode */ | |
7770ce47 | 942 | 0, /* __u8 Unicode */ |
c157d8e2 | 943 | 'H', /* __u8 Unicode */ |
7770ce47 | 944 | 0, /* __u8 Unicode */ |
c157d8e2 | 945 | 'C', /* __u8 Unicode */ |
7770ce47 | 946 | 0, /* __u8 Unicode */ |
c157d8e2 | 947 | 'I', /* __u8 Unicode */ |
7770ce47 | 948 | 0, /* __u8 Unicode */ |
c157d8e2 | 949 | ' ', /* __u8 Unicode */ |
7770ce47 | 950 | 0, /* __u8 Unicode */ |
c157d8e2 | 951 | 'R', /* __u8 Unicode */ |
7770ce47 | 952 | 0, /* __u8 Unicode */ |
c157d8e2 | 953 | 'o', /* __u8 Unicode */ |
7770ce47 | 954 | 0, /* __u8 Unicode */ |
c157d8e2 | 955 | 'o', /* __u8 Unicode */ |
7770ce47 | 956 | 0, /* __u8 Unicode */ |
c157d8e2 | 957 | 't', /* __u8 Unicode */ |
7770ce47 | 958 | 0, /* __u8 Unicode */ |
c157d8e2 | 959 | ' ', /* __u8 Unicode */ |
7770ce47 | 960 | 0, /* __u8 Unicode */ |
c157d8e2 | 961 | 'H', /* __u8 Unicode */ |
7770ce47 | 962 | 0, /* __u8 Unicode */ |
c157d8e2 | 963 | 'u', /* __u8 Unicode */ |
7770ce47 | 964 | 0, /* __u8 Unicode */ |
c157d8e2 | 965 | 'b', /* __u8 Unicode */ |
7770ce47 | 966 | 0, /* __u8 Unicode */ |
c157d8e2 SR |
967 | }; |
968 | ||
969 | /* Hub class-specific descriptor is constructed dynamically */ | |
970 | ||
7770ce47 | 971 | |
c157d8e2 SR |
972 | /*-------------------------------------------------------------------------*/ |
973 | ||
974 | #define OK(x) len = (x); break | |
975 | #ifdef DEBUG | |
976 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} | |
977 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} | |
978 | #else | |
979 | #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) | |
980 | #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) | |
981 | #endif | |
982 | #define RD_RH_STAT roothub_status(&gohci) | |
983 | #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) | |
984 | ||
985 | /* request to virtual root hub */ | |
986 | ||
7770ce47 | 987 | int rh_check_port_status(ohci_t *controller) |
c157d8e2 SR |
988 | { |
989 | __u32 temp, ndp, i; | |
990 | int res; | |
991 | ||
992 | res = -1; | |
7770ce47 | 993 | temp = roothub_a (controller); |
c157d8e2 SR |
994 | ndp = (temp & RH_A_NDP); |
995 | for (i = 0; i < ndp; i++) { | |
7770ce47 | 996 | temp = roothub_portstatus (controller, i); |
c157d8e2 SR |
997 | /* check for a device disconnect */ |
998 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
7770ce47 SR |
999 | (RH_PS_PESC | RH_PS_CSC)) && |
1000 | ((temp & RH_PS_CCS) == 0)) { | |
c157d8e2 SR |
1001 | res = i; |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | return res; | |
1006 | } | |
1007 | ||
1008 | static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, | |
7770ce47 | 1009 | void *buffer, int transfer_len, struct devrequest *cmd) |
c157d8e2 | 1010 | { |
7770ce47 | 1011 | void * data = buffer; |
c157d8e2 SR |
1012 | int leni = transfer_len; |
1013 | int len = 0; | |
1014 | int stat = 0; | |
1015 | __u32 datab[4]; | |
7770ce47 | 1016 | __u8 *data_buf = (__u8 *)datab; |
c157d8e2 SR |
1017 | __u16 bmRType_bReq; |
1018 | __u16 wValue; | |
1019 | __u16 wIndex; | |
1020 | __u16 wLength; | |
1021 | ||
1022 | #ifdef DEBUG | |
7770ce47 SR |
1023 | urb_priv.actual_length = 0; |
1024 | pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); | |
c157d8e2 SR |
1025 | #endif |
1026 | if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { | |
1027 | info("Root-Hub submit IRQ: NOT implemented"); | |
1028 | return 0; | |
1029 | } | |
1030 | ||
7770ce47 SR |
1031 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); |
1032 | wValue = m16_swap (cmd->value); | |
1033 | wIndex = m16_swap (cmd->index); | |
1034 | wLength = m16_swap (cmd->length); | |
c157d8e2 SR |
1035 | |
1036 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
7770ce47 | 1037 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); |
c157d8e2 SR |
1038 | |
1039 | switch (bmRType_bReq) { | |
7770ce47 SR |
1040 | /* Request Destination: |
1041 | without flags: Device, | |
1042 | RH_INTERFACE: interface, | |
1043 | RH_ENDPOINT: endpoint, | |
1044 | RH_CLASS means HUB here, | |
1045 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1046 | */ | |
c157d8e2 SR |
1047 | |
1048 | case RH_GET_STATUS: | |
7770ce47 | 1049 | *(__u16 *) data_buf = m16_swap (1); OK (2); |
c157d8e2 | 1050 | case RH_GET_STATUS | RH_INTERFACE: |
7770ce47 | 1051 | *(__u16 *) data_buf = m16_swap (0); OK (2); |
c157d8e2 | 1052 | case RH_GET_STATUS | RH_ENDPOINT: |
7770ce47 | 1053 | *(__u16 *) data_buf = m16_swap (0); OK (2); |
c157d8e2 | 1054 | case RH_GET_STATUS | RH_CLASS: |
7770ce47 SR |
1055 | *(__u32 *) data_buf = m32_swap ( |
1056 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); | |
1057 | OK (4); | |
c157d8e2 | 1058 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
7770ce47 | 1059 | *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); |
c157d8e2 SR |
1060 | |
1061 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1062 | switch (wValue) { | |
7770ce47 | 1063 | case (RH_ENDPOINT_STALL): OK (0); |
c157d8e2 SR |
1064 | } |
1065 | break; | |
1066 | ||
1067 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1068 | switch (wValue) { | |
7770ce47 SR |
1069 | case RH_C_HUB_LOCAL_POWER: |
1070 | OK(0); | |
1071 | case (RH_C_HUB_OVER_CURRENT): | |
1072 | WR_RH_STAT(RH_HS_OCIC); OK (0); | |
c157d8e2 SR |
1073 | } |
1074 | break; | |
1075 | ||
1076 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1077 | switch (wValue) { | |
7770ce47 SR |
1078 | case (RH_PORT_ENABLE): |
1079 | WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); | |
1080 | case (RH_PORT_SUSPEND): | |
1081 | WR_RH_PORTSTAT (RH_PS_POCI); OK (0); | |
1082 | case (RH_PORT_POWER): | |
1083 | WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); | |
1084 | case (RH_C_PORT_CONNECTION): | |
1085 | WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); | |
1086 | case (RH_C_PORT_ENABLE): | |
1087 | WR_RH_PORTSTAT (RH_PS_PESC); OK (0); | |
1088 | case (RH_C_PORT_SUSPEND): | |
1089 | WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); | |
1090 | case (RH_C_PORT_OVER_CURRENT): | |
1091 | WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); | |
1092 | case (RH_C_PORT_RESET): | |
1093 | WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); | |
c157d8e2 SR |
1094 | } |
1095 | break; | |
1096 | ||
1097 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1098 | switch (wValue) { | |
7770ce47 SR |
1099 | case (RH_PORT_SUSPEND): |
1100 | WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); | |
1101 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1102 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1103 | WR_RH_PORTSTAT (RH_PS_PRS); | |
1104 | OK (0); | |
1105 | case (RH_PORT_POWER): | |
1106 | WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); | |
1107 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1108 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1109 | WR_RH_PORTSTAT (RH_PS_PES ); | |
1110 | OK (0); | |
c157d8e2 SR |
1111 | } |
1112 | break; | |
1113 | ||
7770ce47 | 1114 | case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); |
c157d8e2 SR |
1115 | |
1116 | case RH_GET_DESCRIPTOR: | |
1117 | switch ((wValue & 0xff00) >> 8) { | |
7770ce47 | 1118 | case (0x01): /* device descriptor */ |
c157d8e2 | 1119 | len = min_t(unsigned int, |
7770ce47 SR |
1120 | leni, |
1121 | min_t(unsigned int, | |
1122 | sizeof (root_hub_dev_des), | |
1123 | wLength)); | |
1124 | data_buf = root_hub_dev_des; OK(len); | |
1125 | case (0x02): /* configuration descriptor */ | |
c157d8e2 | 1126 | len = min_t(unsigned int, |
7770ce47 SR |
1127 | leni, |
1128 | min_t(unsigned int, | |
1129 | sizeof (root_hub_config_des), | |
1130 | wLength)); | |
1131 | data_buf = root_hub_config_des; OK(len); | |
1132 | case (0x03): /* string descriptors */ | |
1133 | if(wValue==0x0300) { | |
1134 | len = min_t(unsigned int, | |
1135 | leni, | |
1136 | min_t(unsigned int, | |
1137 | sizeof (root_hub_str_index0), | |
1138 | wLength)); | |
1139 | data_buf = root_hub_str_index0; | |
1140 | OK(len); | |
1141 | } | |
1142 | if(wValue==0x0301) { | |
1143 | len = min_t(unsigned int, | |
1144 | leni, | |
1145 | min_t(unsigned int, | |
1146 | sizeof (root_hub_str_index1), | |
1147 | wLength)); | |
1148 | data_buf = root_hub_str_index1; | |
1149 | OK(len); | |
c157d8e2 | 1150 | } |
7770ce47 SR |
1151 | default: |
1152 | stat = USB_ST_STALLED; | |
c157d8e2 SR |
1153 | } |
1154 | break; | |
1155 | ||
1156 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
7770ce47 SR |
1157 | { |
1158 | __u32 temp = roothub_a (&gohci); | |
1159 | ||
1160 | data_buf [0] = 9; /* min length; */ | |
1161 | data_buf [1] = 0x29; | |
1162 | data_buf [2] = temp & RH_A_NDP; | |
1163 | data_buf [3] = 0; | |
1164 | if (temp & RH_A_PSM) /* per-port power switching? */ | |
1165 | data_buf [3] |= 0x1; | |
1166 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ | |
1167 | data_buf [3] |= 0x10; | |
1168 | else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ | |
1169 | data_buf [3] |= 0x8; | |
1170 | ||
1171 | /* corresponds to data_buf[4-7] */ | |
1172 | datab [1] = 0; | |
1173 | data_buf [5] = (temp & RH_A_POTPGT) >> 24; | |
1174 | temp = roothub_b (&gohci); | |
1175 | data_buf [7] = temp & RH_B_DR; | |
1176 | if (data_buf [2] < 7) { | |
1177 | data_buf [8] = 0xff; | |
1178 | } else { | |
1179 | data_buf [0] += 2; | |
1180 | data_buf [8] = (temp & RH_B_DR) >> 8; | |
1181 | data_buf [10] = data_buf [9] = 0xff; | |
1182 | } | |
1183 | ||
1184 | len = min_t(unsigned int, leni, | |
1185 | min_t(unsigned int, data_buf [0], wLength)); | |
1186 | OK (len); | |
c157d8e2 SR |
1187 | } |
1188 | ||
7770ce47 | 1189 | case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); |
c157d8e2 | 1190 | |
7770ce47 | 1191 | case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); |
c157d8e2 SR |
1192 | |
1193 | default: | |
7770ce47 | 1194 | dbg ("unsupported root hub command"); |
c157d8e2 SR |
1195 | stat = USB_ST_STALLED; |
1196 | } | |
1197 | ||
1198 | #ifdef DEBUG | |
7770ce47 | 1199 | ohci_dump_roothub (&gohci, 1); |
c157d8e2 SR |
1200 | #endif |
1201 | ||
1202 | len = min_t(int, len, leni); | |
1203 | if (data != data_buf) | |
7770ce47 | 1204 | memcpy (data, data_buf, len); |
c157d8e2 SR |
1205 | dev->act_len = len; |
1206 | dev->status = stat; | |
1207 | ||
1208 | #ifdef DEBUG | |
1209 | if (transfer_len) | |
1210 | urb_priv.actual_length = transfer_len; | |
7770ce47 | 1211 | pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
c157d8e2 SR |
1212 | #endif |
1213 | ||
1214 | return stat; | |
1215 | } | |
1216 | ||
1217 | /*-------------------------------------------------------------------------*/ | |
1218 | ||
1219 | /* common code for handling submit messages - used for all but root hub */ | |
1220 | /* accesses. */ | |
1221 | int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1222 | int transfer_len, struct devrequest *setup, int interval) |
c157d8e2 SR |
1223 | { |
1224 | int stat = 0; | |
1225 | int maxsize = usb_maxpacket(dev, pipe); | |
1226 | int timeout; | |
1227 | ||
1228 | /* device pulled? Shortcut the action. */ | |
1229 | if (devgone == dev) { | |
1230 | dev->status = USB_ST_CRC_ERR; | |
1231 | return 0; | |
1232 | } | |
7770ce47 | 1233 | |
c157d8e2 SR |
1234 | #ifdef DEBUG |
1235 | urb_priv.actual_length = 0; | |
7770ce47 | 1236 | pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); |
c157d8e2 SR |
1237 | #endif |
1238 | if (!maxsize) { | |
1239 | err("submit_common_message: pipesize for pipe %lx is zero", | |
7770ce47 | 1240 | pipe); |
c157d8e2 SR |
1241 | return -1; |
1242 | } | |
1243 | ||
7770ce47 | 1244 | if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { |
c157d8e2 SR |
1245 | err("sohci_submit_job failed"); |
1246 | return -1; | |
1247 | } | |
1248 | ||
1249 | /* allow more time for a BULK device to react - some are slow */ | |
7770ce47 SR |
1250 | #define BULK_TO 5000 /* timeout in milliseconds */ |
1251 | if (usb_pipetype (pipe) == PIPE_BULK) | |
c157d8e2 SR |
1252 | timeout = BULK_TO; |
1253 | else | |
1254 | timeout = 100; | |
1255 | ||
1256 | /* wait for it to complete */ | |
1257 | for (;;) { | |
1258 | /* check whether the controller is done */ | |
1259 | stat = hc_interrupt(); | |
1260 | if (stat < 0) { | |
1261 | stat = USB_ST_CRC_ERR; | |
1262 | break; | |
1263 | } | |
7770ce47 SR |
1264 | |
1265 | /* NOTE: since we are not interrupt driven in U-Boot and always | |
1266 | * handle only one URB at a time, we cannot assume the | |
1267 | * transaction finished on the first successful return from | |
1268 | * hc_interrupt().. unless the flag for current URB is set, | |
1269 | * meaning that all TD's to/from device got actually | |
1270 | * transferred and processed. If the current URB is not | |
1271 | * finished we need to re-iterate this loop so as | |
1272 | * hc_interrupt() gets called again as there needs to be some | |
1273 | * more TD's to process still */ | |
1274 | if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { | |
c157d8e2 SR |
1275 | /* 0xff is returned for an SF-interrupt */ |
1276 | break; | |
1277 | } | |
7770ce47 | 1278 | |
c157d8e2 SR |
1279 | if (--timeout) { |
1280 | wait_ms(1); | |
7770ce47 SR |
1281 | if (!urb_finished) |
1282 | dbg("\%"); | |
1283 | ||
c157d8e2 SR |
1284 | } else { |
1285 | err("CTL:TIMEOUT "); | |
7770ce47 | 1286 | dbg("submit_common_msg: TO status %x\n", stat); |
c157d8e2 | 1287 | stat = USB_ST_CRC_ERR; |
7770ce47 | 1288 | urb_finished = 1; |
c157d8e2 SR |
1289 | break; |
1290 | } | |
1291 | } | |
7770ce47 | 1292 | #if 0 |
c157d8e2 SR |
1293 | /* we got an Root Hub Status Change interrupt */ |
1294 | if (got_rhsc) { | |
1295 | #ifdef DEBUG | |
7770ce47 | 1296 | ohci_dump_roothub (&gohci, 1); |
c157d8e2 SR |
1297 | #endif |
1298 | got_rhsc = 0; | |
1299 | /* abuse timeout */ | |
1300 | timeout = rh_check_port_status(&gohci); | |
1301 | if (timeout >= 0) { | |
7770ce47 | 1302 | #if 0 /* this does nothing useful, but leave it here in case that changes */ |
c157d8e2 SR |
1303 | /* the called routine adds 1 to the passed value */ |
1304 | usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); | |
1305 | #endif | |
1306 | /* | |
1307 | * XXX | |
1308 | * This is potentially dangerous because it assumes | |
1309 | * that only one device is ever plugged in! | |
1310 | */ | |
1311 | devgone = dev; | |
1312 | } | |
1313 | } | |
7770ce47 | 1314 | #endif |
c157d8e2 SR |
1315 | |
1316 | dev->status = stat; | |
1317 | dev->act_len = transfer_len; | |
1318 | ||
1319 | #ifdef DEBUG | |
7770ce47 | 1320 | pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); |
c157d8e2 SR |
1321 | #endif |
1322 | ||
1323 | /* free TDs in urb_priv */ | |
7770ce47 | 1324 | urb_free_priv (&urb_priv); |
c157d8e2 SR |
1325 | return 0; |
1326 | } | |
1327 | ||
1328 | /* submit routines called from usb.c */ | |
1329 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1330 | int transfer_len) |
c157d8e2 SR |
1331 | { |
1332 | info("submit_bulk_msg"); | |
1333 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); | |
1334 | } | |
1335 | ||
1336 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1337 | int transfer_len, struct devrequest *setup) |
c157d8e2 SR |
1338 | { |
1339 | int maxsize = usb_maxpacket(dev, pipe); | |
1340 | ||
1341 | info("submit_control_msg"); | |
1342 | #ifdef DEBUG | |
1343 | urb_priv.actual_length = 0; | |
7770ce47 | 1344 | pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); |
c157d8e2 SR |
1345 | #endif |
1346 | if (!maxsize) { | |
1347 | err("submit_control_message: pipesize for pipe %lx is zero", | |
7770ce47 | 1348 | pipe); |
c157d8e2 SR |
1349 | return -1; |
1350 | } | |
1351 | if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { | |
1352 | gohci.rh.dev = dev; | |
1353 | /* root hub - redirect */ | |
1354 | return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, | |
7770ce47 | 1355 | setup); |
c157d8e2 SR |
1356 | } |
1357 | ||
1358 | return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); | |
1359 | } | |
1360 | ||
1361 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1362 | int transfer_len, int interval) |
c157d8e2 SR |
1363 | { |
1364 | info("submit_int_msg"); | |
1365 | return -1; | |
1366 | } | |
1367 | ||
1368 | /*-------------------------------------------------------------------------* | |
1369 | * HC functions | |
1370 | *-------------------------------------------------------------------------*/ | |
1371 | ||
1372 | /* reset the HC and BUS */ | |
1373 | ||
7770ce47 | 1374 | static int hc_reset (ohci_t *ohci) |
c157d8e2 SR |
1375 | { |
1376 | int timeout = 30; | |
7770ce47 | 1377 | int smm_timeout = 50; /* 0,5 sec */ |
c157d8e2 | 1378 | |
7770ce47 SR |
1379 | if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ |
1380 | writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ | |
c157d8e2 | 1381 | info("USB HC TakeOver from SMM"); |
7770ce47 SR |
1382 | while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { |
1383 | wait_ms (10); | |
c157d8e2 SR |
1384 | if (--smm_timeout == 0) { |
1385 | err("USB HC TakeOver failed!"); | |
1386 | return -1; | |
1387 | } | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | /* Disable HC interrupts */ | |
7770ce47 | 1392 | writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); |
c157d8e2 SR |
1393 | |
1394 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", | |
7770ce47 SR |
1395 | ohci->slot_name, |
1396 | readl (&ohci->regs->control)); | |
c157d8e2 SR |
1397 | |
1398 | /* Reset USB (needed by some controllers) */ | |
1399 | ohci->hc_control = 0; | |
7770ce47 | 1400 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
1401 | |
1402 | /* HC Reset requires max 10 us delay */ | |
7770ce47 SR |
1403 | writel (OHCI_HCR, &ohci->regs->cmdstatus); |
1404 | while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
c157d8e2 SR |
1405 | if (--timeout == 0) { |
1406 | err("USB HC reset timed out!"); | |
1407 | return -1; | |
1408 | } | |
7770ce47 | 1409 | udelay (1); |
c157d8e2 SR |
1410 | } |
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | /*-------------------------------------------------------------------------*/ | |
1415 | ||
1416 | /* Start an OHCI controller, set the BUS operational | |
1417 | * enable interrupts | |
1418 | * connect the virtual root hub */ | |
1419 | ||
7770ce47 | 1420 | static int hc_start (ohci_t * ohci) |
c157d8e2 SR |
1421 | { |
1422 | __u32 mask; | |
1423 | unsigned int fminterval; | |
1424 | ||
1425 | ohci->disabled = 1; | |
1426 | ||
1427 | /* Tell the controller where the control and bulk lists are | |
1428 | * The lists are empty now. */ | |
1429 | ||
7770ce47 SR |
1430 | writel (0, &ohci->regs->ed_controlhead); |
1431 | writel (0, &ohci->regs->ed_bulkhead); | |
c157d8e2 | 1432 | |
7770ce47 | 1433 | writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ |
c157d8e2 SR |
1434 | |
1435 | fminterval = 0x2edf; | |
7770ce47 | 1436 | writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); |
c157d8e2 | 1437 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
7770ce47 SR |
1438 | writel (fminterval, &ohci->regs->fminterval); |
1439 | writel (0x628, &ohci->regs->lsthresh); | |
c157d8e2 SR |
1440 | |
1441 | /* start controller operations */ | |
1442 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1443 | ohci->disabled = 0; | |
7770ce47 | 1444 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
1445 | |
1446 | /* disable all interrupts */ | |
1447 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
7770ce47 SR |
1448 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | |
1449 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
1450 | writel (mask, &ohci->regs->intrdisable); | |
c157d8e2 SR |
1451 | /* clear all interrupts */ |
1452 | mask &= ~OHCI_INTR_MIE; | |
7770ce47 | 1453 | writel (mask, &ohci->regs->intrstatus); |
c157d8e2 SR |
1454 | /* Choose the interrupts we care about now - but w/o MIE */ |
1455 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
7770ce47 | 1456 | writel (mask, &ohci->regs->intrenable); |
c157d8e2 SR |
1457 | |
1458 | #ifdef OHCI_USE_NPS | |
1459 | /* required for AMD-756 and some Mac platforms */ | |
7770ce47 SR |
1460 | writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, |
1461 | &ohci->regs->roothub.a); | |
1462 | writel (RH_HS_LPSC, &ohci->regs->roothub.status); | |
1463 | #endif /* OHCI_USE_NPS */ | |
c157d8e2 SR |
1464 | |
1465 | #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) | |
1466 | /* POTPGT delay is bits 24-31, in 2 ms units. */ | |
7770ce47 | 1467 | mdelay ((roothub_a (ohci) >> 23) & 0x1fe); |
c157d8e2 SR |
1468 | |
1469 | /* connect the virtual root hub */ | |
1470 | ohci->rh.devnum = 0; | |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | /*-------------------------------------------------------------------------*/ | |
1476 | ||
1477 | /* an interrupt happens */ | |
1478 | ||
7770ce47 SR |
1479 | static int |
1480 | hc_interrupt (void) | |
c157d8e2 SR |
1481 | { |
1482 | ohci_t *ohci = &gohci; | |
1483 | struct ohci_regs *regs = ohci->regs; | |
1484 | int ints; | |
1485 | int stat = -1; | |
1486 | ||
7770ce47 SR |
1487 | if ((ohci->hcca->done_head != 0) && |
1488 | !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { | |
1489 | ||
1490 | ints = OHCI_INTR_WDH; | |
1491 | ||
1492 | } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { | |
1493 | ohci->disabled++; | |
1494 | err ("%s device removed!", ohci->slot_name); | |
1495 | return -1; | |
1496 | ||
1497 | } else if ((ints &= readl (®s->intrenable)) == 0) { | |
1498 | dbg("hc_interrupt: returning..\n"); | |
1499 | return 0xff; | |
c157d8e2 SR |
1500 | } |
1501 | ||
1502 | /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ | |
1503 | ||
1504 | if (ints & OHCI_INTR_RHSC) { | |
1505 | got_rhsc = 1; | |
7770ce47 | 1506 | stat = 0xff; |
c157d8e2 SR |
1507 | } |
1508 | ||
1509 | if (ints & OHCI_INTR_UE) { | |
1510 | ohci->disabled++; | |
7770ce47 SR |
1511 | err ("OHCI Unrecoverable Error, controller usb-%s disabled", |
1512 | ohci->slot_name); | |
c157d8e2 SR |
1513 | /* e.g. due to PCI Master/Target Abort */ |
1514 | ||
1515 | #ifdef DEBUG | |
7770ce47 | 1516 | ohci_dump (ohci, 1); |
c157d8e2 SR |
1517 | #endif |
1518 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1519 | /* Make some non-interrupt context restart the controller. */ | |
1520 | /* Count and limit the retries though; either hardware or */ | |
1521 | /* software errors can go forever... */ | |
7770ce47 | 1522 | hc_reset (ohci); |
c157d8e2 SR |
1523 | return -1; |
1524 | } | |
1525 | ||
1526 | if (ints & OHCI_INTR_WDH) { | |
7770ce47 SR |
1527 | writel (OHCI_INTR_WDH, ®s->intrdisable); |
1528 | stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); | |
1529 | writel (OHCI_INTR_WDH, ®s->intrenable); | |
c157d8e2 SR |
1530 | } |
1531 | ||
1532 | if (ints & OHCI_INTR_SO) { | |
1533 | dbg("USB Schedule overrun\n"); | |
7770ce47 | 1534 | writel (OHCI_INTR_SO, ®s->intrenable); |
c157d8e2 SR |
1535 | stat = -1; |
1536 | } | |
1537 | ||
1538 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1539 | if (ints & OHCI_INTR_SF) { | |
7770ce47 SR |
1540 | unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; |
1541 | wait_ms(1); | |
1542 | writel (OHCI_INTR_SF, ®s->intrdisable); | |
c157d8e2 | 1543 | if (ohci->ed_rm_list[frame] != NULL) |
7770ce47 | 1544 | writel (OHCI_INTR_SF, ®s->intrenable); |
c157d8e2 SR |
1545 | stat = 0xff; |
1546 | } | |
1547 | ||
7770ce47 | 1548 | writel (ints, ®s->intrstatus); |
c157d8e2 SR |
1549 | return stat; |
1550 | } | |
1551 | ||
1552 | /*-------------------------------------------------------------------------*/ | |
1553 | ||
1554 | /*-------------------------------------------------------------------------*/ | |
1555 | ||
1556 | /* De-allocate all resources.. */ | |
1557 | ||
7770ce47 | 1558 | static void hc_release_ohci (ohci_t *ohci) |
c157d8e2 | 1559 | { |
7770ce47 | 1560 | dbg ("USB HC release ohci usb-%s", ohci->slot_name); |
c157d8e2 SR |
1561 | |
1562 | if (!ohci->disabled) | |
7770ce47 | 1563 | hc_reset (ohci); |
c157d8e2 SR |
1564 | } |
1565 | ||
1566 | /*-------------------------------------------------------------------------*/ | |
1567 | ||
1568 | /* | |
1569 | * low level initalisation routine, called from usb.c | |
1570 | */ | |
1571 | static char ohci_inited = 0; | |
1572 | ||
1573 | int usb_lowlevel_init(void) | |
1574 | { | |
7770ce47 SR |
1575 | memset (&gohci, 0, sizeof (ohci_t)); |
1576 | memset (&urb_priv, 0, sizeof (urb_priv_t)); | |
c157d8e2 SR |
1577 | |
1578 | /* align the storage */ | |
7770ce47 | 1579 | if ((__u32)&ghcca[0] & 0xff) { |
c157d8e2 SR |
1580 | err("HCCA not aligned!!"); |
1581 | return -1; | |
1582 | } | |
1583 | phcca = &ghcca[0]; | |
1584 | info("aligned ghcca %p", phcca); | |
1585 | memset(&ohci_dev, 0, sizeof(struct ohci_device)); | |
7770ce47 | 1586 | if ((__u32)&ohci_dev.ed[0] & 0x7) { |
c157d8e2 SR |
1587 | err("EDs not aligned!!"); |
1588 | return -1; | |
1589 | } | |
1590 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); | |
7770ce47 | 1591 | if ((__u32)gtd & 0x7) { |
c157d8e2 SR |
1592 | err("TDs not aligned!!"); |
1593 | return -1; | |
1594 | } | |
1595 | ptd = gtd; | |
1596 | gohci.hcca = phcca; | |
7770ce47 | 1597 | memset (phcca, 0, sizeof (struct ohci_hcca)); |
c157d8e2 SR |
1598 | |
1599 | gohci.disabled = 1; | |
1600 | gohci.sleeping = 0; | |
1601 | gohci.irq = -1; | |
887e2ec9 SR |
1602 | #if defined(CONFIG_440EP) |
1603 | gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); | |
e01bd218 | 1604 | #elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) |
887e2ec9 SR |
1605 | gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); |
1606 | #endif | |
c157d8e2 SR |
1607 | |
1608 | gohci.flags = 0; | |
1609 | gohci.slot_name = "ppc440"; | |
1610 | ||
7770ce47 SR |
1611 | if (hc_reset (&gohci) < 0) { |
1612 | hc_release_ohci (&gohci); | |
c157d8e2 SR |
1613 | return -1; |
1614 | } | |
1615 | ||
7770ce47 SR |
1616 | if (hc_start (&gohci) < 0) { |
1617 | err ("can't start usb-%s", gohci.slot_name); | |
1618 | hc_release_ohci (&gohci); | |
c157d8e2 SR |
1619 | return -1; |
1620 | } | |
7770ce47 | 1621 | |
c157d8e2 | 1622 | #ifdef DEBUG |
7770ce47 | 1623 | ohci_dump (&gohci, 1); |
c157d8e2 SR |
1624 | #endif |
1625 | ohci_inited = 1; | |
7770ce47 | 1626 | urb_finished = 1; |
c157d8e2 | 1627 | |
e01bd218 | 1628 | #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) |
c157d8e2 SR |
1629 | /* init the device driver */ |
1630 | usb_dev_init(); | |
e01bd218 | 1631 | #endif |
c157d8e2 SR |
1632 | |
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | int usb_lowlevel_stop(void) | |
1637 | { | |
1638 | /* this gets called really early - before the controller has */ | |
1639 | /* even been initialized! */ | |
1640 | if (!ohci_inited) | |
1641 | return 0; | |
1642 | /* TODO release any interrupts, etc. */ | |
1643 | /* call hc_release_ohci() here ? */ | |
7770ce47 | 1644 | hc_reset (&gohci); |
c157d8e2 SR |
1645 | return 0; |
1646 | } | |
1647 | ||
7770ce47 | 1648 | #endif /* CONFIG_USB_OHCI */ |