[people/ms/u-boot.git] / cpu / pxa / cpu.c

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Alex Zuepke <azu@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 */

#include <common.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>

int cpu_init (void)
{
	/*
	 * setup up stack if necessary
	 */
/*

  FIXME: the stack is _below_ the uboot code!!

#ifdef CONFIG_USE_IRQ
	IRQ_STACK_START = _armboot_end +
			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
	_armboot_real_end = FIQ_STACK_START + 4;
#else
	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
#endif
*/
	return (0);
}

int cleanup_before_linux (void)
{
	/*
	 * this function is called just before we call linux
	 * it prepares the processor for linux
	 *
	 * just disable everything that can disturb booting linux
	 */

	unsigned long i;

	disable_interrupts ();

	/* turn off I-cache */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	i &= ~0x1000;
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

	/* flush I-cache */
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));

	return (0);
}

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	extern void reset_cpu (ulong addr);

	printf ("resetting ...\n");

	udelay (50000);				/* wait 50 ms */
	disable_interrupts ();
	reset_cpu (0);

	/*NOTREACHED*/
	return (0);
}

/* taken from blob */
void icache_enable (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* set i-cache */
	i |= 0x1000;

	/* write back to control register */
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}

void icache_disable (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* clear i-cache */
	i &= ~0x1000;

	/* write back to control register */
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

	/* flush i-cache */
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}

int icache_status (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* return bit */
	return (i & 0x1000);
}

/* we will never enable dcache, because we have to setup MMU first */
void dcache_enable (void)
{
	return;
}

void dcache_disable (void)
{
	return;
}

int dcache_status (void)
{
	return 0;					/* always off */
}

void set_GPIO_mode(int gpio_mode)
{
	int gpio = gpio_mode & GPIO_MD_MASK_NR;
	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
	int gafr;

	if (gpio_mode & GPIO_MD_MASK_DIR)
	{
		GPDR(gpio) |= GPIO_bit(gpio);
	}
	else
	{
		GPDR(gpio) &= ~GPIO_bit(gpio);
	}
	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
}
Commit	Line	Data
11a72d9f WD	1	/*
	2	* (C) Copyright 2002
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	*
	6	* (C) Copyright 2002
	7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	8	* Alex Zuepke <azu@sysgo.de>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/*
	30	* CPU specific code
	31	*/
	32
	33	#include <common.h>
	34	#include <command.h>
71f95118	35	#include <asm/arch/pxa-regs.h>
11a72d9f WD	36
	37	int cpu_init (void)
	38	{
	39	/*
	40	* setup up stack if necessary
	41	*/
	42	/*
	43
	44	FIXME: the stack is _below_ the uboot code!!
	45
	46	#ifdef CONFIG_USE_IRQ
	47	IRQ_STACK_START = _armboot_end +
	48	CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
	49	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
	50	_armboot_real_end = FIQ_STACK_START + 4;
	51	#else
	52	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
	53	#endif
	54	*/
	55	return (0);
	56	}
	57
	58	int cleanup_before_linux (void)
	59	{
	60	/*
	61	* this function is called just before we call linux
	62	* it prepares the processor for linux
	63	*
	64	* just disable everything that can disturb booting linux
	65	*/
	66
	67	unsigned long i;
	68
	69	disable_interrupts ();
	70
	71	/* turn off I-cache */
	72	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	73	i &= ~0x1000;
	74	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	75
	76	/* flush I-cache */
	77	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
	78
	79	return (0);
	80	}
	81
	82	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	83	{
	84	extern void reset_cpu (ulong addr);
	85
5f535fe1	86	printf ("resetting ...\n");
11a72d9f WD	87
	88	udelay (50000); /* wait 50 ms */
	89	disable_interrupts ();
	90	reset_cpu (0);
	91
	92	/NOTREACHED/
	93	return (0);
	94	}
	95
	96	/* taken from blob */
	97	void icache_enable (void)
	98	{
	99	register u32 i;
	100
	101	/* read control register */
	102	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	103
	104	/* set i-cache */
	105	i \|= 0x1000;
	106
	107	/* write back to control register */
	108	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	109	}
	110
	111	void icache_disable (void)
	112	{
	113	register u32 i;
	114
	115	/* read control register */
	116	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	117
	118	/* clear i-cache */
	119	i &= ~0x1000;
	120
	121	/* write back to control register */
	122	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	123
	124	/* flush i-cache */
	125	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
	126	}
	127
	128	int icache_status (void)
	129	{
	130	register u32 i;
	131
	132	/* read control register */
	133	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	134
	135	/* return bit */
	136	return (i & 0x1000);
	137	}
	138
	139	/* we will never enable dcache, because we have to setup MMU first */
	140	void dcache_enable (void)
	141	{
	142	return;
	143	}
	144
	145	void dcache_disable (void)
	146	{
	147	return;
	148	}
	149
	150	int dcache_status (void)
151	{
152	return 0; /* always off */
153	}
71f95118 WD	154
	155	void set_GPIO_mode(int gpio_mode)
	156	{
	157	int gpio = gpio_mode & GPIO_MD_MASK_NR;
	158	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
	159	int gafr;
	160
	161	if (gpio_mode & GPIO_MD_MASK_DIR)
	162	{
	163	GPDR(gpio) \|= GPIO_bit(gpio);
	164	}
	165	else
	166	{
	167	GPDR(gpio) &= ~GPIO_bit(gpio);
	168	}
	169	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
	170	GAFR(gpio) = gafr \| (fn << (((gpio) & 0xf)*2));
	171	}