[people/ms/u-boot.git] / cpu / pxa / pxafb.c

/*
 * PXA LCD Controller
 *
 * (C) Copyright 2001-2002
 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************/
/* ** HEADER FILES							*/
/************************************************************************/

#include <config.h>
#include <common.h>
#include <version.h>
#include <stdarg.h>
#include <linux/types.h>
#include <devices.h>
#include <lcd.h>
#include <asm/arch/pxa-regs.h>

/* #define DEBUG */

#ifdef CONFIG_LCD

/*----------------------------------------------------------------------*/
/*
 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
 * your display.
 */

#ifdef CONFIG_PXA_VGA
/* LCD outputs connected to a video DAC  */
# define LCD_BPP	LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x003008f8
# define REG_LCCR3	0x0300FF01

/* 640x480x16 @ 61 Hz */
vidinfo_t panel_info = {
	vl_col:		640,
	vl_row:		480,
	vl_width:	640,
	vl_height:	480,
	vl_clkp:	CONFIG_SYS_HIGH,
	vl_oep:		CONFIG_SYS_HIGH,
	vl_hsp:		CONFIG_SYS_HIGH,
	vl_vsp:		CONFIG_SYS_HIGH,
	vl_dp:		CONFIG_SYS_HIGH,
	vl_bpix:	LCD_BPP,
	vl_lbw:		0,
	vl_splt:	0,
	vl_clor:	0,
	vl_tft:		1,
	vl_hpw:		40,
	vl_blw:		56,
	vl_elw:		56,
	vl_vpw:		20,
	vl_bfw:		8,
	vl_efw:		8,
};
#endif /* CONFIG_PXA_VIDEO */

/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_LM8V31

# define LCD_BPP	LCD_COLOR8
# define LCD_INVERT_COLORS	/* Needed for colors to be correct, but why?	*/

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x0030087C
# define REG_LCCR3	0x0340FF08

vidinfo_t panel_info = {
	vl_col:		640,
	vl_row:		480,
	vl_width:	157,
	vl_height:	118,
	vl_clkp:	CONFIG_SYS_HIGH,
	vl_oep:		CONFIG_SYS_HIGH,
	vl_hsp:		CONFIG_SYS_HIGH,
	vl_vsp:		CONFIG_SYS_HIGH,
	vl_dp:		CONFIG_SYS_HIGH,
	vl_bpix:	LCD_BPP,
	vl_lbw:		0,
	vl_splt:	1,
	vl_clor:	1,
	vl_tft:		0,
	vl_hpw:		1,
	vl_blw:		3,
	vl_elw:		3,
	vl_vpw:		1,
	vl_bfw:		0,
	vl_efw:		0,
};
#endif /* CONFIG_SHARP_LM8V31 */

/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
/* Hitachi SX14Q004-ZZA color STN LCD */
#define LCD_BPP		LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
#define REG_LCCR0	0x00301079
#define REG_LCCR3	0x0340FF20

vidinfo_t panel_info = {
	vl_col:		320,
	vl_row:		240,
	vl_width:	167,
	vl_height:	109,
	vl_clkp:	CONFIG_SYS_HIGH,
	vl_oep:		CONFIG_SYS_HIGH,
	vl_hsp:		CONFIG_SYS_HIGH,
	vl_vsp:		CONFIG_SYS_HIGH,
	vl_dp:		CONFIG_SYS_HIGH,
	vl_bpix:	LCD_BPP,
	vl_lbw:		1,
	vl_splt:	0,
	vl_clor:	1,
	vl_tft:		0,
	vl_hpw:		1,
	vl_blw:		1,
	vl_elw:		1,
	vl_vpw:		7,
	vl_bfw:		0,
	vl_efw:		0,
};
#endif /* CONFIG_HITACHI_SX14 */

/*----------------------------------------------------------------------*/

#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
#endif
#if LCD_BPP == LCD_MONOCHROME
void lcd_initcolregs (void);
#endif

#ifdef NOT_USED_SO_FAR
void lcd_disable (void);
void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
#endif /* NOT_USED_SO_FAR */

void lcd_ctrl_init	(void *lcdbase);
void lcd_enable	(void);

int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;

void *lcd_base;			/* Start of framebuffer memory	*/
void *lcd_console_address;		/* Start of console buffer	*/

short console_col;
short console_row;

static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
static void pxafb_setup_gpio (vidinfo_t *vid);
static void pxafb_enable_controller (vidinfo_t *vid);
static int pxafb_init (vidinfo_t *vid);
/************************************************************************/

/************************************************************************/
/* ---------------  PXA chipset specific functions  ------------------- */
/************************************************************************/

void lcd_ctrl_init (void *lcdbase)
{
	pxafb_init_mem(lcdbase, &panel_info);
	pxafb_init(&panel_info);
	pxafb_setup_gpio(&panel_info);
	pxafb_enable_controller(&panel_info);
}

/*----------------------------------------------------------------------*/
#ifdef NOT_USED_SO_FAR
void
lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
{
}
#endif /* NOT_USED_SO_FAR */

/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
	struct pxafb_info *fbi = &panel_info.pxa;
	unsigned short *palette = (unsigned short *)fbi->palette;
	u_int val;

	if (regno < fbi->palette_size) {
		val = ((red << 8) & 0xf800);
		val |= ((green << 4) & 0x07e0);
		val |= (blue & 0x001f);

#ifdef LCD_INVERT_COLORS
		palette[regno] = ~val;
#else
		palette[regno] = val;
#endif
	}

	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
		regno, &palette[regno],
		red, green, blue,
		palette[regno]);
}
#endif /* LCD_COLOR8 */

/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_MONOCHROME
void lcd_initcolregs (void)
{
	struct pxafb_info *fbi = &panel_info.pxa;
	cmap = (ushort *)fbi->palette;
	ushort regno;

	for (regno = 0; regno < 16; regno++) {
		cmap[regno * 2] = 0;
		cmap[(regno * 2) + 1] = regno & 0x0f;
	}
}
#endif /* LCD_MONOCHROME */

/*----------------------------------------------------------------------*/
void lcd_enable (void)
{
}

/*----------------------------------------------------------------------*/
#ifdef	NOT_USED_SO_FAR
static void lcd_disable (void)
{
}
#endif /* NOT_USED_SO_FAR */

/*----------------------------------------------------------------------*/

/************************************************************************/
/* ** PXA255 specific routines						*/
/************************************************************************/

/*
 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 * descriptors and palette areas.
 */
ulong calc_fbsize (void)
{
	ulong size;
	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;

	size = line_length * panel_info.vl_row;
	size += PAGE_SIZE;

	return size;
}

static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
{
	u_long palette_mem_size;
	struct pxafb_info *fbi = &vid->pxa;
	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;

	fbi->screen = (u_long)lcdbase;

	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
	palette_mem_size = fbi->palette_size * sizeof(u16);

	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
	/* locate palette and descs at end of page following fb */
	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;

	return 0;
}

static void pxafb_setup_gpio (vidinfo_t *vid)
{
	u_long lccr0;

	/*
	 * setup is based on type of panel supported
	 */

	lccr0 = vid->pxa.reg_lccr0;

	/* 4 bit interface */
	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
	{
		debug("Setting GPIO for 4 bit data\n");
		/* bits 58-61 */
		GPDR1 |= (0xf << 26);
		GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);

		/* bits 74-77 */
		GPDR2 |= (0xf << 10);
		GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
	}

	/* 8 bit interface */
	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
		(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
	{
		debug("Setting GPIO for 8 bit data\n");
		/* bits 58-65 */
		GPDR1 |= (0x3f << 26);
		GPDR2 |= (0x3);

		GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
		GAFR2_L = (GAFR2_L & ~0xf) | (0xa);

		/* bits 74-77 */
		GPDR2 |= (0xf << 10);
		GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
	}

	/* 16 bit interface */
	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
	{
		debug("Setting GPIO for 16 bit data\n");
		/* bits 58-77 */
		GPDR1 |= (0x3f << 26);
		GPDR2 |= 0x00003fff;

		GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
		GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
	}
	else
	{
		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
	}
}

static void pxafb_enable_controller (vidinfo_t *vid)
{
	debug("Enabling LCD controller\n");

	/* Sequence from 11.7.10 */
	LCCR3  = vid->pxa.reg_lccr3;
	LCCR2  = vid->pxa.reg_lccr2;
	LCCR1  = vid->pxa.reg_lccr1;
	LCCR0  = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
	FDADR0 = vid->pxa.fdadr0;
	FDADR1 = vid->pxa.fdadr1;
	LCCR0 |= LCCR0_ENB;

	CKEN |= CKEN16_LCD;

	debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
	debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
	debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
	debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
	debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
	debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
}

static int pxafb_init (vidinfo_t *vid)
{
	struct pxafb_info *fbi = &vid->pxa;

	debug("Configuring PXA LCD\n");

	fbi->reg_lccr0 = REG_LCCR0;
	fbi->reg_lccr3 = REG_LCCR3;

	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
		vid->vl_col, vid->vl_hpw,
		vid->vl_blw, vid->vl_elw);
	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
		vid->vl_row, vid->vl_vpw,
		vid->vl_bfw, vid->vl_efw);

	fbi->reg_lccr1 =
		LCCR1_DisWdth(vid->vl_col) +
		LCCR1_HorSnchWdth(vid->vl_hpw) +
		LCCR1_BegLnDel(vid->vl_blw) +
		LCCR1_EndLnDel(vid->vl_elw);

	fbi->reg_lccr2 =
		LCCR2_DisHght(vid->vl_row) +
		LCCR2_VrtSnchWdth(vid->vl_vpw) +
		LCCR2_BegFrmDel(vid->vl_bfw) +
		LCCR2_EndFrmDel(vid->vl_efw);

	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
	fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
			| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);


	/* setup dma descriptors */
	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
	fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);

	#define BYTES_PER_PANEL	((fbi->reg_lccr0 & LCCR0_SDS) ? \
		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))

	/* populate descriptors */
	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
	fbi->dmadesc_fblow->fidr  = 0;
	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;

	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */

	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
	fbi->dmadesc_fbhigh->fidr = 0;
	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;

	fbi->dmadesc_palette->fsadr = fbi->palette;
	fbi->dmadesc_palette->fidr  = 0;
	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;

	if( NBITS(vid->vl_bpix) < 12)
	{
		/* assume any mode with <12 bpp is palette driven */
		fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
		/* flips back and forth between pal and fbhigh */
		fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
	}
	else
	{
		/* palette shouldn't be loaded in true-color mode */
		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
		fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
	}

	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);

	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);

	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);

	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);

	return 0;
}

/************************************************************************/
/************************************************************************/

#endif /* CONFIG_LCD */
Commit	Line	Data
71f95118	1	/*
8655b6f8 WD	2	* PXA LCD Controller
8655b6f8 WD	3	*
71f95118 WD	4	* (C) Copyright 2001-2002
	5	* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/************************************************************************/
	27	/* ** HEADER FILES */
	28	/************************************************************************/
	29
71f95118 WD	30	#include <config.h>
	31	#include <common.h>
	32	#include <version.h>
	33	#include <stdarg.h>
71f95118 WD	34	#include <linux/types.h>
71f95118 WD	35	#include <devices.h>
8655b6f8	36	#include <lcd.h>
71f95118 WD	37	#include <asm/arch/pxa-regs.h>
71f95118 WD	38
8655b6f8	39	/* #define DEBUG */
71f95118	40
8655b6f8	41	#ifdef CONFIG_LCD
71f95118 WD	42
71f95118 WD	43	/----------------------------------------------------------------------/
71f95118	44	/*
8655b6f8 WD	45	* Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
8655b6f8 WD	46	* your display.
71f95118 WD	47	*/
71f95118 WD	48
8655b6f8 WD	49	#ifdef CONFIG_PXA_VGA
	50	/* LCD outputs connected to a video DAC */
	51	# define LCD_BPP LCD_COLOR8
71f95118 WD	52
71f95118 WD	53	/* you have to set lccr0 and lccr3 (including pcd) */
8655b6f8 WD	54	# define REG_LCCR0 0x003008f8
8655b6f8 WD	55	# define REG_LCCR3 0x0300FF01
71f95118 WD	56
71f95118 WD	57	/* 640x480x16 @ 61 Hz */
8655b6f8 WD	58	vidinfo_t panel_info = {
	59	vl_col: 640,
	60	vl_row: 480,
	61	vl_width: 640,
	62	vl_height: 480,
6d0f6bcf JCPV	63	vl_clkp: CONFIG_SYS_HIGH,
	64	vl_oep: CONFIG_SYS_HIGH,
	65	vl_hsp: CONFIG_SYS_HIGH,
	66	vl_vsp: CONFIG_SYS_HIGH,
	67	vl_dp: CONFIG_SYS_HIGH,
8655b6f8 WD	68	vl_bpix: LCD_BPP,
	69	vl_lbw: 0,
	70	vl_splt: 0,
	71	vl_clor: 0,
	72	vl_tft: 1,
	73	vl_hpw: 40,
	74	vl_blw: 56,
	75	vl_elw: 56,
	76	vl_vpw: 20,
	77	vl_bfw: 8,
	78	vl_efw: 8,
71f95118 WD	79	};
	80	#endif /* CONFIG_PXA_VIDEO */
	81
8655b6f8	82	/----------------------------------------------------------------------/
71f95118 WD	83	#ifdef CONFIG_SHARP_LM8V31
71f95118 WD	84
8655b6f8 WD	85	# define LCD_BPP LCD_COLOR8
8655b6f8 WD	86	# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
71f95118 WD	87
71f95118 WD	88	/* you have to set lccr0 and lccr3 (including pcd) */
8655b6f8 WD	89	# define REG_LCCR0 0x0030087C
	90	# define REG_LCCR3 0x0340FF08
	91
	92	vidinfo_t panel_info = {
	93	vl_col: 640,
	94	vl_row: 480,
	95	vl_width: 157,
	96	vl_height: 118,
6d0f6bcf JCPV	97	vl_clkp: CONFIG_SYS_HIGH,
	98	vl_oep: CONFIG_SYS_HIGH,
	99	vl_hsp: CONFIG_SYS_HIGH,
	100	vl_vsp: CONFIG_SYS_HIGH,
	101	vl_dp: CONFIG_SYS_HIGH,
8655b6f8 WD	102	vl_bpix: LCD_BPP,
	103	vl_lbw: 0,
	104	vl_splt: 1,
	105	vl_clor: 1,
	106	vl_tft: 0,
	107	vl_hpw: 1,
	108	vl_blw: 3,
	109	vl_elw: 3,
	110	vl_vpw: 1,
	111	vl_bfw: 0,
	112	vl_efw: 0,
71f95118 WD	113	};
	114	#endif /* CONFIG_SHARP_LM8V31 */
	115
	116	/----------------------------------------------------------------------/
8655b6f8 WD	117	#ifdef CONFIG_HITACHI_SX14
	118	/* Hitachi SX14Q004-ZZA color STN LCD */
	119	#define LCD_BPP LCD_COLOR8
71f95118	120
8655b6f8 WD	121	/* you have to set lccr0 and lccr3 (including pcd) */
	122	#define REG_LCCR0 0x00301079
	123	#define REG_LCCR3 0x0340FF20
	124
	125	vidinfo_t panel_info = {
	126	vl_col: 320,
	127	vl_row: 240,
	128	vl_width: 167,
	129	vl_height: 109,
6d0f6bcf JCPV	130	vl_clkp: CONFIG_SYS_HIGH,
	131	vl_oep: CONFIG_SYS_HIGH,
	132	vl_hsp: CONFIG_SYS_HIGH,
	133	vl_vsp: CONFIG_SYS_HIGH,
	134	vl_dp: CONFIG_SYS_HIGH,
8655b6f8 WD	135	vl_bpix: LCD_BPP,
	136	vl_lbw: 1,
	137	vl_splt: 0,
	138	vl_clor: 1,
	139	vl_tft: 0,
	140	vl_hpw: 1,
	141	vl_blw: 1,
	142	vl_elw: 1,
	143	vl_vpw: 7,
	144	vl_bfw: 0,
	145	vl_efw: 0,
71f95118	146	};
8655b6f8	147	#endif /* CONFIG_HITACHI_SX14 */
71f95118 WD	148
	149	/----------------------------------------------------------------------/
	150
8655b6f8 WD	151	#if LCD_BPP == LCD_COLOR8
8655b6f8 WD	152	void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
71f95118	153	#endif
8655b6f8 WD	154	#if LCD_BPP == LCD_MONOCHROME
8655b6f8 WD	155	void lcd_initcolregs (void);
71f95118 WD	156	#endif
71f95118 WD	157
8655b6f8 WD	158	#ifdef NOT_USED_SO_FAR
	159	void lcd_disable (void);
	160	void lcd_getcolreg (ushort regno, ushort red, ushort green, ushort *blue);
	161	#endif /* NOT_USED_SO_FAR */
71f95118	162
8655b6f8 WD	163	void lcd_ctrl_init (void *lcdbase);
8655b6f8 WD	164	void lcd_enable (void);
71f95118	165
8655b6f8 WD	166	int lcd_line_length;
	167	int lcd_color_fg;
	168	int lcd_color_bg;
71f95118	169
8655b6f8 WD	170	void lcd_base; / Start of framebuffer memory */
8655b6f8 WD	171	void lcd_console_address; / Start of console buffer */
71f95118	172
8655b6f8 WD	173	short console_col;
8655b6f8 WD	174	short console_row;
71f95118	175
8655b6f8 WD	176	static int pxafb_init_mem (void lcdbase, vidinfo_t vid);
	177	static void pxafb_setup_gpio (vidinfo_t *vid);
	178	static void pxafb_enable_controller (vidinfo_t *vid);
	179	static int pxafb_init (vidinfo_t *vid);
71f95118 WD	180	/************************************************************************/
71f95118 WD	181
71f95118	182	/************************************************************************/
8655b6f8	183	/* --------------- PXA chipset specific functions ------------------- */
71f95118 WD	184	/************************************************************************/
71f95118 WD	185
8655b6f8	186	void lcd_ctrl_init (void *lcdbase)
71f95118	187	{
8bde7f77	188	pxafb_init_mem(lcdbase, &panel_info);
71f95118 WD	189	pxafb_init(&panel_info);
	190	pxafb_setup_gpio(&panel_info);
	191	pxafb_enable_controller(&panel_info);
	192	}
	193
	194	/----------------------------------------------------------------------/
8655b6f8 WD	195	#ifdef NOT_USED_SO_FAR
8655b6f8 WD	196	void
71f95118 WD	197	lcd_getcolreg (ushort regno, ushort red, ushort green, ushort *blue)
	198	{
	199	}
8655b6f8	200	#endif /* NOT_USED_SO_FAR */
71f95118 WD	201
71f95118 WD	202	/----------------------------------------------------------------------/
71f95118	203	#if LCD_BPP == LCD_COLOR8
8655b6f8	204	void
71f95118 WD	205	lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
	206	{
	207	struct pxafb_info *fbi = &panel_info.pxa;
	208	unsigned short palette = (unsigned short )fbi->palette;
	209	u_int val;
8bde7f77	210
71f95118 WD	211	if (regno < fbi->palette_size) {
	212	val = ((red << 8) & 0xf800);
	213	val \|= ((green << 4) & 0x07e0);
	214	val \|= (blue & 0x001f);
	215
	216	#ifdef LCD_INVERT_COLORS
	217	palette[regno] = ~val;
	218	#else
8655b6f8	219	palette[regno] = val;
71f95118 WD	220	#endif
	221	}
	222
	223	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
	224	regno, &palette[regno],
	225	red, green, blue,
	226	palette[regno]);
	227	}
8655b6f8	228	#endif /* LCD_COLOR8 */
71f95118 WD	229
71f95118 WD	230	/----------------------------------------------------------------------/
71f95118	231	#if LCD_BPP == LCD_MONOCHROME
71f95118 WD	232	void lcd_initcolregs (void)
71f95118 WD	233	{
8655b6f8 WD	234	struct pxafb_info *fbi = &panel_info.pxa;
8655b6f8 WD	235	cmap = (ushort *)fbi->palette;
71f95118 WD	236	ushort regno;
	237
	238	for (regno = 0; regno < 16; regno++) {
8655b6f8 WD	239	cmap[regno * 2] = 0;
8655b6f8 WD	240	cmap[(regno * 2) + 1] = regno & 0x0f;
71f95118 WD	241	}
71f95118 WD	242	}
8655b6f8	243	#endif /* LCD_MONOCHROME */
71f95118 WD	244
71f95118 WD	245	/----------------------------------------------------------------------/
8655b6f8	246	void lcd_enable (void)
71f95118	247	{
71f95118	248	}
71f95118 WD	249
71f95118 WD	250	/----------------------------------------------------------------------/
71f95118 WD	251	#ifdef NOT_USED_SO_FAR
	252	static void lcd_disable (void)
	253	{
	254	}
8655b6f8	255	#endif /* NOT_USED_SO_FAR */
71f95118	256
8655b6f8	257	/----------------------------------------------------------------------/
71f95118 WD	258
71f95118 WD	259	/************************************************************************/
8655b6f8	260	/* ** PXA255 specific routines */
71f95118 WD	261	/************************************************************************/
71f95118 WD	262
8655b6f8 WD	263	/*
	264	* Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
	265	* descriptors and palette areas.
	266	*/
	267	ulong calc_fbsize (void)
71f95118	268	{
8655b6f8 WD	269	ulong size;
8655b6f8 WD	270	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
71f95118	271
8655b6f8 WD	272	size = line_length * panel_info.vl_row;
8655b6f8 WD	273	size += PAGE_SIZE;
71f95118	274
8655b6f8	275	return size;
71f95118 WD	276	}
71f95118 WD	277
8655b6f8	278	static int pxafb_init_mem (void lcdbase, vidinfo_t vid)
71f95118 WD	279	{
	280	u_long palette_mem_size;
	281	struct pxafb_info *fbi = &vid->pxa;
	282	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
	283
	284	fbi->screen = (u_long)lcdbase;
	285
	286	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
	287	palette_mem_size = fbi->palette_size * sizeof(u16);
8655b6f8	288
71f95118 WD	289	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
71f95118 WD	290	/* locate palette and descs at end of page following fb */
8655b6f8	291	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
71f95118 WD	292
	293	return 0;
	294	}
	295
8655b6f8	296	static void pxafb_setup_gpio (vidinfo_t *vid)
71f95118 WD	297	{
	298	u_long lccr0;
	299
	300	/*
	301	* setup is based on type of panel supported
	302	*/
	303
	304	lccr0 = vid->pxa.reg_lccr0;
	305
	306	/* 4 bit interface */
	307	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
	308	{
	309	debug("Setting GPIO for 4 bit data\n");
	310	/* bits 58-61 */
	311	GPDR1 \|= (0xf << 26);
	312	GAFR1_U = (GAFR1_U & ~(0xff << 20)) \| (0xaa << 20);
	313
	314	/* bits 74-77 */
	315	GPDR2 \|= (0xf << 10);
	316	GAFR2_L = (GAFR2_L & ~(0xff << 20)) \| (0xaa << 20);
	317	}
	318
	319	/* 8 bit interface */
	320	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) \|\| (lccr0 & LCCR0_DPD))) \|\|
8655b6f8	321	(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
71f95118 WD	322	{
	323	debug("Setting GPIO for 8 bit data\n");
	324	/* bits 58-65 */
	325	GPDR1 \|= (0x3f << 26);
	326	GPDR2 \|= (0x3);
	327
	328	GAFR1_U = (GAFR1_U & ~(0xfff << 20)) \| (0xaaa << 20);
	329	GAFR2_L = (GAFR2_L & ~0xf) \| (0xa);
	330
	331	/* bits 74-77 */
	332	GPDR2 \|= (0xf << 10);
	333	GAFR2_L = (GAFR2_L & ~(0xff << 20)) \| (0xaa << 20);
	334	}
	335
	336	/* 16 bit interface */
	337	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) \|\| (lccr0 & LCCR0_PAS)))
	338	{
	339	debug("Setting GPIO for 16 bit data\n");
	340	/* bits 58-77 */
	341	GPDR1 \|= (0x3f << 26);
	342	GPDR2 \|= 0x00003fff;
	343
	344	GAFR1_U = (GAFR1_U & ~(0xfff << 20)) \| (0xaaa << 20);
	345	GAFR2_L = (GAFR2_L & 0xf0000000) \| 0x0aaaaaaa;
	346	}
	347	else
	348	{
	349	printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
	350	}
	351	}
	352
8655b6f8	353	static void pxafb_enable_controller (vidinfo_t *vid)
71f95118 WD	354	{
	355	debug("Enabling LCD controller\n");
	356
	357	/* Sequence from 11.7.10 */
	358	LCCR3 = vid->pxa.reg_lccr3;
	359	LCCR2 = vid->pxa.reg_lccr2;
	360	LCCR1 = vid->pxa.reg_lccr1;
	361	LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
	362	FDADR0 = vid->pxa.fdadr0;
	363	FDADR1 = vid->pxa.fdadr1;
	364	LCCR0 \|= LCCR0_ENB;
	365
	366	CKEN \|= CKEN16_LCD;
	367
	368	debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
	369	debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
	370	debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
	371	debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
	372	debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
	373	debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
	374	}
	375
8655b6f8	376	static int pxafb_init (vidinfo_t *vid)
71f95118 WD	377	{
	378	struct pxafb_info *fbi = &vid->pxa;
	379
	380	debug("Configuring PXA LCD\n");
	381
	382	fbi->reg_lccr0 = REG_LCCR0;
	383	fbi->reg_lccr3 = REG_LCCR3;
	384
	385	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
	386	vid->vl_col, vid->vl_hpw,
	387	vid->vl_blw, vid->vl_elw);
	388	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
	389	vid->vl_row, vid->vl_vpw,
	390	vid->vl_bfw, vid->vl_efw);
	391
	392	fbi->reg_lccr1 =
	393	LCCR1_DisWdth(vid->vl_col) +
	394	LCCR1_HorSnchWdth(vid->vl_hpw) +
	395	LCCR1_BegLnDel(vid->vl_blw) +
	396	LCCR1_EndLnDel(vid->vl_elw);
8bde7f77	397
71f95118 WD	398	fbi->reg_lccr2 =
	399	LCCR2_DisHght(vid->vl_row) +
	400	LCCR2_VrtSnchWdth(vid->vl_vpw) +
	401	LCCR2_BegFrmDel(vid->vl_bfw) +
	402	LCCR2_EndFrmDel(vid->vl_efw);
	403
8bde7f77	404	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP \| LCCR3_VSP);
8655b6f8 WD	405	fbi->reg_lccr3 \|= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
8655b6f8 WD	406	\| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
8bde7f77	407
71f95118 WD	408
	409	/* setup dma descriptors */
	410	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor )((unsigned int)fbi->palette - 316);
	411	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor )((unsigned int)fbi->palette - 216);
	412	fbi->dmadesc_palette = (struct pxafb_dma_descriptor )((unsigned int)fbi->palette - 116);
	413
	414	#define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
8bde7f77 WD	415	(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
	416	(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
	417
71f95118 WD	418	/* populate descriptors */
	419	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
	420	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
	421	fbi->dmadesc_fblow->fidr = 0;
	422	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
	423
	424	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
8bde7f77	425
71f95118 WD	426	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
	427	fbi->dmadesc_fbhigh->fidr = 0;
	428	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
	429
	430	fbi->dmadesc_palette->fsadr = fbi->palette;
	431	fbi->dmadesc_palette->fidr = 0;
	432	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) \| LDCMD_PAL;
	433
	434	if( NBITS(vid->vl_bpix) < 12)
	435	{
	436	/* assume any mode with <12 bpp is palette driven */
	437	fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
	438	fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
	439	/* flips back and forth between pal and fbhigh */
8bde7f77	440	fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
71f95118 WD	441	}
	442	else
	443	{
	444	/* palette shouldn't be loaded in true-color mode */
	445	fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
	446	fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
	447	}
	448
	449	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
	450	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
	451	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
	452
	453	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
	454	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
	455	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
	456
	457	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
	458	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
	459	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
	460
	461	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
	462	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
	463	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
8bde7f77	464
71f95118 WD	465	return 0;
	466	}
	467
	468	/************************************************************************/
	469	/************************************************************************/
	470
	471	#endif /* CONFIG_LCD */