]>
Commit | Line | Data |
---|---|---|
0ae76531 DF |
1 | U-boot for arm64 |
2 | ||
3 | Summary | |
4 | ======= | |
5 | No hardware platform of arm64 is available now. The u-boot is | |
6 | simulated on Foundation Model and Fast Model for ARMv8. | |
7 | ||
8 | Notes | |
9 | ===== | |
10 | ||
11 | 1. Currenly, u-boot run at the highest exception level processor | |
12 | supported and jump to EL2 or optionally EL1 before enter OS. | |
13 | ||
14 | 2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc | |
15 | use rela relocation format, a tool(tools/relocate-rela) by Scott Wood | |
16 | is used to encode the initial addend of rela to u-boot.bin. After running, | |
17 | the u-boot will be relocated to destination again. | |
18 | ||
19 | 3. Fdt should be placed at a 2-megabyte boundary and within the first 512 | |
20 | megabytes from the start of the kernel image. So, fdt_high should be | |
21 | defined specially. | |
22 | Please reference linux/Documentation/arm64/booting.txt for detail. | |
23 | ||
24 | 4. Spin-table is used to wake up secondary processors. One location | |
25 | (or per processor location) is defined to hold the kernel entry point | |
26 | for secondary processors. It must be ensured that the location is | |
27 | accessible and zero immediately after secondary processor | |
28 | enter slave_cpu branch execution in start.S. The location address | |
29 | is encoded in cpu node of DTS. Linux kernel store the entry point | |
30 | of secondary processors to it and send event to wakeup secondary | |
31 | processors. | |
32 | Please reference linux/Documentation/arm64/booting.txt for detail. | |
33 | ||
34 | 5. Generic board is supported. | |
35 | ||
36 | 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and | |
37 | aarch32 specific codes. | |
38 | ||
94f7ff36 ST |
39 | 7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores |
40 | supporting 64k pages it allows usage of full 48+ virtual/physical addresses | |
41 | ||
42 | Enabling this option requires the following ones to be defined: | |
43 | - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the | |
44 | system memory map (start, length, attributes) | |
45 | - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP | |
46 | - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries | |
47 | - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries | |
48 | for the largest CONFIG_SYS_MEM_MAP entry | |
49 | - CONFIG_COREID_MASK - the mask value used to get the core from the | |
50 | MPIDR_EL1 register | |
51 | - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level | |
52 | page tables | |
53 | - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block | |
54 | entry from L2 page tables | |
55 | - CONFIG_SYS_PGTABLE_SIZE - total size of the page table | |
56 | - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3} | |
57 | ||
58 | ||
59 | ||
60 | ||
0ae76531 DF |
61 | Contributor |
62 | =========== | |
94f7ff36 ST |
63 | Tom Rini <trini@ti.com> |
64 | Scott Wood <scottwood@freescale.com> | |
65 | York Sun <yorksun@freescale.com> | |
66 | Simon Glass <sjg@chromium.org> | |
67 | Sharma Bhupesh <bhupesh.sharma@freescale.com> | |
68 | Rob Herring <robherring2@gmail.com> | |
69 | Sergey Temerkhanov <s.temerkhanov@gmail.com> |