[people/ms/u-boot.git] / doc / README.dk1s10_std32


TODO:	specify IDE i/f
	specify OCI


===============================================================================
	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
===============================================================================
see also [1]-[5]

CPU:	"standard_32"
	32 bit NIOS for 50 MHz
	256 Byte for register file (15 levels)
	4 KByte instruction cache (4 bytes in each cache line)
	4 KByte data cache (4 bytes in each cache line)
	2 KByte On Chip ROM with GERMS boot monitor
	64 KByte On Chip RAM
	MSTEP multiplier
	no Debug Core
	On Chip Instrumentation (OCI) enabled

	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
			CONFIG_SYS_NIOS_CPU_ICACHE	     = 4096
			CONFIG_SYS_NIOS_CPU_DCACHE	     = 4096
			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 256
			CONFIG_SYS_NIOS_CPU_MUL	     = 0
			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0

OCI:	(TODO)

IRQ:	 Nr.  | used by
	------+--------------------------------------------------------
	 16   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
	 25   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 25
	 30   | LAN91C111 |  CONFIG_SYS_NIOS_CPU_LAN0_IRQ   = 30
	 35   | PIO5	  |  CONFIG_SYS_NIOS_CPU_PIO5_IRQ   = 35
	 40   | PIO0	  |  CONFIG_SYS_NIOS_CPU_PIO0_IRQ   = 40
	 50   | TIMER1	  |  CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50

MEMORY:	 8 MByte Flash
	 1 MByte SRAM
	16 MByte SDRAM

Timer:	TIMER0: high priority programmable timer (IRQ16)
	TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)

	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 1
			CONFIG_SYS_NIOS_CPU_USER_TIMER	     = 0

PIO:	 Nr.  | description
	------+--------------------------------------------------------
	 PIO0 | BUTTON:	    4 inputs for user push buttons (IRQ40)
	 PIO1 | LCD:	   11 in/outputs for ASCII LCD
	 PIO2 | LED:	    8 outputs for user LEDs
	 PIO3 | SEVENSEG:  16 outputs for user seven segment display
	 PIO4 | RECONF:	    1 in/output for . . . . . . . . . . . .
	 PIO5 | CFPRESENT:  1 input for CF present event (IRQ35)
	 PIO6 | CFPOWER:    1 output to controll CF power supply
	 PIO7 | CFATASEL:   1 output to controll CF ATA card select

	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 0
			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = 1
			CONFIG_SYS_NIOS_CPU_LED_PIO	     = 2
			CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = 3
			CONFIG_SYS_NIOS_CPU_RECONF_PIO	     = 4
			CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO   = 5
			CONFIG_SYS_NIOS_CPU_CFPOWER_PIO     = 6
			CONFIG_SYS_NIOS_CPU_CFATASEL_PIO    = 7

UART:	UART0: fixed baudrate of 115200, fixed protocol 8N1,
	       without handshake RTS/CTS (IRQ25)

LAN:	SMsC LAN91C111 with:
	  - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
	  - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)

IDE:	(TODO)


===============================================================================
	M E M O R Y   M A P
===============================================================================

- - - - - - - - - - -  external memory 2  - - - - - - - - - - - - - - - - - - -

  0x02000000 ---32-----------16|15------------0-
	       |	       :	       | \
	       |	       :	       | |
  SDRAM	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
	       |	       :	       | |   = 0x01000000
	       |	       :	       | /
  0x01000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SDRAM_BASE
	       |			       |
	       :	      gap	       :
	       :			       :

- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -

	       :			       :
	       :	      gap	       :
	       |			       |
  0x00920a80 ---32-----------16|15------------0-
	       |	       |	       | \
	       :  (real size   :	       : |
  IDE i/f      :   and content :	       :  > 0x00000080
  [5]	       :   unknown)    :	       : |
	       |	       |	       | /
  0x00920a00 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE0
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  TIMER1       |		     (unused)  | |
  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
	       |		     (unused)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  control (1 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  status (2 bit)	 (rw)  | /
  0x009209e0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER1
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO7	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (wo)  | /
  0x009209d0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO7
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO6	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (wo)  | /
  0x009209c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO6
	       |  edgecapture (1 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO5	       |  interruptmask (1 bit)	 (rw)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (ro)  | /
  0x009209b0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO5
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO4	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (1 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (1 bit)		 (rw)  | /
  0x009209a0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO4
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO3	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (16 bit)		 (wo)  | /
  0x00920990 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO2	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (8 bit)		 (wo)  | /
  0x00920980 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO1	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (11 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (11 bit)		 (rw)  | /
  0x00920970 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
	       |  edgecapture (4 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO0	       |  interruptmask (4 bit)	 (rw)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (4 bit)		 (ro)  | /
  0x00920960 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |  snaph (16 bit)	 (rw)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  TIMER0       |  snapl (16 bit)	 (rw)  | |
  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
	       |  periodh (16 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  periodl (16 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  control (4 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  status (2 bit)	 (rw)  | /
  0x00920940 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
	       |			       | \
	       :	      gap	       :  > (space for UART1)
	       |			       | /
  0x00920920 ---32-----------16|15------------0-
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  UART0	       |		     (unused)  |  > 0x00000020
  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
	       |  control (10 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  status (10 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  txdata (8 bit)	 (wo)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  rxdata (8 bit)	 (ro)  | /
  0x00920900 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0

- - - - - - - - - - -  on chip debugging  - - - - - - - - - - - - - - - - - - -

  0x00920900 -----------------------------------
	       |			       | \
	       :  (real size		       : |
  OCI Debug    :   and content		       :  > CONFIG_SYS_NIOS_CPU_OCI_SIZE
	       :   unknown)		       : |   = 0x00000100
	       |			       | /
  0x00920800 -----------------------------------    CONFIG_SYS_NIOS_CPU_OCI_BASE

- - - - - - - - - - -  on chip memory 2	  - - - - - - - - - - -

  0x00920800 ---32-----------16|15------------0-
	       |	       :	       | \
	       |	       :	       | |
  GERMS	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_ROM_SIZE
	       |	       :	       | |   = 0x00000800
	       |	       :	       | /
  0x00920000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
  0x00920000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ROM_BASE

- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -

  0x00920000 ---32-----------16|15------------0-
	       |	      gap	       | \
  0x00910310 --+-------------------------------| |
	       |			       | |
	       |  register bank (size = 0x10)  | |
	       | +--------.---.---.---	       | |
	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
	       | |---------------------------+ | |
  LAN91C111    | | BANK	       | RESERVED    | | |
	       | |- - - - - - -|- - - - - - -| |  > na_lan91c111_size
	       | | RPCR	       | MIR	     | | |   = 0x00010000
	       | |- - - - - - -|- - - - - - -| | |
	       | | COUNTER     | RCR	     | | |
	       | |- - - - - - -|- - - - - - -| | |
	       | | EPH STATUS  | TCR	     | | |
	       | +---------------------------+ | |
  0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
	       |	      gap	       | /
  0x00910000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_LAN0_BASE

- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -

  0x00910000 ---32-----------16|15------------0-
	       |	       :	       | \
	       |	       :	       | |
  onchip RAM   |	       :	       |  > CONFIG_SYS_NIOS_CPU_RAM_SIZE
	       |	       :	       | |   = 0x00010000
	       |	       :	       | /
  0x00900000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_RAM_BASE

- - - - - - - - - - -  external memory 1  - - - - - - - - - - - - - - - - - - -

  0x00900000 ---32-----------16|15------------0-
  0x00900000 --+32-----------16|15------------0+
	       |	       .	       | \ \
	       |	       .	       | | |
	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
	       |	       .	       | | |   = 0x00000100
	       |	       .	       | | /
  0x008fff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
  0x008fff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
	       |	       .	       | | \
	       |	       .	       | | |
	       |	       .	       | |  > stack area
	       |	       .	       | | |
	       |	       .	       | | V
	       |	       .	       | |
  SRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
	       |	       .	       | |   = 0x00100000
	       |			       | /
  0x00800000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
  0x00800000 ---8-------------4|3-------------0-
	       |  sector 127		       | \
    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
	       |	       :	       | |
  Flash	       |-   -	-   -  :  -   -	  -   -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
	       |  sector 1     :	       | |   = 0x00800000
    + 0x010000 |- - - - - - - - - - - - - - - -| |
	       |  sector 0 (size = 0x10000)    | /
  0x00000000 ---8-------------4|3-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE


===============================================================================
	F L A S H   M E M O R Y	  A L L O C A T I O N
===============================================================================

  0x00800000 ---8-------------4|3-------------0-
	       |	       :	       | \
  SAFE	       |	       :	       |  > 1 MByte
  FPGA conf.   |	       :	       | /    (NOT usable by software)
  0x00700000 --+- - - - - - - -:- - - - - - - -+-
	       |	       :	       | \
  USER	       |	       :	       |  > 1 MByte
  FPGA conf.   |	       :	       | /    (NOT usable by software)
  0x00600000 --+- - - - - - - -:- - - - - - - -+-
	       |	       :	       | \
	       |	       :	       | |
  WEB pages    |	       :	       |  > 2 MByte
	       |	       :	       | |    (provisory usable)
	       |	       :	       | /
  0x00400000 --+- - - - - - - -:- - - - - - - -+-
	       |	       :	       | \
	       |	       :	       | |
	       |	       :	       | |
	       |	       :	       |  > 4 MByte free for use
	       |	       :	       | |
  0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
	       |	       :	       | /
  0x00000000   |- - - - - - - -:- - - - - - - -+- - u-boot environment
  0x00000000 ---8-------------4|3-------------0-


===============================================================================
	R E F E R E N C E S
===============================================================================
[1]	http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
[5]	http://www.opencores.org/projects/ata/
	http://www.t13.org/index.html


===============================================================================
Stephan Linz <linz@li-pro.net>
Commit	Line	Data
c935d3bd WD	1
	2	TODO: specify IDE i/f
	3	specify OCI
	4
	5
	6	===============================================================================
	7	C P U , M E M O R Y , I N / O U T C O M P O N E N T S
	8	===============================================================================
	9	see also [1]-[5]
	10
	11	CPU: "standard_32"
	12	32 bit NIOS for 50 MHz
	13	256 Byte for register file (15 levels)
	14	4 KByte instruction cache (4 bytes in each cache line)
	15	4 KByte data cache (4 bytes in each cache line)
	16	2 KByte On Chip ROM with GERMS boot monitor
	17	64 KByte On Chip RAM
	18	MSTEP multiplier
	19	no Debug Core
	20	On Chip Instrumentation (OCI) enabled
	21
6d0f6bcf JCPV	22	U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000
	23	CONFIG_SYS_NIOS_CPU_ICACHE = 4096
	24	CONFIG_SYS_NIOS_CPU_DCACHE = 4096
	25	CONFIG_SYS_NIOS_CPU_REG_NUMS = 256
	26	CONFIG_SYS_NIOS_CPU_MUL = 0
	27	CONFIG_SYS_NIOS_CPU_MSTEP = 1
	28	CONFIG_SYS_NIOS_CPU_DBG_CORE = 0
c935d3bd WD	29
	30	OCI: (TODO)
	31
	32	IRQ: Nr. \| used by
	33	------+--------------------------------------------------------
6d0f6bcf JCPV	34	16 \| TIMER0 \| CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
	35	25 \| UART0 \| CONFIG_SYS_NIOS_CPU_UART0_IRQ = 25
	36	30 \| LAN91C111 \| CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 30
	37	35 \| PIO5 \| CONFIG_SYS_NIOS_CPU_PIO5_IRQ = 35
	38	40 \| PIO0 \| CONFIG_SYS_NIOS_CPU_PIO0_IRQ = 40
	39	50 \| TIMER1 \| CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50
c935d3bd WD	40
	41	MEMORY: 8 MByte Flash
	42	1 MByte SRAM
	43	16 MByte SDRAM
	44
	45	Timer: TIMER0: high priority programmable timer (IRQ16)
	46	TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
	47
6d0f6bcf JCPV	48	U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 1
6d0f6bcf JCPV	49	CONFIG_SYS_NIOS_CPU_USER_TIMER = 0
c935d3bd WD	50
	51	PIO: Nr. \| description
	52	------+--------------------------------------------------------
	53	PIO0 \| BUTTON: 4 inputs for user push buttons (IRQ40)
	54	PIO1 \| LCD: 11 in/outputs for ASCII LCD
	55	PIO2 \| LED: 8 outputs for user LEDs
	56	PIO3 \| SEVENSEG: 16 outputs for user seven segment display
	57	PIO4 \| RECONF: 1 in/output for . . . . . . . . . . . .
	58	PIO5 \| CFPRESENT: 1 input for CF present event (IRQ35)
	59	PIO6 \| CFPOWER: 1 output to controll CF power supply
	60	PIO7 \| CFATASEL: 1 output to controll CF ATA card select
	61
6d0f6bcf JCPV	62	U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 0
	63	CONFIG_SYS_NIOS_CPU_LCD_PIO = 1
	64	CONFIG_SYS_NIOS_CPU_LED_PIO = 2
	65	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 3
	66	CONFIG_SYS_NIOS_CPU_RECONF_PIO = 4
	67	CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = 5
	68	CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 6
	69	CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = 7
c935d3bd WD	70
	71	UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
	72	without handshake RTS/CTS (IRQ25)
	73
	74	LAN: SMsC LAN91C111 with:
	75	- offset 0x300 (LAN91C111_REGISTERS_OFFSET)
	76	- data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
	77
	78	IDE: (TODO)
	79
	80
	81	===============================================================================
	82	M E M O R Y M A P
	83	===============================================================================
	84
	85	- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
	86
	87	0x02000000 ---32-----------16\|15------------0-
	88	\| : \| \
	89	\| : \| \|
6d0f6bcf	90	SDRAM \| : \| > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
c935d3bd WD	91	\| : \| \| = 0x01000000
c935d3bd WD	92	\| : \| /
6d0f6bcf	93	0x01000000 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE
c935d3bd WD	94	\| \|
	95	: gap :
	96	: :
	97
	98	- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
	99
	100	: :
	101	: gap :
	102	\| \|
	103	0x00920a80 ---32-----------16\|15------------0-
	104	\| \| \| \
	105	: (real size : : \|
	106	IDE i/f : and content : : > 0x00000080
	107	[5] : unknown) : : \|
	108	\| \| \| /
6d0f6bcf	109	0x00920a00 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_IDE0
c935d3bd WD	110	\| (unused) \| \
	111	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
	112	\| (unused) \| \|
	113	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
	114	\| (unused) \| \|
	115	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
	116	TIMER1 \| (unused) \| \|
	117	[3] + 0x10 \|- - - - - - - - - - - - - - - -\| > 0x00000020
	118	\| (unused) \| \|
	119	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	120	\| (unused) \| \|
	121	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
	122	\| control (1 bit) (rw) \| \|
	123	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	124	\| status (2 bit) (rw) \| /
6d0f6bcf	125	0x009209e0 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_TIMER1
c935d3bd WD	126	\| (unused) \| \
	127	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	128	PIO7 \| (unused) \| \|
	129	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	130	\| (unused) \| \|
	131	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	132	\| data (1 bit) (wo) \| /
6d0f6bcf	133	0x009209d0 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO7
c935d3bd WD	134	\| (unused) \| \
	135	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	136	PIO6 \| (unused) \| \|
	137	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	138	\| (unused) \| \|
	139	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	140	\| data (1 bit) (wo) \| /
6d0f6bcf	141	0x009209c0 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO6
c935d3bd WD	142	\| edgecapture (1 bit) (rw) \| \
	143	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	144	PIO5 \| interruptmask (1 bit) (rw) \| \|
	145	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	146	\| (unused) \| \|
	147	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	148	\| data (1 bit) (ro) \| /
6d0f6bcf	149	0x009209b0 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO5
c935d3bd WD	150	\| (unused) \| \
	151	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	152	PIO4 \| (unused) \| \|
	153	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	154	\| direction (1 bit) (rw) \| \|
	155	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	156	\| data (1 bit) (rw) \| /
6d0f6bcf	157	0x009209a0 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO4
c935d3bd WD	158	\| (unused) \| \
	159	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	160	PIO3 \| (unused) \| \|
	161	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	162	\| (unused) \| \|
	163	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	164	\| data (16 bit) (wo) \| /
6d0f6bcf	165	0x00920990 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO3
c935d3bd WD	166	\| (unused) \| \
	167	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	168	PIO2 \| (unused) \| \|
	169	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	170	\| (unused) \| \|
	171	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	172	\| data (8 bit) (wo) \| /
6d0f6bcf	173	0x00920980 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO2
c935d3bd WD	174	\| (unused) \| \
	175	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	176	PIO1 \| (unused) \| \|
	177	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	178	\| direction (11 bit) (rw) \| \|
	179	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	180	\| data (11 bit) (rw) \| /
6d0f6bcf	181	0x00920970 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO1
c935d3bd WD	182	\| edgecapture (4 bit) (rw) \| \
	183	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	184	PIO0 \| interruptmask (4 bit) (rw) \| \|
	185	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	186	\| (unused) \| \|
	187	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	188	\| data (4 bit) (ro) \| /
6d0f6bcf	189	0x00920960 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO0
c935d3bd WD	190	\| (unused) \| \
	191	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
	192	\| (unused) \| \|
	193	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
	194	\| snaph (16 bit) (rw) \| \|
	195	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
	196	TIMER0 \| snapl (16 bit) (rw) \| \|
	197	[3] + 0x10 \|- - - - - - - - - - - - - - - -\| > 0x00000020
	198	\| periodh (16 bit) (rw) \| \|
	199	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	200	\| periodl (16 bit) (rw) \| \|
	201	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
	202	\| control (4 bit) (rw) \| \|
	203	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	204	\| status (2 bit) (rw) \| /
6d0f6bcf	205	0x00920940 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0
c935d3bd WD	206	\| \| \
	207	: gap : > (space for UART1)
	208	\| \| /
	209	0x00920920 ---32-----------16\|15------------0-
	210	\| (unused) \| \
	211	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
	212	\| (unused) \| \|
	213	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
	214	\| (unused) \| \|
	215	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
	216	UART0 \| (unused) \| > 0x00000020
	217	[2] + 0x10 \|- - - - - - - - - - - - - - - -\| \|
	218	\| control (10 bit) (rw) \| \|
	219	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	220	\| status (10 bit) (rw) \| \|
	221	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
	222	\| txdata (8 bit) (wo) \| \|
	223	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	224	\| rxdata (8 bit) (ro) \| /
6d0f6bcf	225	0x00920900 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_UART0
c935d3bd WD	226
	227	- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
	228
	229	0x00920900 -----------------------------------
	230	\| \| \
	231	: (real size : \|
6d0f6bcf	232	OCI Debug : and content : > CONFIG_SYS_NIOS_CPU_OCI_SIZE
c935d3bd WD	233	: unknown) : \| = 0x00000100
c935d3bd WD	234	\| \| /
6d0f6bcf	235	0x00920800 ----------------------------------- CONFIG_SYS_NIOS_CPU_OCI_BASE
c935d3bd WD	236
	237	- - - - - - - - - - - on chip memory 2 - - - - - - - - - - -
	238
	239	0x00920800 ---32-----------16\|15------------0-
	240	\| : \| \
	241	\| : \| \|
6d0f6bcf	242	GERMS \| : \| > CONFIG_SYS_NIOS_CPU_ROM_SIZE
c935d3bd WD	243	\| : \| \| = 0x00000800
c935d3bd WD	244	\| : \| /
6d0f6bcf JCPV	245	0x00920000 \|- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
6d0f6bcf JCPV	246	0x00920000 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE
c935d3bd WD	247
	248	- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
	249
	250	0x00920000 ---32-----------16\|15------------0-
	251	\| gap \| \
	252	0x00910310 --+-------------------------------\| \|
	253	\| \| \|
	254	\| register bank (size = 0x10) \| \|
	255	\| +--------.---.---.--- \| \|
	256	\| \| bank 0 \ 1 \ 2 \ 3 \ \| \|
	257	\| \|---------------------------+ \| \|
	258	LAN91C111 \| \| BANK \| RESERVED \| \| \|
	259	\| \|- - - - - - -\|- - - - - - -\| \| > na_lan91c111_size
	260	\| \| RPCR \| MIR \| \| \| = 0x00010000
	261	\| \|- - - - - - -\|- - - - - - -\| \| \|
	262	\| \| COUNTER \| RCR \| \| \|
	263	\| \|- - - - - - -\|- - - - - - -\| \| \|
	264	\| \| EPH STATUS \| TCR \| \| \|
	265	\| +---------------------------+ \| \|
	266	0x00910300 --+--LAN91C111_REGISTERS_OFFSET---\| \|
	267	\| gap \| /
6d0f6bcf	268	0x00910000 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE
c935d3bd WD	269
	270	- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
	271
	272	0x00910000 ---32-----------16\|15------------0-
	273	\| : \| \
	274	\| : \| \|
6d0f6bcf	275	onchip RAM \| : \| > CONFIG_SYS_NIOS_CPU_RAM_SIZE
c935d3bd WD	276	\| : \| \| = 0x00010000
c935d3bd WD	277	\| : \| /
6d0f6bcf	278	0x00900000 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_RAM_BASE
c935d3bd WD	279
	280	- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
	281
	282	0x00900000 ---32-----------16\|15------------0-
	283	0x00900000 --+32-----------16\|15------------0+
	284	\| . \| \ \
	285	\| . \| \| \|
6d0f6bcf	286	\| . \| \| > CONFIG_SYS_NIOS_CPU_VEC_SIZE
c935d3bd WD	287	\| . \| \| \| = 0x00000100
c935d3bd WD	288	\| . \| \| /
6d0f6bcf JCPV	289	0x008fff00 \|- - - - - - - - - - - - - - - -+-\|- CONFIG_SYS_NIOS_CPU_VEC_BASE
6d0f6bcf JCPV	290	0x008fff00 \|- - - - - - - - - - - - - - - -+-\|- CONFIG_SYS_NIOS_CPU_STACK
c935d3bd WD	291	\| . \| \| \
	292	\| . \| \| \|
	293	\| . \| \| > stack area
	294	\| . \| \| \|
	295	\| . \| \| V
	296	\| . \| \|
6d0f6bcf	297	SRAM \| . \| > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
c935d3bd WD	298	\| . \| \| = 0x00100000
c935d3bd WD	299	\| \| /
6d0f6bcf	300	0x00800000 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE
c935d3bd WD	301	0x00800000 ---8-------------4\|3-------------0-
	302	\| sector 127 \| \
	303	+ 0x7f0000 \|- - - - - - - - - - - - - - - -\| \|
	304	\| : \| \|
6d0f6bcf	305	Flash \|- - - - : - - - -\| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
c935d3bd WD	306	\| sector 1 : \| \| = 0x00800000
	307	+ 0x010000 \|- - - - - - - - - - - - - - - -\| \|
	308	\| sector 0 (size = 0x10000) \| /
6d0f6bcf	309	0x00000000 ---8-------------4\|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE
c935d3bd WD	310
	311
	312	===============================================================================
	313	F L A S H M E M O R Y A L L O C A T I O N
	314	===============================================================================
	315
	316	0x00800000 ---8-------------4\|3-------------0-
	317	\| : \| \
	318	SAFE \| : \| > 1 MByte
	319	FPGA conf. \| : \| / (NOT usable by software)
	320	0x00700000 --+- - - - - - - -:- - - - - - - -+-
	321	\| : \| \
	322	USER \| : \| > 1 MByte
	323	FPGA conf. \| : \| / (NOT usable by software)
	324	0x00600000 --+- - - - - - - -:- - - - - - - -+-
	325	\| : \| \
	326	\| : \| \|
	327	WEB pages \| : \| > 2 MByte
	328	\| : \| \| (provisory usable)
	329	\| : \| /
	330	0x00400000 --+- - - - - - - -:- - - - - - - -+-
	331	\| : \| \
	332	\| : \| \|
	333	\| : \| \|
	334	\| : \| > 4 MByte free for use
	335	\| : \| \|
	336	0x00040000 --+- - - - - - - -:- - - - - - - -+-\|- u-boot _start()
	337	\| : \| /
ec4c544b	338	0x00000000 \|- - - - - - - -:- - - - - - - -+- - u-boot environment
c935d3bd WD	339	0x00000000 ---8-------------4\|3-------------0-
	340
	341
	342	===============================================================================
	343	R E F E R E N C E S
	344	===============================================================================
	345	[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
	346	[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
	347	[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
	348	[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
	349	[5] http://www.opencores.org/projects/ata/
	350	http://www.t13.org/index.html
	351
	352
	353	===============================================================================
	354	Stephan Linz <linz@li-pro.net>