[people/ms/u-boot.git] / doc / README.dk20k200_std32


===============================================================================
	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
===============================================================================
see also [1]-[4]

CPU:	"standard_32"
	32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
	256 Byte for register file (15 levels)
	no instruction cache
	no data cache
	1 KByte On Chip ROM with GERMS boot monitor
	no On Chip RAM
	MSTEP multiplier
	no Debug Core
	no On Chip Instrumentation (OCI) enabled

	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
			CONFIG_SYS_NIOS_CPU_ICACHE	     = 0
			CONFIG_SYS_NIOS_CPU_DCACHE	     = 0
			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 256
			CONFIG_SYS_NIOS_CPU_MUL	     = 0
			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0

IRQ:	 Nr.  | used by
	------+--------------------------------------------------------
	 25   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 25
	 26   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 26
	 27   | PIO2	  |  CONFIG_SYS_NIOS_CPU_PIO2_IRQ   = 27
	 28   | UART1	  |  CONFIG_SYS_NIOS_CPU_UART1_IRQ  = 28    (debug)

MEMORY:	  1 MByte Flash
	256 KByte SRAM
	(SDRAM with standard SODIMM only)

Timer:	TIMER0: high priority programmable timer (IRQ25)

	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 0

PIO:	 Nr.  | description
	------+--------------------------------------------------------
	 PIO0 | SEVENSEG:  16 outputs for user seven segment display
	 PIO1 | LED:	    8 outputs for user LEDs
	 PIO2 | BUTTON:	    4 inputs for user push buttons (IRQ27)
	 PIO3 | LCD:	   11 in/outputs for ASCII LCD

	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = 0
			CONFIG_SYS_NIOS_CPU_LED_PIO	     = 1
			CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 2
			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = 3

UART:	UART0: fixed baudrate of 115200, fixed protocol 8N2,
	       without handshake RTS/CTS (IRQ26)
	UART1: fixed baudrate of 115200, fixed protocol 8N1,
	       without handshake RTS/CTS (IRQ28)


===============================================================================
	M E M O R Y   M A P
===============================================================================

- - - - - - - - - - -	external memory	  - - - - - - - - - - - - - - - - - - -

  0x00200000 ---15------------8|7-------------0-
	       |  sector 18		       | \
    + 0x0f0000 |- - - - - - - - - - - - - - - -| |
	       |	       :	       | |
  Flash	       |-   -	-   -  :  -   -	  -   -| |
	       |  sector 5     :	       | |
    + 0x020000 |-   -	-   -  -  -   -	  -   -| |
	       |  sector 4 (size = 0x10000)    | |
    + 0x010000 |- - - - - - - - - - - - - - - -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
	       |  sector 3 (size = 0x08000)    | |   = 0x00100000
    + 0x008000 |- - - - - - - - - - - - - - - -| |
	       |  sector 2 (size = 0x02000)    | |
    + 0x006000 |- - - - - - - - - - - - - - - -| |
	       |  sector 1 (size = 0x02000)    | |
    + 0x004000 |- - - - - - - - - - - - - - - -| |
	       |  sector 0 (size = 0x04000)    | /
  0x00100000 ---15------------8|7-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
	       |			       |
	       :	      gap	       :
	       |			       |
  0x00080000 ---32-----------16|15------------0-
  0x00080000 --+32-----------16|15------------0+
	       |	       .	       | \ \
	       |	       .	       | | |
	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
	       |	       .	       | | |   = 0x00000100
	       |	       .	       | | /
  0x0007ff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
  0x0007ff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
	       |	       .	       | | \
	       |	       .	       | | |
	       |	       .	       | |  > stack area
	       |	       .	       | | |
	       |	       .	       | | V
	       |	       .	       | |
  SRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
	       |	       .	       | |   = 0x00040000
	       |			       | /
  0x00040000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
	       |			       |
	       :	      gap	       :
	       :			       :

- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -

	       :			       :
	       :	      gap	       :
	       |			       |
  0x00000400 ---32-----------16|15------------0-
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  UART1	       |		     (unused)  |  > 0x00000020
  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
	       |  control (10 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  status (10 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  txdata (8 bit)	 (wo)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  rxdata (8 bit)	 (ro)  | /
  0x000004c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART1
	       |			       |
	       :	      gap	       :
	       |			       |
  0x00000490 ---32-----------16|15------------0-
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO3	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (11 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (11 bit)		 (rw)  | /
  0x00000480 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
	       |  edgecapture (12 bit)	 (rw)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO2	       |  interruptmask (12 bit) (rw)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (12 bit)		 (ro)  | /
  0x00000470 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO1	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |  direction (2 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (2 bit)		 (rw)  | /
  0x00000460 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |  snaph (16 bit)	 (rw)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  TIMER0       |  snapl (16 bit)	 (rw)  | |
  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
	       |  periodh (16 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  periodl (16 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  control (4 bit)	 (rw)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  status (2 bit)	 (rw)  | /
  0x00000440 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
	       |		     (unused)  | \
	+ 0x0c |- - - - - - - - - - - - - - - -| |
  PIO0	       |		     (unused)  | |
  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
	       |		     (unused)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  data (16 bit)		 (wo)  | /
  0x00000420 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
	       |		     (unused)  | \
	+ 0x1c |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x18 |- - - - - - - - - - - - - - - -| |
	       |		     (unused)  | |
	+ 0x14 |- - - - - - - - - - - - - - - -| |
  UART0	       |		     (unused)  |  > 0x00000020
  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
	       |  control (10 bit)	 (rw)  | |
	+ 0x0c |- - - - - - - - - - - - - - - -| |
	       |  status (10 bit)	 (rw)  | |
	+ 0x08 |- - - - - - - - - - - - - - - -| |
	       |  txdata (8 bit)	 (wo)  | |
	+ 0x04 |- - - - - - - - - - - - - - - -| |
	       |  rxdata (8 bit)	 (ro)  | /
  0x00000400 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0

- - - - - - - - - - -	on chip memory	  - - - - - - - - - - -

  0x00000400 ---32-----------16|15------------0-
	       |	       :	       | \
	       |	       :	       | |
  GERMS	       |	       :	       |  > na_boot_monitor_rom_size
	       |	       :	       | |   = 0x00000400
	       |	       :	       | /
  0x00000000   |- - - - - - - - - - - - - - - -+- - nasys_reset_address
  0x00000000 ---32-----------16|15------------0-    na_boot_monitor_rom


===============================================================================
	F L A S H   M E M O R Y	  A L L O C A T I O N
===============================================================================

  0x00200000 ---15------------8|7-------------0-
	       |	       :	       | \
  SAFE	       |	       :	       |  > 256 KByte
  FPGA conf.   |	       :	       | /    (NOT usable by software)
  0x001c0000 --+- - - - - - - -:- - - - - - - -+-
	       |	       :	       | \
  USER	       |	       :	       |  > 256 KByte
  FPGA conf.   |	       :	       | /    (NOT usable by software)
  0x00180000 --+- - - - - - - -:- - - - - - - -+-
	       |	       :	       | \
	       |	       :	       | |
	       |	       :	       |  > 512 KByte free for use
  0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
	       |	       :	       | /
  0x00100000 ---15------------8|7-------------0-


===============================================================================
	R E F E R E N C E S
===============================================================================
[1]	http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf


===============================================================================
Stephan Linz <linz@li-pro.net>
Commit	Line	Data
c935d3bd WD	1
	2	===============================================================================
	3	C P U , M E M O R Y , I N / O U T C O M P O N E N T S
	4	===============================================================================
	5	see also [1]-[4]
	6
	7	CPU: "standard_32"
	8	32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
	9	256 Byte for register file (15 levels)
	10	no instruction cache
	11	no data cache
	12	1 KByte On Chip ROM with GERMS boot monitor
	13	no On Chip RAM
	14	MSTEP multiplier
	15	no Debug Core
	16	no On Chip Instrumentation (OCI) enabled
	17
6d0f6bcf JCPV	18	U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000
	19	CONFIG_SYS_NIOS_CPU_ICACHE = 0
	20	CONFIG_SYS_NIOS_CPU_DCACHE = 0
	21	CONFIG_SYS_NIOS_CPU_REG_NUMS = 256
	22	CONFIG_SYS_NIOS_CPU_MUL = 0
	23	CONFIG_SYS_NIOS_CPU_MSTEP = 1
	24	CONFIG_SYS_NIOS_CPU_DBG_CORE = 0
c935d3bd WD	25
	26	IRQ: Nr. \| used by
	27	------+--------------------------------------------------------
6d0f6bcf JCPV	28	25 \| TIMER0 \| CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 25
	29	26 \| UART0 \| CONFIG_SYS_NIOS_CPU_UART0_IRQ = 26
	30	27 \| PIO2 \| CONFIG_SYS_NIOS_CPU_PIO2_IRQ = 27
	31	28 \| UART1 \| CONFIG_SYS_NIOS_CPU_UART1_IRQ = 28 (debug)
c935d3bd WD	32
	33	MEMORY: 1 MByte Flash
	34	256 KByte SRAM
	35	(SDRAM with standard SODIMM only)
	36
	37	Timer: TIMER0: high priority programmable timer (IRQ25)
	38
6d0f6bcf	39	U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 0
c935d3bd WD	40
	41	PIO: Nr. \| description
	42	------+--------------------------------------------------------
	43	PIO0 \| SEVENSEG: 16 outputs for user seven segment display
	44	PIO1 \| LED: 8 outputs for user LEDs
	45	PIO2 \| BUTTON: 4 inputs for user push buttons (IRQ27)
	46	PIO3 \| LCD: 11 in/outputs for ASCII LCD
	47
6d0f6bcf JCPV	48	U-Boot CFG: CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 0
	49	CONFIG_SYS_NIOS_CPU_LED_PIO = 1
	50	CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 2
	51	CONFIG_SYS_NIOS_CPU_LCD_PIO = 3
c935d3bd WD	52
	53	UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,
	54	without handshake RTS/CTS (IRQ26)
	55	UART1: fixed baudrate of 115200, fixed protocol 8N1,
	56	without handshake RTS/CTS (IRQ28)
	57
	58
	59	===============================================================================
	60	M E M O R Y M A P
	61	===============================================================================
	62
	63	- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
	64
	65	0x00200000 ---15------------8\|7-------------0-
	66	\| sector 18 \| \
	67	+ 0x0f0000 \|- - - - - - - - - - - - - - - -\| \|
	68	\| : \| \|
	69	Flash \|- - - - : - - - -\| \|
	70	\| sector 5 : \| \|
	71	+ 0x020000 \|- - - - - - - - -\| \|
	72	\| sector 4 (size = 0x10000) \| \|
6d0f6bcf	73	+ 0x010000 \|- - - - - - - - - - - - - - - -\| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
c935d3bd WD	74	\| sector 3 (size = 0x08000) \| \| = 0x00100000
	75	+ 0x008000 \|- - - - - - - - - - - - - - - -\| \|
	76	\| sector 2 (size = 0x02000) \| \|
	77	+ 0x006000 \|- - - - - - - - - - - - - - - -\| \|
	78	\| sector 1 (size = 0x02000) \| \|
	79	+ 0x004000 \|- - - - - - - - - - - - - - - -\| \|
	80	\| sector 0 (size = 0x04000) \| /
6d0f6bcf	81	0x00100000 ---15------------8\|7-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE
c935d3bd WD	82	\| \|
	83	: gap :
	84	\| \|
	85	0x00080000 ---32-----------16\|15------------0-
	86	0x00080000 --+32-----------16\|15------------0+
	87	\| . \| \ \
	88	\| . \| \| \|
6d0f6bcf	89	\| . \| \| > CONFIG_SYS_NIOS_CPU_VEC_SIZE
c935d3bd WD	90	\| . \| \| \| = 0x00000100
c935d3bd WD	91	\| . \| \| /
6d0f6bcf JCPV	92	0x0007ff00 \|- - - - - - - - - - - - - - - -+-\|- CONFIG_SYS_NIOS_CPU_VEC_BASE
6d0f6bcf JCPV	93	0x0007ff00 \|- - - - - - - - - - - - - - - -+-\|- CONFIG_SYS_NIOS_CPU_STACK
c935d3bd WD	94	\| . \| \| \
	95	\| . \| \| \|
	96	\| . \| \| > stack area
	97	\| . \| \| \|
	98	\| . \| \| V
	99	\| . \| \|
6d0f6bcf	100	SRAM \| . \| > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
c935d3bd WD	101	\| . \| \| = 0x00040000
c935d3bd WD	102	\| \| /
6d0f6bcf	103	0x00040000 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE
c935d3bd WD	104	\| \|
	105	: gap :
	106	: :
	107
	108	- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
	109
	110	: :
	111	: gap :
	112	\| \|
	113	0x00000400 ---32-----------16\|15------------0-
	114	\| (unused) \| \
	115	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
	116	\| (unused) \| \|
	117	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
	118	\| (unused) \| \|
	119	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
ec4c544b	120	UART1 \| (unused) \| > 0x00000020
c935d3bd WD	121	[2] + 0x10 \|- - - - - - - - - - - - - - - -\| \|
	122	\| control (10 bit) (rw) \| \|
	123	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	124	\| status (10 bit) (rw) \| \|
	125	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
	126	\| txdata (8 bit) (wo) \| \|
	127	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	128	\| rxdata (8 bit) (ro) \| /
6d0f6bcf	129	0x000004c0 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_UART1
c935d3bd WD	130	\| \|
	131	: gap :
	132	\| \|
	133	0x00000490 ---32-----------16\|15------------0-
	134	\| (unused) \| \
	135	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	136	PIO3 \| (unused) \| \|
	137	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	138	\| direction (11 bit) (rw) \| \|
	139	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	140	\| data (11 bit) (rw) \| /
6d0f6bcf	141	0x00000480 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO3
c935d3bd WD	142	\| edgecapture (12 bit) (rw) \| \
	143	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	144	PIO2 \| interruptmask (12 bit) (rw) \| \|
	145	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	146	\| (unused) \| \|
	147	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	148	\| data (12 bit) (ro) \| /
6d0f6bcf	149	0x00000470 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO2
c935d3bd WD	150	\| (unused) \| \
	151	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	152	PIO1 \| (unused) \| \|
	153	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	154	\| direction (2 bit) (rw) \| \|
	155	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	156	\| data (2 bit) (rw) \| /
6d0f6bcf	157	0x00000460 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO1
c935d3bd WD	158	\| (unused) \| \
	159	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
	160	\| (unused) \| \|
	161	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
	162	\| snaph (16 bit) (rw) \| \|
	163	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
	164	TIMER0 \| snapl (16 bit) (rw) \| \|
	165	[3] + 0x10 \|- - - - - - - - - - - - - - - -\| > 0x00000020
	166	\| periodh (16 bit) (rw) \| \|
	167	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	168	\| periodl (16 bit) (rw) \| \|
	169	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
	170	\| control (4 bit) (rw) \| \|
	171	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	172	\| status (2 bit) (rw) \| /
6d0f6bcf	173	0x00000440 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0
c935d3bd WD	174	\| (unused) \| \
	175	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	176	PIO0 \| (unused) \| \|
	177	[4] + 0x08 \|- - - - - - - - - - - - - - - -\| > 0x00000010
	178	\| (unused) \| \|
	179	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	180	\| data (16 bit) (wo) \| /
6d0f6bcf	181	0x00000420 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_PIO0
c935d3bd WD	182	\| (unused) \| \
	183	+ 0x1c \|- - - - - - - - - - - - - - - -\| \|
	184	\| (unused) \| \|
	185	+ 0x18 \|- - - - - - - - - - - - - - - -\| \|
	186	\| (unused) \| \|
	187	+ 0x14 \|- - - - - - - - - - - - - - - -\| \|
	188	UART0 \| (unused) \| > 0x00000020
	189	[2] + 0x10 \|- - - - - - - - - - - - - - - -\| \|
	190	\| control (10 bit) (rw) \| \|
	191	+ 0x0c \|- - - - - - - - - - - - - - - -\| \|
	192	\| status (10 bit) (rw) \| \|
	193	+ 0x08 \|- - - - - - - - - - - - - - - -\| \|
	194	\| txdata (8 bit) (wo) \| \|
	195	+ 0x04 \|- - - - - - - - - - - - - - - -\| \|
	196	\| rxdata (8 bit) (ro) \| /
6d0f6bcf	197	0x00000400 ---32-----------16\|15------------0- CONFIG_SYS_NIOS_CPU_UART0
c935d3bd WD	198
	199	- - - - - - - - - - - on chip memory - - - - - - - - - - -
	200
	201	0x00000400 ---32-----------16\|15------------0-
	202	\| : \| \
	203	\| : \| \|
	204	GERMS \| : \| > na_boot_monitor_rom_size
	205	\| : \| \| = 0x00000400
	206	\| : \| /
	207	0x00000000 \|- - - - - - - - - - - - - - - -+- - nasys_reset_address
	208	0x00000000 ---32-----------16\|15------------0- na_boot_monitor_rom
	209
	210
	211	===============================================================================
	212	F L A S H M E M O R Y A L L O C A T I O N
	213	===============================================================================
	214
	215	0x00200000 ---15------------8\|7-------------0-
	216	\| : \| \
	217	SAFE \| : \| > 256 KByte
	218	FPGA conf. \| : \| / (NOT usable by software)
	219	0x001c0000 --+- - - - - - - -:- - - - - - - -+-
	220	\| : \| \
	221	USER \| : \| > 256 KByte
	222	FPGA conf. \| : \| / (NOT usable by software)
	223	0x00180000 --+- - - - - - - -:- - - - - - - -+-
	224	\| : \| \
	225	\| : \| \|
	226	\| : \| > 512 KByte free for use
	227	0x00140000 --+- - - - - - - -:- - - - - - - -+-\|- u-boot _start()
	228	\| : \| /
	229	0x00100000 ---15------------8\|7-------------0-
	230
	231
	232	===============================================================================
	233	R E F E R E N C E S
	234	===============================================================================
	235	[1] http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
	236	[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
	237	[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
	238	[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
	239
	240
	241	===============================================================================
	242	Stephan Linz <linz@li-pro.net>