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c9ffd839 HW |
1 | |
2 | Table of interleaving modes supported in cpu/8xxx/ddr/ | |
3 | ====================================================== | |
4 | +-------------+---------------------------------------------------------+ | |
5 | | | Rank Interleaving | | |
6 | | +--------+-----------+-----------+------------+-----------+ | |
7 | |Memory | | | | 2x2 | 4x1 | | |
8 | |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | | |
9 | |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | | |
10 | +-------------+--------+-----------+-----------+------------+-----------+ | |
11 | |None | Yes | Yes | Yes | Yes | Yes | | |
12 | +-------------+--------+-----------+-----------+------------+-----------+ | |
13 | |Cacheline | Yes | Yes | No | No, Only(*)| Yes | | |
14 | | |CS0 Only| | | {CS0+CS1} | | | |
15 | +-------------+--------+-----------+-----------+------------+-----------+ | |
16 | |Page | Yes | Yes | No | No, Only(*)| Yes | | |
17 | | |CS0 Only| | | {CS0+CS1} | | | |
18 | +-------------+--------+-----------+-----------+------------+-----------+ | |
19 | |Bank | Yes | Yes | No | No, Only(*)| Yes | | |
20 | | |CS0 Only| | | {CS0+CS1} | | | |
21 | +-------------+--------+-----------+-----------+------------+-----------+ | |
22 | |Superbank | No | Yes | No | No, Only(*)| Yes | | |
23 | | | | | | {CS0+CS1} | | | |
24 | +-------------+--------+-----------+-----------+------------+-----------+ | |
25 | (*) Although the hardware can be configured with memory controller | |
26 | interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} | |
27 | from each controller. {CS2+CS3} on each controller are only rank | |
28 | interleaved on that controller. | |
29 | ||
076bff8f YS |
30 | For memory controller interleaving, identical DIMMs are suggested. Software |
31 | doesn't check the size or organization of interleaved DIMMs. | |
32 | ||
c9ffd839 HW |
33 | The ways to configure the ddr interleaving mode |
34 | ============================================== | |
35 | 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting | |
36 | under "CONFIG_EXTRA_ENV_SETTINGS", like: | |
37 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
79e4e648 | 38 | "hwconfig=fsl_ddr:ctlr_intlv=bank" \ |
c9ffd839 HW |
39 | ...... |
40 | ||
41 | 2. Run u-boot "setenv" command to configure the memory interleaving mode. | |
42 | Either numerical or string value is accepted. | |
43 | ||
44 | # disable memory controller interleaving | |
79e4e648 | 45 | setenv hwconfig "fsl_ddr:ctlr_intlv=null" |
c9ffd839 HW |
46 | |
47 | # cacheline interleaving | |
79e4e648 | 48 | setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" |
c9ffd839 HW |
49 | |
50 | # page interleaving | |
79e4e648 | 51 | setenv hwconfig "fsl_ddr:ctlr_intlv=page" |
c9ffd839 HW |
52 | |
53 | # bank interleaving | |
79e4e648 | 54 | setenv hwconfig "fsl_ddr:ctlr_intlv=bank" |
c9ffd839 HW |
55 | |
56 | # superbank | |
79e4e648 | 57 | setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" |
c9ffd839 HW |
58 | |
59 | # disable bank (chip-select) interleaving | |
79e4e648 | 60 | setenv hwconfig "fsl_ddr:bank_intlv=null" |
c9ffd839 HW |
61 | |
62 | # bank(chip-select) interleaving cs0+cs1 | |
79e4e648 | 63 | setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" |
c9ffd839 HW |
64 | |
65 | # bank(chip-select) interleaving cs2+cs3 | |
79e4e648 | 66 | setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" |
c9ffd839 HW |
67 | |
68 | # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) | |
79e4e648 | 69 | setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" |
c9ffd839 HW |
70 | |
71 | # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) | |
79e4e648 KG |
72 | setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" |
73 | ||
7fd101c9 YS |
74 | Memory controller address hashing |
75 | ================================== | |
76 | If the DDR controller supports address hashing, it can be enabled by hwconfig. | |
77 | ||
78 | Syntax is: | |
79 | hwconfig=fsl_ddr:addr_hash=true | |
80 | ||
ebbe11dd YS |
81 | |
82 | Memory testing options for mpc85xx | |
83 | ================================== | |
84 | 1. Memory test can be done once U-boot prompt comes up using mtest, or | |
85 | 2. Memory test can be done with Power-On-Self-Test function, activated at | |
86 | compile time. | |
87 | ||
88 | In order to enable the POST memory test, CONFIG_POST needs to be | |
89 | defined in board configuraiton header file. By default, POST memory test | |
90 | performs a fast test. A slow test can be enabled by changing the flag at | |
91 | compiling time. To test memory bigger than 2GB, 36BIT support is needed. | |
92 | Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB | |
93 | window to physical address so that all physical memory can be tested. | |
94 | ||
7fd101c9 YS |
95 | Combination of hwconfig |
96 | ======================= | |
97 | Hwconfig can be combined with multiple parameters, for example, on a supported | |
98 | platform | |
99 | ||
100 | hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 |