[people/ms/u-boot.git] / doc / README.mpc837xemds

Freescale MPC837xEMDS Board
-----------------------------------------
1.	Board Switches and Jumpers
1.0	There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
	For some reason, the HW designers describe the switch settings
	in terms of 0 and 1, and then map that to physical switches where
	the label "On" refers to logic 0 and "Off" is logic 1.

	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
	bits may contribute to signals that are numbered based at 0,
	and some of those signals may be high-bit-number-0 too.  Heed
	well the names and labels and do not get confused.

		"Off" == 1
		"On"  == 0

	SW4[8] is the bit labled 8 on Switch 4.
	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
	SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
		and bits labeled 8 is set as "Off".

1.1	For the MPC837xEMDS Processor Board

	First, make sure the board default setting is consistent with the
	document shipped with your board. Then apply the following setting:
	SW3[1-8]= 0011_0000  (BOOTSEQ, ROMLOC setting)
	SW4[1-8]= 0000_0110  (core PLL setting)
	SW5[1-8]= 1001_1000  (system PLL, boot up from low end of flash)
	SW6[1-8]= 0000_1000  (HRCW is read from NOR FLASH)
	SW7[1-8]= 0110_1101  (TSEC1/2 interface setting - RGMII)
	J3 2-3, TSEC1 LVDD1 with 2.5V
	J6 2-3, TSEC2 LVDD2 with 2.5V
	J9 2-3, CLKIN from osc on board
	J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
	J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
	    mounted, HRCW load from BCSR.

	on board Oscillator: 66M

2.	Memory Map

2.1.	The memory map should look pretty much like this:

	0x0000_0000	0x7fff_ffff	DDR			2G
	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
	0xc000_0000	0xdfff_ffff	Empty			512M
	0xe000_0000	0xe00f_ffff	Int Mem Reg Space	1M
	0xe010_0000	0xe02f_ffff	Empty			2M
	0xe030_0000	0xe03f_ffff	PCI IO			1M
	0xe040_0000	0xe05f_ffff	Empty			2M
	0xe060_0000	0xe060_7fff	NAND Flash		32K
	0xf400_0000	0xf7ff_ffff	Empty			64M
	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
	0xfe00_0000	0xffff_ffff	NOR Flash on CS0	32M

3. Definitions

3.1 Explanation of NEW definitions in:

	include/configs/MPC837XEMDS.h

    CONFIG_MPC83xx	    MPC83xx family for both MPC837x and MPC8360
    CONFIG_MPC837x	    MPC837x specific
    CONFIG_MPC837XEMDS	    MPC837XEMDS board specific

4. Compilation

	Assuming you're using BASH shell:

		export CROSS_COMPILE=your-cross-compile-prefix
		cd u-boot
		make distclean
		make MPC837XEMDS_config
		make

5. Downloading and Flashing Images

5.0 Download over serial line using Kermit:

	loadb
	[Drop to kermit:
	    ^\c
	    send <u-boot-bin-image>
	    c
	]


    Or via tftp:

	tftp 40000 u-boot.bin

5.1 Reflash U-boot Image using U-boot

	tftp 40000 u-boot.bin
	protect off fe000000 fe1fffff
	erase fe000000 fe1fffff

	cp.b 40000 fe000000 xxxx

You have to supply the correct byte count with 'xxxx' from the TFTP result log.

6. Notes
	1) The console baudrate for MPC837XEMDS is 115200bps.
Commit	Line	Data
f8900ce9 DL	1	Freescale MPC837xEMDS Board
	2	-----------------------------------------
	3	1. Board Switches and Jumpers
53677ef1	4	1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
f8900ce9 DL	5	For some reason, the HW designers describe the switch settings
	6	in terms of 0 and 1, and then map that to physical switches where
	7	the label "On" refers to logic 0 and "Off" is logic 1.
	8
	9	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
	10	bits may contribute to signals that are numbered based at 0,
	11	and some of those signals may be high-bit-number-0 too. Heed
	12	well the names and labels and do not get confused.
	13
	14	"Off" == 1
	15	"On" == 0
	16
	17	SW4[8] is the bit labled 8 on Switch 4.
	18	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
	19	SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
	20	and bits labeled 8 is set as "Off".
	21
	22	1.1 For the MPC837xEMDS Processor Board
	23
	24	First, make sure the board default setting is consistent with the
	25	document shipped with your board. Then apply the following setting:
	26	SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
	27	SW4[1-8]= 0000_0110 (core PLL setting)
	28	SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
	29	SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
	30	SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
	31	J3 2-3, TSEC1 LVDD1 with 2.5V
	32	J6 2-3, TSEC2 LVDD2 with 2.5V
	33	J9 2-3, CLKIN from osc on board
	34	J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
	35	J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
	36	mounted, HRCW load from BCSR.
	37
	38	on board Oscillator: 66M
	39
	40	2. Memory Map
	41
	42	2.1. The memory map should look pretty much like this:
	43
	44	0x0000_0000 0x7fff_ffff DDR 2G
	45	0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
	46	0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
	47	0xc000_0000 0xdfff_ffff Empty 512M
	48	0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
	49	0xe010_0000 0xe02f_ffff Empty 2M
	50	0xe030_0000 0xe03f_ffff PCI IO 1M
	51	0xe040_0000 0xe05f_ffff Empty 2M
be5a7190	52	0xe060_0000 0xe060_7fff NAND Flash 32K
f8900ce9 DL	53	0xf400_0000 0xf7ff_ffff Empty 64M
	54	0xf800_0000 0xf800_7fff BCSR on CS1 32K
	55	0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
	56
	57	3. Definitions
	58
	59	3.1 Explanation of NEW definitions in:
	60
	61	include/configs/MPC837XEMDS.h
	62
0f898604	63	CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
2c7920af	64	CONFIG_MPC837x MPC837x specific
f8900ce9 DL	65	CONFIG_MPC837XEMDS MPC837XEMDS board specific
	66
	67	4. Compilation
	68
	69	Assuming you're using BASH shell:
	70
	71	export CROSS_COMPILE=your-cross-compile-prefix
	72	cd u-boot
	73	make distclean
	74	make MPC837XEMDS_config
	75	make
	76
	77	5. Downloading and Flashing Images
	78
	79	5.0 Download over serial line using Kermit:
	80
	81	loadb
	82	[Drop to kermit:
	83	^\c
	84	send <u-boot-bin-image>
	85	c
	86	]
	87
	88
	89	Or via tftp:
	90
	91	tftp 40000 u-boot.bin
	92
	93	5.1 Reflash U-boot Image using U-boot
	94
	95	tftp 40000 u-boot.bin
	96	protect off fe000000 fe1fffff
	97	erase fe000000 fe1fffff
	98
	99	cp.b 40000 fe000000 xxxx
	100
	101	You have to supply the correct byte count with 'xxxx' from the TFTP result log.
	102
	103	6. Notes
	104	1) The console baudrate for MPC837XEMDS is 115200bps.