[people/ms/u-boot.git] / doc / README.mpc85xx

External Debug Support
----------------------

Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).  In particular, for the debugger to
be able to receive control after a single step or breakpoint:
	- MSR[DE] must be set
	- A valid opcode must be fetchable, through the MMU, from the debug
	  exception vector (IVPR + IVOR15).

To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
immediately on entry and keeps it set. It also uses a temporary TLB to keep a
mapping to a valid opcode at the debug exception vector, even if we normally
don't support exception vectors being used that early, and that's not the area
where U-Boot currently executes from.

Note that there may still be some small windows where debugging will not work,
such as in between updating IVPR and IVOR15.

Config Switches:
----------------

Please refer README section "MPC85xx External Debug Support"

Major Config Switches during various boot Modes
----------------------------------------------

NOR boot
		!defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
NOR boot Secure
		!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
RAMBOOT(SD, SPI & NAND boot)
		 defined(CONFIG_SYS_RAMBOOT)
RAMBOOT Secure (SD, SPI & NAND)
		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
NAND SPL BOOT
		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)


TLB Entries during u-boot execution
-----------------------------------

Note: Sequence number is in order of execution

A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot

   1) TLB entry to overcome e500 v1/v2 debug restriction
       Location	  : Label "_start_e500"
       TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
       Properties : 256K, AS0, I, IPROT

   2) TLB entry for working in AS1
       Location	  : Label "create_init_ram_area"
       TLB Entry  : 15
       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
       Properties : 1M, AS1, I, G, IPROT

   3) TLB entry for the stack during AS1
       Location	  : Lable "create_init_ram_area"
       TLB Entry  : 14
       EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
       Properties : 16K, AS1, IPROT

   4) TLB entry for CCSRBAR during AS1 execution
       Location	  : cpu_init_early_f
       TLB Entry  : 13
       EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
       Properties : 1M, AS1, I, G

   5) Invalidate unproctected TLB Entries
       Location	  : cpu_init_early_f
       Invalidated: 13

   6) Create TLB entries as per boards/freescale/<board>/tlb.c
       Location	  : cpu_init_early_f --> init_tlbs()
       Properties : ..., AS0, ...
      Please note It can overwrites previous TLB Entries.

   7) Disable TLB Entries of AS1
       Location	  : cpu_init_f --> disable_tlb()
       Disable	  : 15, 14

   8) Update Flash's TLB entry
       Location	  : Board_init_r
       TLB entry  : Search from TLB entries
       EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
       Properties : Board specific size, AS0, I, G, IPROT


B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot

   1) TLB entry to overcome e500 v1/v2 debug restriction
       Location	  : Label "_start_e500"
       TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
#if defined(CONFIG_SECURE_BOOT)
       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
       Properties : 1M, AS1, I, G, IPROT
#else
       EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
       Properties : 4M, AS0, I, G, IPROT
#endif

   2) TLB entry for working in AS1
       Location	  : Label "create_init_ram_area"
       TLB Entry  : 15
#if defined(CONFIG_SECURE_BOOT)
       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
       Properties : 1M, AS1, I, G, IPROT
#else
       EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
       Properties : 4M, AS1, I, G, IPROT
#endif

   3) TLB entry for the stack during AS1
       Location	  : Lable "create_init_ram_area"
       TLB Entry  : 14
       EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
       Properties : 16K, AS1, IPROT

   4) TLB entry for CCSRBAR during AS1 execution
       Location	  : cpu_init_early_f
       TLB Entry  : 13
       EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
       Properties : 1M, AS1, I, G

   5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
       Location	  : cpu_init_early_f
       TLB Entry  : 9
       EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
       Properties : 1M, AS1, I

   6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
       Location	  : cpu_init_early_f --> setup_ifc
       TLB Entry  : Get Flash TLB
       EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
       Properties : 4M, AS1, I, G, IPROT

   7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
       Location	  : cpu_init_early_f --> setup_ifc
       TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
       EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
       Properties : 4M, AS0, I, G, IPROT

   8) Invalidate unproctected TLB Entries
       Location	  : cpu_init_early_f
       Invalidated: 13, 9

   9) Create TLB entries as per boards/freescale/<board>/tlb.c
       Location	  : cpu_init_early_f --> init_tlbs()
       Properties : ..., AS0, ...
      Note: It can overwrites previous TLB Entries

   10) Disable TLB Entries of AS1
       Location	  : cpu_init_f --> disable_tlb()
       Disable	  : 15, 14

   11) Create DDR's TLB entriy
       Location	  : Board_init_f -> dram_init
       TLB entry  : Search free TLB entry

   12) Update Flash's TLB entry
       Location	  : Board_init_r
       TLB entry  : Search from TLB entries
       EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
       Properties : Board specific size, AS0, I, G, IPROT
Commit	Line	Data
afa6b551 PK	1	External Debug Support
	2	----------------------
	3
	4	Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
	5	restrictions on external debugging (JTAG). In particular, for the debugger to
	6	be able to receive control after a single step or breakpoint:
	7	- MSR[DE] must be set
	8	- A valid opcode must be fetchable, through the MMU, from the debug
	9	exception vector (IVPR + IVOR15).
	10
	11	To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
	12	immediately on entry and keeps it set. It also uses a temporary TLB to keep a
	13	mapping to a valid opcode at the debug exception vector, even if we normally
	14	don't support exception vectors being used that early, and that's not the area
	15	where U-Boot currently executes from.
	16
	17	Note that there may still be some small windows where debugging will not work,
	18	such as in between updating IVPR and IVOR15.
	19
	20	Config Switches:
	21	----------------
	22
	23	Please refer README section "MPC85xx External Debug Support"
	24
	25	Major Config Switches during various boot Modes
	26	----------------------------------------------
	27
	28	NOR boot
c97cd1ba	29	!defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
afa6b551	30	NOR boot Secure
00c60f91	31	!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
afa6b551	32	RAMBOOT(SD, SPI & NAND boot)
00c60f91	33	defined(CONFIG_SYS_RAMBOOT)
afa6b551	34	RAMBOOT Secure (SD, SPI & NAND)
00c60f91	35	defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
afa6b551	36	NAND SPL BOOT
00c60f91	37	defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
afa6b551 PK	38
	39
	40	TLB Entries during u-boot execution
	41	-----------------------------------
	42
	43	Note: Sequence number is in order of execution
	44
	45	A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
	46
	47	1) TLB entry to overcome e500 v1/v2 debug restriction
00c60f91	48	Location : Label "_start_e500"
afa6b551 PK	49	TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
	50	EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
	51	Properties : 256K, AS0, I, IPROT
	52
	53	2) TLB entry for working in AS1
00c60f91	54	Location : Label "create_init_ram_area"
afa6b551 PK	55	TLB Entry : 15
	56	EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
	57	Properties : 1M, AS1, I, G, IPROT
	58
	59	3) TLB entry for the stack during AS1
00c60f91	60	Location : Lable "create_init_ram_area"
afa6b551 PK	61	TLB Entry : 14
	62	EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
	63	Properties : 16K, AS1, IPROT
	64
	65	4) TLB entry for CCSRBAR during AS1 execution
00c60f91	66	Location : cpu_init_early_f
afa6b551 PK	67	TLB Entry : 13
	68	EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
	69	Properties : 1M, AS1, I, G
	70
	71	5) Invalidate unproctected TLB Entries
00c60f91	72	Location : cpu_init_early_f
afa6b551 PK	73	Invalidated: 13
	74
	75	6) Create TLB entries as per boards/freescale/<board>/tlb.c
00c60f91	76	Location : cpu_init_early_f --> init_tlbs()
afa6b551 PK	77	Properties : ..., AS0, ...
	78	Please note It can overwrites previous TLB Entries.
	79
	80	7) Disable TLB Entries of AS1
00c60f91 WD	81	Location : cpu_init_f --> disable_tlb()
00c60f91 WD	82	Disable : 15, 14
afa6b551 PK	83
afa6b551 PK	84	8) Update Flash's TLB entry
00c60f91	85	Location : Board_init_r
afa6b551 PK	86	TLB entry : Search from TLB entries
	87	EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
	88	Properties : Board specific size, AS0, I, G, IPROT
	89
	90
	91	B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
	92
	93	1) TLB entry to overcome e500 v1/v2 debug restriction
00c60f91	94	Location : Label "_start_e500"
afa6b551 PK	95	TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
	96	#if defined(CONFIG_SECURE_BOOT)
	97	EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
	98	Properties : 1M, AS1, I, G, IPROT
	99	#else
	100	EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
	101	Properties : 4M, AS0, I, G, IPROT
	102	#endif
	103
	104	2) TLB entry for working in AS1
00c60f91	105	Location : Label "create_init_ram_area"
afa6b551 PK	106	TLB Entry : 15
	107	#if defined(CONFIG_SECURE_BOOT)
	108	EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
	109	Properties : 1M, AS1, I, G, IPROT
	110	#else
	111	EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
	112	Properties : 4M, AS1, I, G, IPROT
	113	#endif
	114
	115	3) TLB entry for the stack during AS1
00c60f91	116	Location : Lable "create_init_ram_area"
afa6b551 PK	117	TLB Entry : 14
	118	EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
	119	Properties : 16K, AS1, IPROT
	120
	121	4) TLB entry for CCSRBAR during AS1 execution
00c60f91	122	Location : cpu_init_early_f
afa6b551 PK	123	TLB Entry : 13
	124	EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
	125	Properties : 1M, AS1, I, G
	126
	127	5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
00c60f91	128	Location : cpu_init_early_f
afa6b551 PK	129	TLB Entry : 9
	130	EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
	131	Properties : 1M, AS1, I
	132
	133	6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
00c60f91	134	Location : cpu_init_early_f --> setup_ifc
afa6b551 PK	135	TLB Entry : Get Flash TLB
	136	EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
	137	Properties : 4M, AS1, I, G, IPROT
	138
	139	7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
00c60f91	140	Location : cpu_init_early_f --> setup_ifc
afa6b551 PK	141	TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
	142	EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
	143	Properties : 4M, AS0, I, G, IPROT
	144
	145	8) Invalidate unproctected TLB Entries
00c60f91	146	Location : cpu_init_early_f
afa6b551 PK	147	Invalidated: 13, 9
	148
	149	9) Create TLB entries as per boards/freescale/<board>/tlb.c
00c60f91	150	Location : cpu_init_early_f --> init_tlbs()
afa6b551 PK	151	Properties : ..., AS0, ...
	152	Note: It can overwrites previous TLB Entries
	153
	154	10) Disable TLB Entries of AS1
00c60f91 WD	155	Location : cpu_init_f --> disable_tlb()
00c60f91 WD	156	Disable : 15, 14
afa6b551 PK	157
afa6b551 PK	158	11) Create DDR's TLB entriy
f1683aa7	159	Location : Board_init_f -> dram_init
afa6b551 PK	160	TLB entry : Search free TLB entry
	161
	162	12) Update Flash's TLB entry
00c60f91	163	Location : Board_init_r
afa6b551 PK	164	TLB entry : Search from TLB entries
	165	EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
	166	Properties : Board specific size, AS0, I, G, IPROT