[people/ms/u-boot.git] / doc / README.mvblm7

Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
-------------------------------------

1.	Board Description

	The mvBL-M7 is a 120x120mm single board computing platform
	with strong focus on stereo image processing applications.

	Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
	on any port (requires add-on board).

2	System Components

2.1	CPU
	Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
	512MByte DDR-II memory @ 133MHz.
	8 MByte Nor Flash on local bus.
	2 Vitesse VSC8601 RGMII ethernet Phys.
	1 USB host controller over ULPI I/F.
	2 serial ports. Console running on ttyS0 @ 115200 8N1.
	1 SD-Card slot connected to SPI.
	System configuration (HRCW) is taken from I2C EEPROM.

2.2	PCI
	A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.

2.3	FPGA
	Altera Cyclone-II EP2C20/35 with PCI DMA engines.
	Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
	Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.

2.3.1	I/O @ FPGA
	2x8 Outputs : Infineon High-Side Switches to Main Supply.
	2x8 Inputs  : Programmable input threshold + trigger capabilities
	2 dedicated flash interfaces for illuminator boards.
	Cross trigger for chaining several boards.

2.4	I2C
	Bus1:
		MAX5381 DAC @ 0x60 for 1st digital input threshold.
		LM75 @ 0x90 for temperature monitoring.
		EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
		1st image sensor interface (slave adresses depend on sensor)
	Bus2:
		MAX5381 DAC @ 0x60 for 2nd digital input threshold.
		2nd image sensor interface (slave adresses depend on sensor)

3	Flash layout.

	reset vector is 0xFFF00100, i.e. "HIGHBOOT".

	FF800000	environment
	FF802000	redundant environment
	FF804000	u-boot script image
	FF806000	redundant u-boot script image
	FF808000	device tree blob
	FF80A000	redundant device tree blob
	FF80C000	tbd.
	FF80E000	tbd.
	FF810000	kernel
	FFC00000	root FS
	FFF00000	u-boot
	FFF80000	FPGA raw bit file

	mtd partitions are propagated to linux kernel via device tree blob.

4	Booting

	On startup the bootscript @ FF804000 is executed. This script can be
	exchanged easily. Default boot mode is "boot from flash", i.e. system
	works stand-alone.

	This behaviour depends on some environment variables :

	"netboot" : yes ->try dhcp/bootp and boot from network.
	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
	DHCP server configuration, e.g. to provide different images to
	different devices.

	During netboot the system tries to get 3 image files:
	1. Kernel - name + data is given during BOOTP.
	2. Initrd - name is stored in "initrd_name"
	3. device tree blob - name is stored in "dtb_name"
	Fallback files are the flash versions.
Commit	Line	Data
c005b939 AS	1	Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
	2	-------------------------------------
	3
	4	1. Board Description
	5
	6	The mvBL-M7 is a 120x120mm single board computing platform
	7	with strong focus on stereo image processing applications.
	8
	9	Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
	10	on any port (requires add-on board).
	11
	12	2 System Components
	13
e093a247	14	2.1 CPU
c005b939 AS	15	Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
	16	512MByte DDR-II memory @ 133MHz.
	17	8 MByte Nor Flash on local bus.
	18	2 Vitesse VSC8601 RGMII ethernet Phys.
	19	1 USB host controller over ULPI I/F.
	20	2 serial ports. Console running on ttyS0 @ 115200 8N1.
	21	1 SD-Card slot connected to SPI.
	22	System configuration (HRCW) is taken from I2C EEPROM.
	23
	24	2.2 PCI
	25	A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
e093a247	26
c005b939 AS	27	2.3 FPGA
	28	Altera Cyclone-II EP2C20/35 with PCI DMA engines.
	29	Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
	30	Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
	31
	32	2.3.1 I/O @ FPGA
	33	2x8 Outputs : Infineon High-Side Switches to Main Supply.
	34	2x8 Inputs : Programmable input threshold + trigger capabilities
	35	2 dedicated flash interfaces for illuminator boards.
	36	Cross trigger for chaining several boards.
	37
	38	2.4 I2C
	39	Bus1:
	40	MAX5381 DAC @ 0x60 for 1st digital input threshold.
	41	LM75 @ 0x90 for temperature monitoring.
	42	EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
	43	1st image sensor interface (slave adresses depend on sensor)
	44	Bus2:
	45	MAX5381 DAC @ 0x60 for 2nd digital input threshold.
	46	2nd image sensor interface (slave adresses depend on sensor)
	47
	48	3 Flash layout.
	49
	50	reset vector is 0xFFF00100, i.e. "HIGHBOOT".
	51
	52	FF800000 environment
	53	FF802000 redundant environment
	54	FF804000 u-boot script image
	55	FF806000 redundant u-boot script image
	56	FF808000 device tree blob
	57	FF80A000 redundant device tree blob
	58	FF80C000 tbd.
	59	FF80E000 tbd.
	60	FF810000 kernel
	61	FFC00000 root FS
	62	FFF00000 u-boot
	63	FFF80000 FPGA raw bit file
	64
	65	mtd partitions are propagated to linux kernel via device tree blob.
	66
	67	4 Booting
	68
	69	On startup the bootscript @ FF804000 is executed. This script can be
	70	exchanged easily. Default boot mode is "boot from flash", i.e. system
	71	works stand-alone.
	72
	73	This behaviour depends on some environment variables :
	74
	75	"netboot" : yes ->try dhcp/bootp and boot from network.
	76	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
	77	DHCP server configuration, e.g. to provide different images to
	78	different devices.
	79
	80	During netboot the system tries to get 3 image files:
	81	1. Kernel - name + data is given during BOOTP.
	82	2. Initrd - name is stored in "initrd_name"
	83	3. device tree blob - name is stored in "dtb_name"
	84	Fallback files are the flash versions.