[people/ms/u-boot.git] / doc / README.nand

NAND FLASH commands and notes

See NOTE below!!!

# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA

Commands:

   nand bad
      Print a list of all of the bad blocks in the current device.

   nand device
      Print information about the current NAND device.

   nand device num
      Make device `num' the current device and print information about it.

   nand erase off|partition size
   nand erase clean [off|partition size]
      Erase `size' bytes starting at offset `off'. Alternatively partition
      name can be specified, in this case size will be eventually limited
      to not exceed partition size (this behaviour applies also to read
      and write commands). Only complete erase blocks can be erased.

      If `erase' is specified without an offset or size, the entire flash
      is erased. If `erase' is specified with partition but without an
      size, the entire partition is erased.

      If `clean' is specified, a JFFS2-style clean marker is written to
      each block after it is erased.

      This command will not erase blocks that are marked bad. There is
      a debug option in cmd_nand.c to allow bad blocks to be erased.
      Please read the warning there before using it, as blocks marked
      bad by the manufacturer must _NEVER_ be erased.

   nand info
      Print information about all of the NAND devices found.

   nand read addr ofs|partition size
      Read `size' bytes from `ofs' in NAND flash to `addr'.  Blocks that
      are marked bad are skipped.  If a page cannot be read because an
      uncorrectable data error is found, the command stops with an error.

   nand read.oob addr ofs|partition size
      Read `size' bytes from the out-of-band data area corresponding to
      `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
      data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks or ECC errors.

   nand write addr ofs|partition size
      Write `size' bytes from `addr' to `ofs' in NAND flash.  Blocks that
      are marked bad are skipped.  If a page cannot be read because an
      uncorrectable data error is found, the command stops with an error.

      As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
      as long as the image is short enough to fit even after skipping the
      bad blocks.  Compact images, such as those produced by mkfs.jffs2
      should work well, but loading an image copied from another flash is
      going to be trouble if there are any bad blocks.

   nand write.oob addr ofs|partition size
      Write `size' bytes from `addr' to the out-of-band data area
      corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
      of data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks.

Configuration Options:

   CONFIG_CMD_NAND
      Enables NAND support and commmands.

   CONFIG_MTD_NAND_ECC_JFFS2
      Define this if you want the Error Correction Code information in
      the out-of-band data to be formatted to match the JFFS2 file system.
      CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
      someone to implement.

   CFG_MAX_NAND_DEVICE
      The maximum number of NAND devices you want to support.

NAND Interface:

   #define NAND_WAIT_READY(nand)
      Wait until the NAND flash is ready. Typically this would be a
      loop waiting for the READY/BUSY line from the flash to indicate it
      it is ready.

   #define WRITE_NAND_COMMAND(d, adr)
      Write the command byte `d' to the flash at `adr' with the
      CLE (command latch enable) line true. If your board uses writes to
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_SETCLE()
      and company do it.

   #define WRITE_NAND_ADDRESS(d, adr)
      Write the address byte `d' to the flash at `adr' with the
      ALE (address latch enable) line true. If your board uses writes to
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_SETALE()
      and company do it.

   #define WRITE_NAND(d, adr)
      Write the data byte `d' to the flash at `adr' with the
      ALE and CLE lines false. If your board uses writes to
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_CLRALE()
      and company do it.

   #define READ_NAND(adr)
      Read a data byte from the flash at `adr' with the
      ALE and CLE lines false. If your board uses reads from
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_CLRALE()
      and company do it.

   #define NAND_DISABLE_CE(nand)
      Set CE (Chip Enable) low to enable the NAND flash.

   #define NAND_ENABLE_CE(nand)
      Set CE (Chip Enable) high to disable the NAND flash.

   #define NAND_CTL_CLRALE(nandptr)
      Set ALE (address latch enable) low. If ALE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

   #define NAND_CTL_SETALE(nandptr)
      Set ALE (address latch enable) high. If ALE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

   #define NAND_CTL_CLRCLE(nandptr)
      Set CLE (command latch enable) low. If CLE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

   #define NAND_CTL_SETCLE(nandptr)
      Set CLE (command latch enable) high. If CLE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

More Definitions:

   These definitions are needed in the board configuration for now, but
   may really belong in a header file.
   TODO: Figure which ones are truly configuration settings and rename
	 them to CFG_NAND_... and move the rest somewhere appropriate.

   #define SECTORSIZE 512
   #define ADDR_COLUMN 1
   #define ADDR_PAGE 2
   #define ADDR_COLUMN_PAGE 3
   #define NAND_ChipID_UNKNOWN 0x00
   #define NAND_MAX_FLOORS 1
   #define NAND_MAX_CHIPS 1


NOTE:
=====

We now use a complete rewrite of the NAND code based on what is in
2.6.12 Linux kernel.

The old NAND handling code has been re-factored and is now confined
to only board-specific files and - unfortunately - to the DoC code
(see below). A new configuration variable has been introduced:
CONFIG_NAND_LEGACY, which has to be defined in the board config file if
that board uses legacy code.

The necessary changes have been made to all affected boards, and no
build breakage has been introduced, except for NETTA and NETTA_ISDN
targets from MAKEALL. This is due to the fact that these two boards
use JFFS, which has been adopted to use the new NAND, and at the same
time use NAND in legacy mode. The breakage will disappear when the
board-specific code is changed to the new NAND.

As mentioned above, the legacy code is still used by the DoC subsystem.
The consequence of this is that the legacy NAND can't be removed  from
the tree until the DoC is ported to use the new NAND support (or boards
with DoC will break).


Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006

JFFS2 related commands:

  implement "nand erase clean" and old "nand erase"
  using both the new code which is able to skip bad blocks
  "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.

Miscellaneous and testing commands:
  "markbad [offset]"
  create an artificial bad block (for testing bad block handling)

  "scrub [offset length]"
  like "erase" but don't skip bad block. Instead erase them.
  DANGEROUS!!! Factory set bad blocks will be lost. Use only
  to remove artificial bad blocks created with the "markbad" command.


NAND locking command (for chips with active LOCKPRE pin)

  "nand lock"
  set NAND chip to lock state (all pages locked)

  "nand lock tight"
  set NAND chip to lock tight state (software can't change locking anymore)

  "nand lock status"
  displays current locking status of all pages

  "nand unlock [offset] [size]"
  unlock consecutive area (can be called multiple times for different areas)


I have tested the code with board containing 128MiB NAND large page chips
and 32MiB small page chips.
Commit	Line	Data
7a8e9bed WD	1	NAND FLASH commands and notes
7a8e9bed WD	2
4e3ccd26 WD	3	See NOTE below!!!
4e3ccd26 WD	4
7a8e9bed WD	5	# (C) Copyright 2003
	6	# Dave Ellis, SIXNET, dge@sixnetio.com
	7	#
	8	# See file CREDITS for list of people who contributed to this
	9	# project.
	10	#
	11	# This program is free software; you can redistribute it and/or
	12	# modify it under the terms of the GNU General Public License as
	13	# published by the Free Software Foundation; either version 2 of
	14	# the License, or (at your option) any later version.
	15	#
	16	# This program is distributed in the hope that it will be useful,
	17	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	# GNU General Public License for more details.
	20	#
	21	# You should have received a copy of the GNU General Public License
	22	# along with this program; if not, write to the Free Software
	23	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	# MA 02111-1307 USA
	25
	26	Commands:
	27
	28	nand bad
	29	Print a list of all of the bad blocks in the current device.
	30
	31	nand device
	32	Print information about the current NAND device.
	33
	34	nand device num
	35	Make device `num' the current device and print information about it.
	36
856f0544 SR	37	nand erase off\|partition size
	38	nand erase clean [off\|partition size]
	39	Erase `size' bytes starting at offset `off'. Alternatively partition
	40	name can be specified, in this case size will be eventually limited
	41	to not exceed partition size (this behaviour applies also to read
	42	and write commands). Only complete erase blocks can be erased.
	43
	44	If `erase' is specified without an offset or size, the entire flash
	45	is erased. If `erase' is specified with partition but without an
	46	size, the entire partition is erased.
7a8e9bed WD	47
7a8e9bed WD	48	If `clean' is specified, a JFFS2-style clean marker is written to
856f0544	49	each block after it is erased.
7a8e9bed WD	50
	51	This command will not erase blocks that are marked bad. There is
	52	a debug option in cmd_nand.c to allow bad blocks to be erased.
	53	Please read the warning there before using it, as blocks marked
	54	bad by the manufacturer must _NEVER_ be erased.
	55
	56	nand info
	57	Print information about all of the NAND devices found.
	58
856f0544	59	nand read addr ofs\|partition size
984e03cd SW	60	Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
	61	are marked bad are skipped. If a page cannot be read because an
	62	uncorrectable data error is found, the command stops with an error.
7a8e9bed	63
856f0544	64	nand read.oob addr ofs\|partition size
7a8e9bed WD	65	Read `size' bytes from the out-of-band data area corresponding to
	66	`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
	67	data for one 512-byte page or 2 256-byte pages. There is no check
	68	for bad blocks or ECC errors.
	69
856f0544	70	nand write addr ofs\|partition size
984e03cd SW	71	Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
	72	are marked bad are skipped. If a page cannot be read because an
	73	uncorrectable data error is found, the command stops with an error.
	74
	75	As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
	76	as long as the image is short enough to fit even after skipping the
	77	bad blocks. Compact images, such as those produced by mkfs.jffs2
	78	should work well, but loading an image copied from another flash is
	79	going to be trouble if there are any bad blocks.
7a8e9bed	80
856f0544	81	nand write.oob addr ofs\|partition size
7a8e9bed WD	82	Write `size' bytes from `addr' to the out-of-band data area
	83	corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
	84	of data for one 512-byte page or 2 256-byte pages. There is no check
	85	for bad blocks.
	86
	87	Configuration Options:
	88
b5501f7d JL	89	CONFIG_CMD_NAND
b5501f7d JL	90	Enables NAND support and commmands.
7a8e9bed WD	91
	92	CONFIG_MTD_NAND_ECC_JFFS2
	93	Define this if you want the Error Correction Code information in
	94	the out-of-band data to be formatted to match the JFFS2 file system.
	95	CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
	96	someone to implement.
	97
	98	CFG_MAX_NAND_DEVICE
	99	The maximum number of NAND devices you want to support.
	100
	101	NAND Interface:
	102
	103	#define NAND_WAIT_READY(nand)
	104	Wait until the NAND flash is ready. Typically this would be a
	105	loop waiting for the READY/BUSY line from the flash to indicate it
	106	it is ready.
	107
	108	#define WRITE_NAND_COMMAND(d, adr)
	109	Write the command byte `d' to the flash at `adr' with the
	110	CLE (command latch enable) line true. If your board uses writes to
	111	different addresses to control CLE and ALE, you can modify `adr'
	112	to be the appropriate address here. If your board uses I/O registers
	113	to control them, it is probably better to let NAND_CTL_SETCLE()
	114	and company do it.
	115
	116	#define WRITE_NAND_ADDRESS(d, adr)
	117	Write the address byte `d' to the flash at `adr' with the
	118	ALE (address latch enable) line true. If your board uses writes to
	119	different addresses to control CLE and ALE, you can modify `adr'
	120	to be the appropriate address here. If your board uses I/O registers
	121	to control them, it is probably better to let NAND_CTL_SETALE()
	122	and company do it.
	123
	124	#define WRITE_NAND(d, adr)
	125	Write the data byte `d' to the flash at `adr' with the
	126	ALE and CLE lines false. If your board uses writes to
	127	different addresses to control CLE and ALE, you can modify `adr'
	128	to be the appropriate address here. If your board uses I/O registers
	129	to control them, it is probably better to let NAND_CTL_CLRALE()
	130	and company do it.
	131
	132	#define READ_NAND(adr)
	133	Read a data byte from the flash at `adr' with the
	134	ALE and CLE lines false. If your board uses reads from
	135	different addresses to control CLE and ALE, you can modify `adr'
	136	to be the appropriate address here. If your board uses I/O registers
	137	to control them, it is probably better to let NAND_CTL_CLRALE()
	138	and company do it.
	139
	140	#define NAND_DISABLE_CE(nand)
	141	Set CE (Chip Enable) low to enable the NAND flash.
	142
	143	#define NAND_ENABLE_CE(nand)
	144	Set CE (Chip Enable) high to disable the NAND flash.
	145
	146	#define NAND_CTL_CLRALE(nandptr)
	147	Set ALE (address latch enable) low. If ALE control is handled by
	148	WRITE_NAND_ADDRESS() this can be empty.
	149
	150	#define NAND_CTL_SETALE(nandptr)
	151	Set ALE (address latch enable) high. If ALE control is handled by
	152	WRITE_NAND_ADDRESS() this can be empty.
	153
	154	#define NAND_CTL_CLRCLE(nandptr)
155	Set CLE (command latch enable) low. If CLE control is handled by
156	WRITE_NAND_ADDRESS() this can be empty.
157
158	#define NAND_CTL_SETCLE(nandptr)
159	Set CLE (command latch enable) high. If CLE control is handled by
160	WRITE_NAND_ADDRESS() this can be empty.
8bde7f77	161
7a8e9bed WD	162	More Definitions:
	163
	164	These definitions are needed in the board configuration for now, but
	165	may really belong in a header file.
	166	TODO: Figure which ones are truly configuration settings and rename
8bde7f77	167	them to CFG_NAND_... and move the rest somewhere appropriate.
7a8e9bed WD	168
	169	#define SECTORSIZE 512
	170	#define ADDR_COLUMN 1
	171	#define ADDR_PAGE 2
	172	#define ADDR_COLUMN_PAGE 3
	173	#define NAND_ChipID_UNKNOWN 0x00
	174	#define NAND_MAX_FLOORS 1
	175	#define NAND_MAX_CHIPS 1
4e3ccd26 WD	176
4e3ccd26 WD	177
4e3ccd26 WD	178	NOTE:
	179	=====
	180
	181	We now use a complete rewrite of the NAND code based on what is in
	182	2.6.12 Linux kernel.
	183
	184	The old NAND handling code has been re-factored and is now confined
	185	to only board-specific files and - unfortunately - to the DoC code
	186	(see below). A new configuration variable has been introduced:
cc4a0cee	187	CONFIG_NAND_LEGACY, which has to be defined in the board config file if
323bfa8f	188	that board uses legacy code.
4e3ccd26 WD	189
	190	The necessary changes have been made to all affected boards, and no
	191	build breakage has been introduced, except for NETTA and NETTA_ISDN
	192	targets from MAKEALL. This is due to the fact that these two boards
	193	use JFFS, which has been adopted to use the new NAND, and at the same
	194	time use NAND in legacy mode. The breakage will disappear when the
	195	board-specific code is changed to the new NAND.
	196
bfc81252 WD	197	As mentioned above, the legacy code is still used by the DoC subsystem.
	198	The consequence of this is that the legacy NAND can't be removed from
	199	the tree until the DoC is ported to use the new NAND support (or boards
4e3ccd26	200	with DoC will break).
2255b2d2 SR	201
2255b2d2 SR	202
2255b2d2 SR	203	Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
	204
	205	JFFS2 related commands:
	206
	207	implement "nand erase clean" and old "nand erase"
	208	using both the new code which is able to skip bad blocks
	209	"nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
	210
2255b2d2 SR	211	Miscellaneous and testing commands:
	212	"markbad [offset]"
	213	create an artificial bad block (for testing bad block handling)
	214
	215	"scrub [offset length]"
	216	like "erase" but don't skip bad block. Instead erase them.
	217	DANGEROUS!!! Factory set bad blocks will be lost. Use only
	218	to remove artificial bad blocks created with the "markbad" command.
	219
	220
	221	NAND locking command (for chips with active LOCKPRE pin)
	222
	223	"nand lock"
	224	set NAND chip to lock state (all pages locked)
	225
	226	"nand lock tight"
	227	set NAND chip to lock tight state (software can't change locking anymore)
	228
	229	"nand lock status"
	230	displays current locking status of all pages
	231
	232	"nand unlock [offset] [size]"
	233	unlock consecutive area (can be called multiple times for different areas)
	234
	235
	236	I have tested the code with board containing 128MiB NAND large page chips
	237	and 32MiB small page chips.