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c5c1af21 CLS |
1 | |
2 | -------------------------------------------- | |
3 | SOCFPGA Documentation for U-Boot and SPL | |
4 | -------------------------------------------- | |
5 | ||
6 | This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore | |
7 | based SOCFPGA. To know more about the hardware itself, please refer to | |
8 | www.altera.com. | |
9 | ||
10 | ||
11 | -------------------------------------------- | |
12 | socfpga_dw_mmc | |
13 | -------------------------------------------- | |
14 | Here are macro and detailed configuration required to enable DesignWare SDMMC | |
15 | controller support within SOCFPGA | |
16 | ||
c5c1af21 CLS |
17 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 |
18 | -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM |