[people/ms/u-boot.git] / drivers / block / ahci.c

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006.
 * Author: Jason Jin<Jason.jin@freescale.com>
 *         Zhang Wei<wei.zhang@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * with the reference on libata and ahci drvier in kernel
 *
 */
#include <common.h>

#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <scsi.h>
#include <ata.h>
#include <linux/ctype.h>
#include <ahci.h>

struct ahci_probe_ent *probe_ent = NULL;
hd_driveid_t *ataid[AHCI_MAX_PORTS];

#define writel_with_flush(a,b)	do { writel(a,b); readl(b); } while (0)


static inline u32 ahci_port_base(u32 base, u32 port)
{
	return base + 0x100 + (port * 0x80);
}


static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
			    unsigned int port_idx)
{
	base = ahci_port_base(base, port_idx);

	port->cmd_addr = base;
	port->scr_addr = base + PORT_SCR;
}


#define msleep(a) udelay(a * 1000)
#define ssleep(a) msleep(a * 1000)

static int waiting_for_cmd_completed(volatile u8 *offset,
				     int timeout_msec,
				     u32 sign)
{
	int i;
	u32 status;

	for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
		msleep(1);

	return (i < timeout_msec) ? 0 : -1;
}


static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
	pci_dev_t pdev = probe_ent->dev;
	volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
	u32 tmp, cap_save;
	u16 tmp16;
	int i, j;
	volatile u8 *port_mmio;
	unsigned short vendor;

	cap_save = readl(mmio + HOST_CAP);
	cap_save &= ((1 << 28) | (1 << 17));
	cap_save |= (1 << 27);

	/* global controller reset */
	tmp = readl(mmio + HOST_CTL);
	if ((tmp & HOST_RESET) == 0)
		writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);

	/* reset must complete within 1 second, or
	 * the hardware should be considered fried.
	 */
	ssleep(1);

	tmp = readl(mmio + HOST_CTL);
	if (tmp & HOST_RESET) {
		debug("controller reset failed (0x%x)\n", tmp);
		return -1;
	}

	writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
	writel(cap_save, mmio + HOST_CAP);
	writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);

	pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);

	if (vendor == PCI_VENDOR_ID_INTEL) {
		u16 tmp16;
		pci_read_config_word(pdev, 0x92, &tmp16);
		tmp16 |= 0xf;
		pci_write_config_word(pdev, 0x92, tmp16);
	}

	probe_ent->cap = readl(mmio + HOST_CAP);
	probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
	probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;

	debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
	      probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);

	for (i = 0; i < probe_ent->n_ports; i++) {
		probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
		port_mmio = (u8 *) probe_ent->port[i].port_mmio;
		ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);

		/* make sure port is not active */
		tmp = readl(port_mmio + PORT_CMD);
		if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
			   PORT_CMD_FIS_RX | PORT_CMD_START)) {
			tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
				 PORT_CMD_FIS_RX | PORT_CMD_START);
			writel_with_flush(tmp, port_mmio + PORT_CMD);

			/* spec says 500 msecs for each bit, so
			 * this is slightly incorrect.
			 */
			msleep(500);
		}

		writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);

		j = 0;
		while (j < 100) {
			msleep(10);
			tmp = readl(port_mmio + PORT_SCR_STAT);
			if ((tmp & 0xf) == 0x3)
				break;
			j++;
		}

		tmp = readl(port_mmio + PORT_SCR_ERR);
		debug("PORT_SCR_ERR 0x%x\n", tmp);
		writel(tmp, port_mmio + PORT_SCR_ERR);

		/* ack any pending irq events for this port */
		tmp = readl(port_mmio + PORT_IRQ_STAT);
		debug("PORT_IRQ_STAT 0x%x\n", tmp);
		if (tmp)
			writel(tmp, port_mmio + PORT_IRQ_STAT);

		writel(1 << i, mmio + HOST_IRQ_STAT);

		/* set irq mask (enables interrupts) */
		writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);

		/*register linkup ports */
		tmp = readl(port_mmio + PORT_SCR_STAT);
		debug("Port %d status: 0x%x\n", i, tmp);
		if ((tmp & 0xf) == 0x03)
			probe_ent->link_port_map |= (0x01 << i);
	}

	tmp = readl(mmio + HOST_CTL);
	debug("HOST_CTL 0x%x\n", tmp);
	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
	tmp = readl(mmio + HOST_CTL);
	debug("HOST_CTL 0x%x\n", tmp);

	pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
	tmp |= PCI_COMMAND_MASTER;
	pci_write_config_word(pdev, PCI_COMMAND, tmp16);

	return 0;
}


static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
	pci_dev_t pdev = probe_ent->dev;
	volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
	u32 vers, cap, impl, speed;
	const char *speed_s;
	u16 cc;
	const char *scc_s;

	vers = readl(mmio + HOST_VERSION);
	cap = probe_ent->cap;
	impl = probe_ent->port_map;

	speed = (cap >> 20) & 0xf;
	if (speed == 1)
		speed_s = "1.5";
	else if (speed == 2)
		speed_s = "3";
	else
		speed_s = "?";

	pci_read_config_word(pdev, 0x0a, &cc);
	if (cc == 0x0101)
		scc_s = "IDE";
	else if (cc == 0x0106)
		scc_s = "SATA";
	else if (cc == 0x0104)
		scc_s = "RAID";
	else
		scc_s = "unknown";

	printf("AHCI %02x%02x.%02x%02x "
	       "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
	       (vers >> 24) & 0xff,
	       (vers >> 16) & 0xff,
	       (vers >> 8) & 0xff,
	       vers & 0xff,
	       ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);

	printf("flags: "
	       "%s%s%s%s%s%s"
	       "%s%s%s%s%s%s%s\n",
	       cap & (1 << 31) ? "64bit " : "",
	       cap & (1 << 30) ? "ncq " : "",
	       cap & (1 << 28) ? "ilck " : "",
	       cap & (1 << 27) ? "stag " : "",
	       cap & (1 << 26) ? "pm " : "",
	       cap & (1 << 25) ? "led " : "",
	       cap & (1 << 24) ? "clo " : "",
	       cap & (1 << 19) ? "nz " : "",
	       cap & (1 << 18) ? "only " : "",
	       cap & (1 << 17) ? "pmp " : "",
	       cap & (1 << 15) ? "pio " : "",
	       cap & (1 << 14) ? "slum " : "",
	       cap & (1 << 13) ? "part " : "");
}

static int ahci_init_one(pci_dev_t pdev)
{
	u16 vendor;
	int rc;

	memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);

	probe_ent = malloc(sizeof(struct ahci_probe_ent));
	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
	probe_ent->dev = pdev;

	probe_ent->host_flags = ATA_FLAG_SATA
				| ATA_FLAG_NO_LEGACY
				| ATA_FLAG_MMIO
				| ATA_FLAG_PIO_DMA
				| ATA_FLAG_NO_ATAPI;
	probe_ent->pio_mask = 0x1f;
	probe_ent->udma_mask = 0x7f;	/*Fixme,assume to support UDMA6 */

	probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
						PCI_REGION_MEM);

	/* Take from kernel:
	 * JMicron-specific fixup:
	 * make sure we're in AHCI mode
	 */
	pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
	if (vendor == 0x197b)
		pci_write_config_byte(pdev, 0x41, 0xa1);

	/* initialize adapter */
	rc = ahci_host_init(probe_ent);
	if (rc)
		goto err_out;

	ahci_print_info(probe_ent);

	return 0;

      err_out:
	return rc;
}


#define MAX_DATA_BYTE_COUNT  (4*1024*1024)

static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
{
	struct ahci_ioports *pp = &(probe_ent->port[port]);
	struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
	u32 sg_count;
	int i;

	sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
	if (sg_count > AHCI_MAX_SG) {
		printf("Error:Too much sg!\n");
		return -1;
	}

	for (i = 0; i < sg_count; i++) {
		ahci_sg->addr =
		    cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
		ahci_sg->addr_hi = 0;
		ahci_sg->flags_size = cpu_to_le32(0x3fffff &
					  (buf_len < MAX_DATA_BYTE_COUNT
					   ? (buf_len - 1)
					   : (MAX_DATA_BYTE_COUNT - 1)));
		ahci_sg++;
		buf_len -= MAX_DATA_BYTE_COUNT;
	}

	return sg_count;
}


static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
{
	pp->cmd_slot->opts = cpu_to_le32(opts);
	pp->cmd_slot->status = 0;
	pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
	pp->cmd_slot->tbl_addr_hi = 0;
}


static void ahci_set_feature(u8 port)
{
	struct ahci_ioports *pp = &(probe_ent->port[port]);
	volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
	u32 cmd_fis_len = 5;	/* five dwords */
	u8 fis[20];

	/*set feature */
	memset(fis, 0, 20);
	fis[0] = 0x27;
	fis[1] = 1 << 7;
	fis[2] = ATA_CMD_SETF;
	fis[3] = SETFEATURES_XFER;
	fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;

	memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
	ahci_fill_cmd_slot(pp, cmd_fis_len);
	writel(1, port_mmio + PORT_CMD_ISSUE);
	readl(port_mmio + PORT_CMD_ISSUE);

	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
		printf("set feature error!\n");
	}
}


static int ahci_port_start(u8 port)
{
	struct ahci_ioports *pp = &(probe_ent->port[port]);
	volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
	u32 port_status;
	u32 mem;

	debug("Enter start port: %d\n", port);
	port_status = readl(port_mmio + PORT_SCR_STAT);
	debug("Port %d status: %x\n", port, port_status);
	if ((port_status & 0xf) != 0x03) {
		printf("No Link on this port!\n");
		return -1;
	}

	mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
	if (!mem) {
		free(pp);
		printf("No mem for table!\n");
		return -ENOMEM;
	}

	mem = (mem + 0x800) & (~0x7ff);	/* Aligned to 2048-bytes */
	memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);

	/*
	 * First item in chunk of DMA memory: 32-slot command table,
	 * 32 bytes each in size
	 */
	pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
	debug("cmd_slot = 0x%x\n", pp->cmd_slot);
	mem += (AHCI_CMD_SLOT_SZ + 224);

	/*
	 * Second item: Received-FIS area
	 */
	pp->rx_fis = mem;
	mem += AHCI_RX_FIS_SZ;

	/*
	 * Third item: data area for storing a single command
	 * and its scatter-gather table
	 */
	pp->cmd_tbl = mem;
	debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);

	mem += AHCI_CMD_TBL_HDR;
	pp->cmd_tbl_sg = (struct ahci_sg *)mem;

	writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);

	writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);

	writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
			  PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
			  PORT_CMD_START, port_mmio + PORT_CMD);

	debug("Exit start port %d\n", port);

	return 0;
}


static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
				int buf_len)
{

	struct ahci_ioports *pp = &(probe_ent->port[port]);
	volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
	u32 opts;
	u32 port_status;
	int sg_count;

	debug("Enter get_ahci_device_data: for port %d\n", port);

	if (port > probe_ent->n_ports) {
		printf("Invaild port number %d\n", port);
		return -1;
	}

	port_status = readl(port_mmio + PORT_SCR_STAT);
	if ((port_status & 0xf) != 0x03) {
		debug("No Link on port %d!\n", port);
		return -1;
	}

	memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);

	sg_count = ahci_fill_sg(port, buf, buf_len);
	opts = (fis_len >> 2) | (sg_count << 16);
	ahci_fill_cmd_slot(pp, opts);

	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);

	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
		printf("timeout exit!\n");
		return -1;
	}
	debug("get_ahci_device_data: %d byte transferred.\n",
	      pp->cmd_slot->status);

	return 0;
}


static char *ata_id_strcpy(u16 *target, u16 *src, int len)
{
	int i;
	for (i = 0; i < len / 2; i++)
		target[i] = le16_to_cpu(src[i]);
	return (char *)target;
}


static void dump_ataid(hd_driveid_t *ataid)
{
	debug("(49)ataid->capability = 0x%x\n", ataid->capability);
	debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
	debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
	debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
	debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
	debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
	debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
	debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
	debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
	debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
	debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
	debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
	debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
	debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
	debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
}


/*
 * SCSI INQUIRY command operation.
 */
static int ata_scsiop_inquiry(ccb *pccb)
{
	u8 hdr[] = {
		0,
		0,
		0x5,		/* claim SPC-3 version compatibility */
		2,
		95 - 4,
	};
	u8 fis[20];
	u8 *tmpid;
	u8 port;

	/* Clean ccb data buffer */
	memset(pccb->pdata, 0, pccb->datalen);

	memcpy(pccb->pdata, hdr, sizeof(hdr));

	if (pccb->datalen <= 35)
		return 0;

	memset(fis, 0, 20);
	/* Construct the FIS */
	fis[0] = 0x27;		/* Host to device FIS. */
	fis[1] = 1 << 7;	/* Command FIS. */
	fis[2] = ATA_CMD_IDENT;	/* Command byte. */

	/* Read id from sata */
	port = pccb->target;
	if (!(tmpid = malloc(sizeof(hd_driveid_t))))
		return -ENOMEM;

	if (get_ahci_device_data(port, (u8 *) & fis, 20,
				 tmpid, sizeof(hd_driveid_t))) {
		debug("scsi_ahci: SCSI inquiry command failure.\n");
		return -EIO;
	}

	if (ataid[port])
		free(ataid[port]);
	ataid[port] = (hd_driveid_t *) tmpid;

	memcpy(&pccb->pdata[8], "ATA     ", 8);
	ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
	ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);

	dump_ataid(ataid[port]);
	return 0;
}


/*
 * SCSI READ10 command operation.
 */
static int ata_scsiop_read10(ccb * pccb)
{
	u64 lba = 0;
	u32 len = 0;
	u8 fis[20];

	lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
	    | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
	len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);

	/* For 10-byte and 16-byte SCSI R/W commands, transfer
	 * length 0 means transfer 0 block of data.
	 * However, for ATA R/W commands, sector count 0 means
	 * 256 or 65536 sectors, not 0 sectors as in SCSI.
	 *
	 * WARNING: one or two older ATA drives treat 0 as 0...
	 */
	if (!len)
		return 0;
	memset(fis, 0, 20);

	/* Construct the FIS */
	fis[0] = 0x27;		/* Host to device FIS. */
	fis[1] = 1 << 7;	/* Command FIS. */
	fis[2] = ATA_CMD_RD_DMA;	/* Command byte. */

	/* LBA address, only support LBA28 in this driver */
	fis[4] = pccb->cmd[5];
	fis[5] = pccb->cmd[4];
	fis[6] = pccb->cmd[3];
	fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;

	/* Sector Count */
	fis[12] = pccb->cmd[8];
	fis[13] = pccb->cmd[7];

	/* Read from ahci */
	if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
				 pccb->pdata, pccb->datalen)) {
		debug("scsi_ahci: SCSI READ10 command failure.\n");
		return -EIO;
	}

	return 0;
}


/*
 * SCSI READ CAPACITY10 command operation.
 */
static int ata_scsiop_read_capacity10(ccb *pccb)
{
	u32 cap;

	if (!ataid[pccb->target]) {
		printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
		       "\tNo ATA info!\n"
		       "\tPlease run SCSI commmand INQUIRY firstly!\n");
		return -EPERM;
	}

	cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
	memcpy(pccb->pdata, &cap, sizeof(cap));

	pccb->pdata[4] = pccb->pdata[5] = 0;
	pccb->pdata[6] = 512 >> 8;
	pccb->pdata[7] = 512 & 0xff;

	return 0;
}


/*
 * SCSI TEST UNIT READY command operation.
 */
static int ata_scsiop_test_unit_ready(ccb *pccb)
{
	return (ataid[pccb->target]) ? 0 : -EPERM;
}


int scsi_exec(ccb *pccb)
{
	int ret;

	switch (pccb->cmd[0]) {
	case SCSI_READ10:
		ret = ata_scsiop_read10(pccb);
		break;
	case SCSI_RD_CAPAC:
		ret = ata_scsiop_read_capacity10(pccb);
		break;
	case SCSI_TST_U_RDY:
		ret = ata_scsiop_test_unit_ready(pccb);
		break;
	case SCSI_INQUIRY:
		ret = ata_scsiop_inquiry(pccb);
		break;
	default:
		printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
		return FALSE;
	}

	if (ret) {
		debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
		return FALSE;
	}
	return TRUE;

}


void scsi_low_level_init(int busdevfunc)
{
	int i;
	u32 linkmap;

	ahci_init_one(busdevfunc);

	linkmap = probe_ent->link_port_map;

	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
		if (((linkmap >> i) & 0x01)) {
			if (ahci_port_start((u8) i)) {
				printf("Can not start port %d\n", i);
				continue;
			}
			ahci_set_feature((u8) i);
		}
	}
}


void scsi_bus_reset(void)
{
	/*Not implement*/
}


void scsi_print_error(ccb * pccb)
{
	/*The ahci error info can be read in the ahci driver*/
}
Commit	Line	Data
4782ac80	1	/*
4c2e3da8	2	* Copyright (C) Freescale Semiconductor, Inc. 2006.
4782ac80 JZ	3	* Author: Jason Jin<Jason.jin@freescale.com>
	4	* Zhang Wei<wei.zhang@freescale.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*
	24	* with the reference on libata and ahci drvier in kernel
	25	*
	26	*/
	27	#include <common.h>
	28
4782ac80 JZ	29	#include <command.h>
	30	#include <pci.h>
	31	#include <asm/processor.h>
	32	#include <asm/errno.h>
	33	#include <asm/io.h>
	34	#include <malloc.h>
	35	#include <scsi.h>
	36	#include <ata.h>
	37	#include <linux/ctype.h>
	38	#include <ahci.h>
	39
	40	struct ahci_probe_ent *probe_ent = NULL;
	41	hd_driveid_t *ataid[AHCI_MAX_PORTS];
	42
4a7cc0f2 JL	43	#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
4a7cc0f2 JL	44
4782ac80 JZ	45
	46	static inline u32 ahci_port_base(u32 base, u32 port)
	47	{
	48	return base + 0x100 + (port * 0x80);
	49	}
	50
	51
	52	static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
	53	unsigned int port_idx)
	54	{
	55	base = ahci_port_base(base, port_idx);
	56
4a7cc0f2 JL	57	port->cmd_addr = base;
4a7cc0f2 JL	58	port->scr_addr = base + PORT_SCR;
4782ac80 JZ	59	}
	60
	61
	62	#define msleep(a) udelay(a * 1000)
	63	#define ssleep(a) msleep(a * 1000)
4a7cc0f2 JL	64
	65	static int waiting_for_cmd_completed(volatile u8 *offset,
	66	int timeout_msec,
	67	u32 sign)
4782ac80 JZ	68	{
	69	int i;
	70	u32 status;
4a7cc0f2 JL	71
4a7cc0f2 JL	72	for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
4782ac80 JZ	73	msleep(1);
4782ac80 JZ	74
4a7cc0f2	75	return (i < timeout_msec) ? 0 : -1;
4782ac80 JZ	76	}
	77
	78
	79	static int ahci_host_init(struct ahci_probe_ent *probe_ent)
	80	{
	81	pci_dev_t pdev = probe_ent->dev;
	82	volatile u8 mmio = (volatile u8 )probe_ent->mmio_base;
	83	u32 tmp, cap_save;
	84	u16 tmp16;
	85	int i, j;
4a7cc0f2	86	volatile u8 *port_mmio;
4782ac80 JZ	87	unsigned short vendor;
	88
	89	cap_save = readl(mmio + HOST_CAP);
4a7cc0f2	90	cap_save &= ((1 << 28) \| (1 << 17));
4782ac80 JZ	91	cap_save \|= (1 << 27);
	92
	93	/* global controller reset */
	94	tmp = readl(mmio + HOST_CTL);
	95	if ((tmp & HOST_RESET) == 0)
	96	writel_with_flush(tmp \| HOST_RESET, mmio + HOST_CTL);
	97
	98	/* reset must complete within 1 second, or
	99	* the hardware should be considered fried.
	100	*/
	101	ssleep(1);
	102
	103	tmp = readl(mmio + HOST_CTL);
	104	if (tmp & HOST_RESET) {
	105	debug("controller reset failed (0x%x)\n", tmp);
	106	return -1;
	107	}
	108
	109	writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
	110	writel(cap_save, mmio + HOST_CAP);
	111	writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
	112
	113	pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
	114
	115	if (vendor == PCI_VENDOR_ID_INTEL) {
	116	u16 tmp16;
	117	pci_read_config_word(pdev, 0x92, &tmp16);
	118	tmp16 \|= 0xf;
	119	pci_write_config_word(pdev, 0x92, tmp16);
	120	}
	121
	122	probe_ent->cap = readl(mmio + HOST_CAP);
	123	probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
	124	probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
	125
	126	debug("cap 0x%x port_map 0x%x n_ports %d\n",
4a7cc0f2	127	probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
4782ac80 JZ	128
4782ac80 JZ	129	for (i = 0; i < probe_ent->n_ports; i++) {
4a7cc0f2 JL	130	probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
	131	port_mmio = (u8 *) probe_ent->port[i].port_mmio;
	132	ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
4782ac80 JZ	133
	134	/* make sure port is not active */
	135	tmp = readl(port_mmio + PORT_CMD);
	136	if (tmp & (PORT_CMD_LIST_ON \| PORT_CMD_FIS_ON \|
	137	PORT_CMD_FIS_RX \| PORT_CMD_START)) {
	138	tmp &= ~(PORT_CMD_LIST_ON \| PORT_CMD_FIS_ON \|
	139	PORT_CMD_FIS_RX \| PORT_CMD_START);
	140	writel_with_flush(tmp, port_mmio + PORT_CMD);
	141
	142	/* spec says 500 msecs for each bit, so
	143	* this is slightly incorrect.
	144	*/
	145	msleep(500);
	146	}
	147
	148	writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
	149
	150	j = 0;
	151	while (j < 100) {
	152	msleep(10);
	153	tmp = readl(port_mmio + PORT_SCR_STAT);
	154	if ((tmp & 0xf) == 0x3)
	155	break;
	156	j++;
	157	}
	158
	159	tmp = readl(port_mmio + PORT_SCR_ERR);
	160	debug("PORT_SCR_ERR 0x%x\n", tmp);
	161	writel(tmp, port_mmio + PORT_SCR_ERR);
	162
	163	/* ack any pending irq events for this port */
	164	tmp = readl(port_mmio + PORT_IRQ_STAT);
	165	debug("PORT_IRQ_STAT 0x%x\n", tmp);
	166	if (tmp)
	167	writel(tmp, port_mmio + PORT_IRQ_STAT);
	168
	169	writel(1 << i, mmio + HOST_IRQ_STAT);
	170
	171	/* set irq mask (enables interrupts) */
	172	writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
	173
4a7cc0f2	174	/register linkup ports /
4782ac80	175	tmp = readl(port_mmio + PORT_SCR_STAT);
4a7cc0f2 JL	176	debug("Port %d status: 0x%x\n", i, tmp);
	177	if ((tmp & 0xf) == 0x03)
	178	probe_ent->link_port_map \|= (0x01 << i);
4782ac80 JZ	179	}
	180
	181	tmp = readl(mmio + HOST_CTL);
	182	debug("HOST_CTL 0x%x\n", tmp);
	183	writel(tmp \| HOST_IRQ_EN, mmio + HOST_CTL);
	184	tmp = readl(mmio + HOST_CTL);
	185	debug("HOST_CTL 0x%x\n", tmp);
	186
	187	pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
	188	tmp \|= PCI_COMMAND_MASTER;
	189	pci_write_config_word(pdev, PCI_COMMAND, tmp16);
	190
	191	return 0;
	192	}
	193
	194
	195	static void ahci_print_info(struct ahci_probe_ent *probe_ent)
	196	{
	197	pci_dev_t pdev = probe_ent->dev;
4a7cc0f2	198	volatile u8 mmio = (volatile u8 )probe_ent->mmio_base;
4782ac80 JZ	199	u32 vers, cap, impl, speed;
	200	const char *speed_s;
	201	u16 cc;
	202	const char *scc_s;
	203
	204	vers = readl(mmio + HOST_VERSION);
	205	cap = probe_ent->cap;
	206	impl = probe_ent->port_map;
	207
	208	speed = (cap >> 20) & 0xf;
	209	if (speed == 1)
	210	speed_s = "1.5";
	211	else if (speed == 2)
	212	speed_s = "3";
	213	else
	214	speed_s = "?";
	215
	216	pci_read_config_word(pdev, 0x0a, &cc);
	217	if (cc == 0x0101)
	218	scc_s = "IDE";
	219	else if (cc == 0x0106)
	220	scc_s = "SATA";
	221	else if (cc == 0x0104)
	222	scc_s = "RAID";
	223	else
	224	scc_s = "unknown";
	225
4a7cc0f2 JL	226	printf("AHCI %02x%02x.%02x%02x "
	227	"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
	228	(vers >> 24) & 0xff,
	229	(vers >> 16) & 0xff,
	230	(vers >> 8) & 0xff,
	231	vers & 0xff,
	232	((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
4782ac80 JZ	233
4782ac80 JZ	234	printf("flags: "
4a7cc0f2 JL	235	"%s%s%s%s%s%s"
	236	"%s%s%s%s%s%s%s\n",
	237	cap & (1 << 31) ? "64bit " : "",
	238	cap & (1 << 30) ? "ncq " : "",
	239	cap & (1 << 28) ? "ilck " : "",
	240	cap & (1 << 27) ? "stag " : "",
	241	cap & (1 << 26) ? "pm " : "",
	242	cap & (1 << 25) ? "led " : "",
	243	cap & (1 << 24) ? "clo " : "",
	244	cap & (1 << 19) ? "nz " : "",
	245	cap & (1 << 18) ? "only " : "",
	246	cap & (1 << 17) ? "pmp " : "",
	247	cap & (1 << 15) ? "pio " : "",
	248	cap & (1 << 14) ? "slum " : "",
	249	cap & (1 << 13) ? "part " : "");
4782ac80 JZ	250	}
4782ac80 JZ	251
4a7cc0f2	252	static int ahci_init_one(pci_dev_t pdev)
4782ac80	253	{
63cec581	254	u16 vendor;
4782ac80 JZ	255	int rc;
4782ac80 JZ	256
4a7cc0f2	257	memset((void )ataid, 0, sizeof(hd_driveid_t ) * AHCI_MAX_PORTS);
4782ac80	258
594e7983 ES	259	probe_ent = malloc(sizeof(struct ahci_probe_ent));
594e7983 ES	260	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
4782ac80 JZ	261	probe_ent->dev = pdev;
4782ac80 JZ	262
4a7cc0f2 JL	263	probe_ent->host_flags = ATA_FLAG_SATA
	264	\| ATA_FLAG_NO_LEGACY
	265	\| ATA_FLAG_MMIO
	266	\| ATA_FLAG_PIO_DMA
	267	\| ATA_FLAG_NO_ATAPI;
	268	probe_ent->pio_mask = 0x1f;
	269	probe_ent->udma_mask = 0x7f; /Fixme,assume to support UDMA6 /
4782ac80	270
1785dbee BB	271	probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
1785dbee BB	272	PCI_REGION_MEM);
4782ac80 JZ	273
	274	/* Take from kernel:
	275	* JMicron-specific fixup:
	276	* make sure we're in AHCI mode
	277	*/
	278	pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
4a7cc0f2	279	if (vendor == 0x197b)
4782ac80 JZ	280	pci_write_config_byte(pdev, 0x41, 0xa1);
	281
	282	/* initialize adapter */
	283	rc = ahci_host_init(probe_ent);
	284	if (rc)
	285	goto err_out;
	286
	287	ahci_print_info(probe_ent);
	288
	289	return 0;
	290
4a7cc0f2	291	err_out:
4782ac80 JZ	292	return rc;
	293	}
	294
	295
	296	#define MAX_DATA_BYTE_COUNT (410241024)
4a7cc0f2	297
4782ac80 JZ	298	static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
4782ac80 JZ	299	{
4782ac80 JZ	300	struct ahci_ioports *pp = &(probe_ent->port[port]);
	301	struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
	302	u32 sg_count;
	303	int i;
	304
	305	sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
4a7cc0f2	306	if (sg_count > AHCI_MAX_SG) {
4782ac80 JZ	307	printf("Error:Too much sg!\n");
	308	return -1;
	309	}
	310
4a7cc0f2 JL	311	for (i = 0; i < sg_count; i++) {
	312	ahci_sg->addr =
	313	cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
4782ac80	314	ahci_sg->addr_hi = 0;
4a7cc0f2 JL	315	ahci_sg->flags_size = cpu_to_le32(0x3fffff &
	316	(buf_len < MAX_DATA_BYTE_COUNT
	317	? (buf_len - 1)
	318	: (MAX_DATA_BYTE_COUNT - 1)));
4782ac80 JZ	319	ahci_sg++;
	320	buf_len -= MAX_DATA_BYTE_COUNT;
	321	}
	322
	323	return sg_count;
	324	}
	325
	326
	327	static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
	328	{
	329	pp->cmd_slot->opts = cpu_to_le32(opts);
	330	pp->cmd_slot->status = 0;
	331	pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
	332	pp->cmd_slot->tbl_addr_hi = 0;
	333	}
	334
	335
	336	static void ahci_set_feature(u8 port)
	337	{
4782ac80	338	struct ahci_ioports *pp = &(probe_ent->port[port]);
4a7cc0f2 JL	339	volatile u8 port_mmio = (volatile u8 )pp->port_mmio;
4a7cc0f2 JL	340	u32 cmd_fis_len = 5; /* five dwords */
4782ac80 JZ	341	u8 fis[20];
4782ac80 JZ	342
4a7cc0f2 JL	343	/set feature /
4a7cc0f2 JL	344	memset(fis, 0, 20);
4782ac80 JZ	345	fis[0] = 0x27;
	346	fis[1] = 1 << 7;
	347	fis[2] = ATA_CMD_SETF;
	348	fis[3] = SETFEATURES_XFER;
	349	fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
	350
4a7cc0f2	351	memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
4782ac80 JZ	352	ahci_fill_cmd_slot(pp, cmd_fis_len);
	353	writel(1, port_mmio + PORT_CMD_ISSUE);
	354	readl(port_mmio + PORT_CMD_ISSUE);
	355
4a7cc0f2	356	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
4782ac80 JZ	357	printf("set feature error!\n");
	358	}
	359	}
	360
	361
	362	static int ahci_port_start(u8 port)
	363	{
4782ac80	364	struct ahci_ioports *pp = &(probe_ent->port[port]);
4a7cc0f2	365	volatile u8 port_mmio = (volatile u8 )pp->port_mmio;
4782ac80 JZ	366	u32 port_status;
	367	u32 mem;
	368
4a7cc0f2	369	debug("Enter start port: %d\n", port);
4782ac80	370	port_status = readl(port_mmio + PORT_SCR_STAT);
4a7cc0f2 JL	371	debug("Port %d status: %x\n", port, port_status);
4a7cc0f2 JL	372	if ((port_status & 0xf) != 0x03) {
4782ac80 JZ	373	printf("No Link on this port!\n");
	374	return -1;
	375	}
	376
4a7cc0f2	377	mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
4782ac80 JZ	378	if (!mem) {
	379	free(pp);
	380	printf("No mem for table!\n");
	381	return -ENOMEM;
	382	}
	383
4a7cc0f2 JL	384	mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
4a7cc0f2 JL	385	memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
4782ac80	386
4782ac80 JZ	387	/*
	388	* First item in chunk of DMA memory: 32-slot command table,
	389	* 32 bytes each in size
	390	*/
	391	pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
4a7cc0f2	392	debug("cmd_slot = 0x%x\n", pp->cmd_slot);
4782ac80	393	mem += (AHCI_CMD_SLOT_SZ + 224);
4a7cc0f2	394
4782ac80 JZ	395	/*
	396	* Second item: Received-FIS area
	397	*/
	398	pp->rx_fis = mem;
4782ac80	399	mem += AHCI_RX_FIS_SZ;
4a7cc0f2	400
4782ac80 JZ	401	/*
	402	* Third item: data area for storing a single command
	403	* and its scatter-gather table
	404	*/
	405	pp->cmd_tbl = mem;
4a7cc0f2	406	debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
4782ac80 JZ	407
	408	mem += AHCI_CMD_TBL_HDR;
	409	pp->cmd_tbl_sg = (struct ahci_sg *)mem;
	410
4a7cc0f2	411	writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
4782ac80 JZ	412
	413	writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
	414
	415	writel_with_flush(PORT_CMD_ICC_ACTIVE \| PORT_CMD_FIS_RX \|
4a7cc0f2 JL	416	PORT_CMD_POWER_ON \| PORT_CMD_SPIN_UP \|
4a7cc0f2 JL	417	PORT_CMD_START, port_mmio + PORT_CMD);
4782ac80	418
4a7cc0f2	419	debug("Exit start port %d\n", port);
4782ac80 JZ	420
	421	return 0;
	422	}
	423
	424
4a7cc0f2 JL	425	static int get_ahci_device_data(u8 port, u8 fis, int fis_len, u8 buf,
4a7cc0f2 JL	426	int buf_len)
4782ac80 JZ	427	{
4782ac80 JZ	428
4a7cc0f2 JL	429	struct ahci_ioports *pp = &(probe_ent->port[port]);
4a7cc0f2 JL	430	volatile u8 port_mmio = (volatile u8 )pp->port_mmio;
4782ac80 JZ	431	u32 opts;
	432	u32 port_status;
	433	int sg_count;
	434
4a7cc0f2	435	debug("Enter get_ahci_device_data: for port %d\n", port);
4782ac80	436
4a7cc0f2	437	if (port > probe_ent->n_ports) {
4782ac80 JZ	438	printf("Invaild port number %d\n", port);
	439	return -1;
	440	}
	441
	442	port_status = readl(port_mmio + PORT_SCR_STAT);
4a7cc0f2 JL	443	if ((port_status & 0xf) != 0x03) {
4a7cc0f2 JL	444	debug("No Link on port %d!\n", port);
4782ac80 JZ	445	return -1;
	446	}
	447
	448	memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
	449
4a7cc0f2 JL	450	sg_count = ahci_fill_sg(port, buf, buf_len);
4a7cc0f2 JL	451	opts = (fis_len >> 2) \| (sg_count << 16);
4782ac80 JZ	452	ahci_fill_cmd_slot(pp, opts);
	453
	454	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
	455
	456	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
	457	printf("timeout exit!\n");
	458	return -1;
	459	}
	460	debug("get_ahci_device_data: %d byte transferred.\n",
4a7cc0f2	461	pp->cmd_slot->status);
4782ac80 JZ	462
	463	return 0;
	464	}
	465
	466
	467	static char ata_id_strcpy(u16 target, u16 *src, int len)
	468	{
	469	int i;
4a7cc0f2	470	for (i = 0; i < len / 2; i++)
4782ac80 JZ	471	target[i] = le16_to_cpu(src[i]);
	472	return (char *)target;
	473	}
	474
	475
	476	static void dump_ataid(hd_driveid_t *ataid)
	477	{
	478	debug("(49)ataid->capability = 0x%x\n", ataid->capability);
	479	debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
	480	debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
	481	debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
	482	debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
	483	debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
	484	debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
	485	debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
	486	debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
	487	debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
	488	debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
	489	debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
	490	debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
	491	debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
	492	debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
	493	}
	494
4a7cc0f2	495
4782ac80 JZ	496	/*
	497	* SCSI INQUIRY command operation.
	498	*/
	499	static int ata_scsiop_inquiry(ccb *pccb)
	500	{
	501	u8 hdr[] = {
	502	0,
	503	0,
4a7cc0f2	504	0x5, /* claim SPC-3 version compatibility */
4782ac80 JZ	505	2,
	506	95 - 4,
	507	};
	508	u8 fis[20];
	509	u8 *tmpid;
	510	u8 port;
	511
	512	/* Clean ccb data buffer */
	513	memset(pccb->pdata, 0, pccb->datalen);
	514
	515	memcpy(pccb->pdata, hdr, sizeof(hdr));
	516
4a7cc0f2	517	if (pccb->datalen <= 35)
4782ac80 JZ	518	return 0;
	519
	520	memset(fis, 0, 20);
	521	/* Construct the FIS */
4a7cc0f2 JL	522	fis[0] = 0x27; /* Host to device FIS. */
	523	fis[1] = 1 << 7; /* Command FIS. */
	524	fis[2] = ATA_CMD_IDENT; /* Command byte. */
4782ac80 JZ	525
	526	/* Read id from sata */
	527	port = pccb->target;
4a7cc0f2	528	if (!(tmpid = malloc(sizeof(hd_driveid_t))))
4782ac80 JZ	529	return -ENOMEM;
4782ac80 JZ	530
4a7cc0f2 JL	531	if (get_ahci_device_data(port, (u8 *) & fis, 20,
4a7cc0f2 JL	532	tmpid, sizeof(hd_driveid_t))) {
4782ac80 JZ	533	debug("scsi_ahci: SCSI inquiry command failure.\n");
	534	return -EIO;
	535	}
	536
4a7cc0f2	537	if (ataid[port])
4782ac80	538	free(ataid[port]);
4a7cc0f2	539	ataid[port] = (hd_driveid_t *) tmpid;
4782ac80 JZ	540
4782ac80 JZ	541	memcpy(&pccb->pdata[8], "ATA ", 8);
4a7cc0f2 JL	542	ata_id_strcpy((u16 ) &pccb->pdata[16], (u16 )ataid[port]->model, 16);
4a7cc0f2 JL	543	ata_id_strcpy((u16 ) &pccb->pdata[32], (u16 )ataid[port]->fw_rev, 4);
4782ac80 JZ	544
	545	dump_ataid(ataid[port]);
	546	return 0;
	547	}
	548
	549
	550	/*
	551	* SCSI READ10 command operation.
	552	*/
4a7cc0f2	553	static int ata_scsiop_read10(ccb * pccb)
4782ac80 JZ	554	{
	555	u64 lba = 0;
	556	u32 len = 0;
	557	u8 fis[20];
	558
4a7cc0f2 JL	559	lba = (((u64) pccb->cmd[2]) << 24) \| (((u64) pccb->cmd[3]) << 16)
	560	\| (((u64) pccb->cmd[4]) << 8) \| ((u64) pccb->cmd[5]);
	561	len = (((u32) pccb->cmd[7]) << 8) \| ((u32) pccb->cmd[8]);
4782ac80 JZ	562
	563	/* For 10-byte and 16-byte SCSI R/W commands, transfer
	564	* length 0 means transfer 0 block of data.
	565	* However, for ATA R/W commands, sector count 0 means
	566	* 256 or 65536 sectors, not 0 sectors as in SCSI.
	567	*
	568	* WARNING: one or two older ATA drives treat 0 as 0...
	569	*/
4a7cc0f2 JL	570	if (!len)
4a7cc0f2 JL	571	return 0;
4782ac80 JZ	572	memset(fis, 0, 20);
	573
	574	/* Construct the FIS */
4a7cc0f2 JL	575	fis[0] = 0x27; /* Host to device FIS. */
4a7cc0f2 JL	576	fis[1] = 1 << 7; /* Command FIS. */
4782ac80 JZ	577	fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
4782ac80 JZ	578
4a7cc0f2	579	/* LBA address, only support LBA28 in this driver */
4782ac80 JZ	580	fis[4] = pccb->cmd[5];
	581	fis[5] = pccb->cmd[4];
	582	fis[6] = pccb->cmd[3];
	583	fis[7] = (pccb->cmd[2] & 0x0f) \| 0xe0;
	584
	585	/* Sector Count */
	586	fis[12] = pccb->cmd[8];
	587	fis[13] = pccb->cmd[7];
	588
	589	/* Read from ahci */
4a7cc0f2 JL	590	if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
4a7cc0f2 JL	591	pccb->pdata, pccb->datalen)) {
4782ac80 JZ	592	debug("scsi_ahci: SCSI READ10 command failure.\n");
	593	return -EIO;
	594	}
	595
	596	return 0;
	597	}
	598
	599
	600	/*
	601	* SCSI READ CAPACITY10 command operation.
	602	*/
	603	static int ata_scsiop_read_capacity10(ccb *pccb)
	604	{
cb6d0b72	605	u32 cap;
4782ac80	606
4a7cc0f2	607	if (!ataid[pccb->target]) {
4782ac80	608	printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
4a7cc0f2 JL	609	"\tNo ATA info!\n"
4a7cc0f2 JL	610	"\tPlease run SCSI commmand INQUIRY firstly!\n");
4782ac80 JZ	611	return -EPERM;
	612	}
	613
cb6d0b72 KG	614	cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
cb6d0b72 KG	615	memcpy(pccb->pdata, &cap, sizeof(cap));
4782ac80	616
cb6d0b72 KG	617	pccb->pdata[4] = pccb->pdata[5] = 0;
	618	pccb->pdata[6] = 512 >> 8;
	619	pccb->pdata[7] = 512 & 0xff;
4782ac80 JZ	620
	621	return 0;
	622	}
	623
	624
	625	/*
	626	* SCSI TEST UNIT READY command operation.
	627	*/
	628	static int ata_scsiop_test_unit_ready(ccb *pccb)
	629	{
	630	return (ataid[pccb->target]) ? 0 : -EPERM;
	631	}
	632
4a7cc0f2	633
4782ac80 JZ	634	int scsi_exec(ccb *pccb)
	635	{
	636	int ret;
	637
4a7cc0f2	638	switch (pccb->cmd[0]) {
4782ac80 JZ	639	case SCSI_READ10:
	640	ret = ata_scsiop_read10(pccb);
	641	break;
	642	case SCSI_RD_CAPAC:
	643	ret = ata_scsiop_read_capacity10(pccb);
	644	break;
	645	case SCSI_TST_U_RDY:
	646	ret = ata_scsiop_test_unit_ready(pccb);
	647	break;
	648	case SCSI_INQUIRY:
	649	ret = ata_scsiop_inquiry(pccb);
	650	break;
	651	default:
	652	printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
	653	return FALSE;
	654	}
	655
4a7cc0f2 JL	656	if (ret) {
4a7cc0f2 JL	657	debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
4782ac80 JZ	658	return FALSE;
	659	}
	660	return TRUE;
	661
	662	}
	663
	664
	665	void scsi_low_level_init(int busdevfunc)
	666	{
	667	int i;
	668	u32 linkmap;
	669
	670	ahci_init_one(busdevfunc);
	671
	672	linkmap = probe_ent->link_port_map;
	673
6d0f6bcf	674	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
4a7cc0f2 JL	675	if (((linkmap >> i) & 0x01)) {
	676	if (ahci_port_start((u8) i)) {
	677	printf("Can not start port %d\n", i);
4782ac80 JZ	678	continue;
4782ac80 JZ	679	}
4a7cc0f2	680	ahci_set_feature((u8) i);
4782ac80 JZ	681	}
	682	}
	683	}
	684
	685
	686	void scsi_bus_reset(void)
	687	{
4a7cc0f2	688	/Not implement/
4782ac80 JZ	689	}
	690
	691
4a7cc0f2	692	void scsi_print_error(ccb * pccb)
4782ac80	693	{
4a7cc0f2	694	/The ahci error info can be read in the ahci driver/
4782ac80	695	}