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[people/ms/u-boot.git] / drivers / block / dwc_ahsata.c
CommitLineData
9f472e65
SB		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
9f472e65
SB		 6 */
7
8#include <libata.h>
9#include <ahci.h>
10#include <fis.h>
e46a4350 11#include <sata.h>
9f472e65
SB		 12
13#include <common.h>
14#include <malloc.h>
15#include <linux/ctype.h>
16#include <asm/errno.h>
17#include <asm/io.h>
18#include <linux/bitops.h>
19#include <asm/arch/clock.h>
20#include "dwc_ahsata.h"
21
22struct sata_port_regs {
23 u32 clb;
24 u32 clbu;
25 u32 fb;
26 u32 fbu;
27 u32 is;
28 u32 ie;
29 u32 cmd;
30 u32 res1[1];
31 u32 tfd;
32 u32 sig;
33 u32 ssts;
34 u32 sctl;
35 u32 serr;
36 u32 sact;
37 u32 ci;
38 u32 sntf;
39 u32 res2[1];
40 u32 dmacr;
41 u32 res3[1];
42 u32 phycr;
43 u32 physr;
44};
45
46struct sata_host_regs {
47 u32 cap;
48 u32 ghc;
49 u32 is;
50 u32 pi;
51 u32 vs;
52 u32 ccc_ctl;
53 u32 ccc_ports;
54 u32 res1[2];
55 u32 cap2;
56 u32 res2[30];
57 u32 bistafr;
58 u32 bistcr;
59 u32 bistfctr;
60 u32 bistsr;
61 u32 bistdecr;
62 u32 res3[2];
63 u32 oobr;
64 u32 res4[8];
65 u32 timer1ms;
66 u32 res5[1];
67 u32 gparam1r;
68 u32 gparam2r;
69 u32 pparamr;
70 u32 testr;
71 u32 versionr;
72 u32 idr;
73};
74
75#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
76#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
77
78#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
79
80static int is_ready;
81
82static inline u32 ahci_port_base(u32 base, u32 port)
83{
84 return base + 0x100 + (port * 0x80);
85}
86
87static int waiting_for_cmd_completed(u8 *offset,
88 int timeout_msec,
89 u32 sign)
90{
91 int i;
92 u32 status;
93
94 for (i = 0;
95 ((status = readl(offset)) & sign) && i < timeout_msec;
96 ++i)
97 mdelay(1);
98
99 return (i < timeout_msec) ? 0 : -1;
100}
101
102static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
103 int clk)
104{
105 struct sata_host_regs *host_mmio =
106 (struct sata_host_regs *)probe_ent->mmio_base;
107
108 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
109 writel(0x02060b14, &(host_mmio->oobr));
110
111 return 0;
112}
113
114static int ahci_host_init(struct ahci_probe_ent *probe_ent)
115{
116 u32 tmp, cap_save, num_ports;
117 int i, j, timeout = 1000;
118 struct sata_port_regs *port_mmio = NULL;
119 struct sata_host_regs *host_mmio =
120 (struct sata_host_regs *)probe_ent->mmio_base;
121 int clk = mxc_get_clock(MXC_SATA_CLK);
122
123 cap_save = readl(&(host_mmio->cap));
124 cap_save |= SATA_HOST_CAP_SSS;
125
126 /* global controller reset */
127 tmp = readl(&(host_mmio->ghc));
128 if ((tmp & SATA_HOST_GHC_HR) == 0)
129 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
130
131 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
132 && --timeout)
133 ;
134
135 if (timeout <= 0) {
136 debug("controller reset failed (0x%x)\n", tmp);
137 return -1;
138 }
139
140 /* Set timer 1ms */
141 writel(clk / 1000, &(host_mmio->timer1ms));
142
143 ahci_setup_oobr(probe_ent, 0);
144
145 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
146 writel(cap_save, &(host_mmio->cap));
147 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
148 writel_with_flush((1 << num_ports) - 1,
149 &(host_mmio->pi));
150
151 /*
152 * Determine which Ports are implemented by the DWC_ahsata,
153 * by reading the PI register. This bit map value aids the
154 * software to determine how many Ports are available and
155 * which Port registers need to be initialized.
156 */
157 probe_ent->cap = readl(&(host_mmio->cap));
158 probe_ent->port_map = readl(&(host_mmio->pi));
159
160 /* Determine how many command slots the HBA supports */
161 probe_ent->n_ports =
162 (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
163
164 debug("cap 0x%x port_map 0x%x n_ports %d\n",
165 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
166
167 for (i = 0; i < probe_ent->n_ports; i++) {
168 probe_ent->port[i].port_mmio =
169 ahci_port_base((u32)host_mmio, i);
170 port_mmio =
171 (struct sata_port_regs *)probe_ent->port[i].port_mmio;
172
173 /* Ensure that the DWC_ahsata is in idle state */
174 tmp = readl(&(port_mmio->cmd));
175
176 /*
177 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
178 * are all cleared, the Port is in an idle state.
179 */
180 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
181 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
182
183 /*
184 * System software places a Port into the idle state by
185 * clearing P#CMD.ST and waiting for P#CMD.CR to return
186 * 0 when read.
187 */
188 tmp &= ~SATA_PORT_CMD_ST;
189 writel_with_flush(tmp, &(port_mmio->cmd));
190
191 /*
192 * spec says 500 msecs for each bit, so
193 * this is slightly incorrect.
194 */
195 mdelay(500);
196
197 timeout = 1000;
198 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
199 && --timeout)
200 ;
201
202 if (timeout <= 0) {
203 debug("port reset failed (0x%x)\n", tmp);
204 return -1;
205 }
206 }
207
208 /* Spin-up device */
209 tmp = readl(&(port_mmio->cmd));
210 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
211
212 /* Wait for spin-up to finish */
213 timeout = 1000;
214 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
215 && --timeout)
216 ;
217 if (timeout <= 0) {
218 debug("Spin-Up can't finish!\n");
219 return -1;
220 }
221
222 for (j = 0; j < 100; ++j) {
223 mdelay(10);
224 tmp = readl(&(port_mmio->ssts));
225 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
226 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
227 break;
228 }
229
230 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
231 timeout = 1000;
232 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
233 && --timeout)
234 ;
235 if (timeout <= 0) {
236 debug("Can't find DIAG_X set!\n");
237 return -1;
238 }
239
240 /*
241 * For each implemented Port, clear the P#SERR
242 * register, by writing ones to each implemented\
243 * bit location.
244 */
245 tmp = readl(&(port_mmio->serr));
246 debug("P#SERR 0x%x\n",
247 tmp);
248 writel(tmp, &(port_mmio->serr));
249
250 /* Ack any pending irq events for this port */
251 tmp = readl(&(host_mmio->is));
252 debug("IS 0x%x\n", tmp);
253 if (tmp)
254 writel(tmp, &(host_mmio->is));
255
256 writel(1 << i, &(host_mmio->is));
257
258 /* set irq mask (enables interrupts) */
259 writel(DEF_PORT_IRQ, &(port_mmio->ie));
260
261 /* register linkup ports */
262 tmp = readl(&(port_mmio->ssts));
263 debug("Port %d status: 0x%x\n", i, tmp);
264 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
265 probe_ent->link_port_map |= (0x01 << i);
266 }
267
268 tmp = readl(&(host_mmio->ghc));
269 debug("GHC 0x%x\n", tmp);
270 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
271 tmp = readl(&(host_mmio->ghc));
272 debug("GHC 0x%x\n", tmp);
273
274 return 0;
275}
276
277static void ahci_print_info(struct ahci_probe_ent *probe_ent)
278{
279 struct sata_host_regs *host_mmio =
280 (struct sata_host_regs *)probe_ent->mmio_base;
281 u32 vers, cap, impl, speed;
282 const char *speed_s;
283 const char *scc_s;
284
285 vers = readl(&(host_mmio->vs));
286 cap = probe_ent->cap;
287 impl = probe_ent->port_map;
288
289 speed = (cap & SATA_HOST_CAP_ISS_MASK)
290 >> SATA_HOST_CAP_ISS_OFFSET;
291 if (speed == 1)
292 speed_s = "1.5";
293 else if (speed == 2)
294 speed_s = "3";
295 else
296 speed_s = "?";
297
298 scc_s = "SATA";
299
300 printf("AHCI %02x%02x.%02x%02x "
301 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
302 (vers >> 24) & 0xff,
303 (vers >> 16) & 0xff,
304 (vers >> 8) & 0xff,
305 vers & 0xff,
306 ((cap >> 8) & 0x1f) + 1,
307 (cap & 0x1f) + 1,
308 speed_s,
309 impl,
310 scc_s);
311
312 printf("flags: "
313 "%s%s%s%s%s%s"
314 "%s%s%s%s%s%s%s\n",
315 cap & (1 << 31) ? "64bit " : "",
316 cap & (1 << 30) ? "ncq " : "",
317 cap & (1 << 28) ? "ilck " : "",
318 cap & (1 << 27) ? "stag " : "",
319 cap & (1 << 26) ? "pm " : "",
320 cap & (1 << 25) ? "led " : "",
321 cap & (1 << 24) ? "clo " : "",
322 cap & (1 << 19) ? "nz " : "",
323 cap & (1 << 18) ? "only " : "",
324 cap & (1 << 17) ? "pmp " : "",
325 cap & (1 << 15) ? "pio " : "",
326 cap & (1 << 14) ? "slum " : "",
327 cap & (1 << 13) ? "part " : "");
328}
329
330static int ahci_init_one(int pdev)
331{
332 int rc;
333 struct ahci_probe_ent *probe_ent = NULL;
334
335 probe_ent = malloc(sizeof(struct ahci_probe_ent));
336 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
337 probe_ent->dev = pdev;
338
339 probe_ent->host_flags = ATA_FLAG_SATA
340 | ATA_FLAG_NO_LEGACY
341 | ATA_FLAG_MMIO
342 | ATA_FLAG_PIO_DMA
343 | ATA_FLAG_NO_ATAPI;
344
345 probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
346
347 /* initialize adapter */
348 rc = ahci_host_init(probe_ent);
349 if (rc)
350 goto err_out;
351
352 ahci_print_info(probe_ent);
353
354 /* Save the private struct to block device struct */
355 sata_dev_desc[pdev].priv = (void *)probe_ent;
356
357 return 0;
358
359err_out:
360 return rc;
361}
362
363static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
364 u8 port, unsigned char *buf, int buf_len)
365{
366 struct ahci_ioports *pp = &(probe_ent->port[port]);
367 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
368 u32 sg_count, max_bytes;
369 int i;
370
371 max_bytes = MAX_DATA_BYTES_PER_SG;
372 sg_count = ((buf_len - 1) / max_bytes) + 1;
373 if (sg_count > AHCI_MAX_SG) {
374 printf("Error:Too much sg!\n");
375 return -1;
376 }
377
378 for (i = 0; i < sg_count; i++) {
379 ahci_sg->addr =
380 cpu_to_le32((u32)buf + i * max_bytes);
381 ahci_sg->addr_hi = 0;
382 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
383 (buf_len < max_bytes
384 ? (buf_len - 1)
385 : (max_bytes - 1)));
386 ahci_sg++;
387 buf_len -= max_bytes;
388 }
389
390 return sg_count;
391}
392
393static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
394{
395 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
396 AHCI_CMD_SLOT_SZ * cmd_slot);
397
398 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
399 cmd_hdr->opts = cpu_to_le32(opts);
400 cmd_hdr->status = 0;
401 cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
402 cmd_hdr->tbl_addr_hi = 0;
403}
404
405#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
406
407static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
408 u8 port, struct sata_fis_h2d *cfis,
409 u8 *buf, u32 buf_len, s32 is_write)
410{
411 struct ahci_ioports *pp = &(probe_ent->port[port]);
412 struct sata_port_regs *port_mmio =
413 (struct sata_port_regs *)pp->port_mmio;
414 u32 opts;
415 int sg_count = 0, cmd_slot = 0;
416
417 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
418 if (32 == cmd_slot) {
419 printf("Can't find empty command slot!\n");
420 return 0;
421 }
422
423 /* Check xfer length */
424 if (buf_len > MAX_BYTES_PER_TRANS) {
425 printf("Max transfer length is %dB\n\r",
426 MAX_BYTES_PER_TRANS);
427 return 0;
428 }
429
430 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
431 if (buf && buf_len)
432 sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
433 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
2dbe64ca 434 if (is_write) {
9f472e65 435 opts |= 0x40;
2dbe64ca
EN		 436 flush_cache((ulong)buf, buf_len);
437 }
9f472e65
SB		 438 ahci_fill_cmd_slot(pp, cmd_slot, opts);
439
2dbe64ca 440 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
9f472e65
SB		 441 writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
442
443 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
444 10000, 0x1 << cmd_slot)) {
445 printf("timeout exit!\n");
446 return -1;
447 }
2dbe64ca
EN		 448 invalidate_dcache_range((int)(pp->cmd_slot),
449 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
9f472e65
SB		 450 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
451 pp->cmd_slot->status);
2dbe64ca
EN		 452 if (!is_write)
453 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
9f472e65
SB		 454
455 return buf_len;
456}
457
458static void ahci_set_feature(u8 dev, u8 port)
459{
460 struct ahci_probe_ent *probe_ent =
461 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 462 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
463 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 464
465 memset(cfis, 0, sizeof(struct sata_fis_h2d));
466 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
467 cfis->pm_port_c = 1 << 7;
468 cfis->command = ATA_CMD_SET_FEATURES;
469 cfis->features = SETFEATURES_XFER;
470 cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
471
472 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
473}
474
475static int ahci_port_start(struct ahci_probe_ent *probe_ent,
476 u8 port)
477{
478 struct ahci_ioports *pp = &(probe_ent->port[port]);
479 struct sata_port_regs *port_mmio =
480 (struct sata_port_regs *)pp->port_mmio;
481 u32 port_status;
482 u32 mem;
483 int timeout = 10000000;
484
485 debug("Enter start port: %d\n", port);
486 port_status = readl(&(port_mmio->ssts));
487 debug("Port %d status: %x\n", port, port_status);
488 if ((port_status & 0xf) != 0x03) {
489 printf("No Link on this port!\n");
490 return -1;
491 }
492
493 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
494 if (!mem) {
495 free(pp);
496 printf("No mem for table!\n");
497 return -ENOMEM;
498 }
499
500 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
501 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
502
503 /*
504 * First item in chunk of DMA memory: 32-slot command table,
505 * 32 bytes each in size
506 */
507 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
508 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
509 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
510
511 /*
512 * Second item: Received-FIS area, 256-Byte aligned
513 */
514 pp->rx_fis = mem;
515 mem += AHCI_RX_FIS_SZ;
516
517 /*
518 * Third item: data area for storing a single command
519 * and its scatter-gather table
520 */
521 pp->cmd_tbl = mem;
522 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
523
524 mem += AHCI_CMD_TBL_HDR;
525
526 writel_with_flush(0x00004444, &(port_mmio->dmacr));
527 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
528 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
529 writel_with_flush(pp->rx_fis, &(port_mmio->fb));
530
531 /* Enable FRE */
532 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
533 &(port_mmio->cmd));
534
535 /* Wait device ready */
536 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
537 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
538 && --timeout)
539 ;
540 if (timeout <= 0) {
541 debug("Device not ready for BSY, DRQ and"
542 "ERR in TFD!\n");
543 return -1;
544 }
545
546 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
547 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
548 PORT_CMD_START, &(port_mmio->cmd));
549
550 debug("Exit start port %d\n", port);
551
552 return 0;
553}
554
555int init_sata(int dev)
556{
557 int i;
558 u32 linkmap;
559 struct ahci_probe_ent *probe_ent = NULL;
560
561 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
562 printf("The sata index %d is out of ranges\n\r", dev);
563 return -1;
564 }
565
566 ahci_init_one(dev);
567
568 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
569 linkmap = probe_ent->link_port_map;
570
571 if (0 == linkmap) {
572 printf("No port device detected!\n");
573 return 1;
574 }
575
576 for (i = 0; i < probe_ent->n_ports; i++) {
577 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
578 if (ahci_port_start(probe_ent, (u8)i)) {
579 printf("Can not start port %d\n", i);
580 return 1;
581 }
582 probe_ent->hard_port_no = i;
583 break;
584 }
585 }
586
587 return 0;
588}
589
590static void dwc_ahsata_print_info(int dev)
591{
592 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
593
594 printf("SATA Device Info:\n\r");
595#ifdef CONFIG_SYS_64BIT_LBA
596 printf("S/N: %s\n\rProduct model number: %s\n\r"
597 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
598 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
599#else
600 printf("S/N: %s\n\rProduct model number: %s\n\r"
601 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
602 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
603#endif
604}
605
606static void dwc_ahsata_identify(int dev, u16 *id)
607{
608 struct ahci_probe_ent *probe_ent =
609 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 610 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
611 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 612 u8 port = probe_ent->hard_port_no;
613
614 memset(cfis, 0, sizeof(struct sata_fis_h2d));
615
616 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
617 cfis->pm_port_c = 0x80; /* is command */
618 cfis->command = ATA_CMD_ID_ATA;
619
620 ahci_exec_ata_cmd(probe_ent, port, cfis,
621 (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
622 ata_swap_buf_le16(id, ATA_ID_WORDS);
623}
624
625static void dwc_ahsata_xfer_mode(int dev, u16 *id)
626{
627 struct ahci_probe_ent *probe_ent =
628 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
629
630 probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
631 probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
632 debug("pio %04x, udma %04x\n\r",
633 probe_ent->pio_mask, probe_ent->udma_mask);
634}
635
636static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
637 u8 *buffer, int is_write)
638{
639 struct ahci_probe_ent *probe_ent =
640 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 641 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
642 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 643 u8 port = probe_ent->hard_port_no;
644 u32 block;
645
646 block = start;
647
648 memset(cfis, 0, sizeof(struct sata_fis_h2d));
649
650 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
651 cfis->pm_port_c = 0x80; /* is command */
652 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
653 cfis->device = ATA_LBA;
654
655 cfis->device |= (block >> 24) & 0xf;
656 cfis->lba_high = (block >> 16) & 0xff;
657 cfis->lba_mid = (block >> 8) & 0xff;
658 cfis->lba_low = block & 0xff;
659 cfis->sector_count = (u8)(blkcnt & 0xff);
660
661 if (ahci_exec_ata_cmd(probe_ent, port, cfis,
662 buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
663 return blkcnt;
664 else
665 return 0;
666}
667
668void dwc_ahsata_flush_cache(int dev)
669{
670 struct ahci_probe_ent *probe_ent =
671 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 672 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
673 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 674 u8 port = probe_ent->hard_port_no;
675
676 memset(cfis, 0, sizeof(struct sata_fis_h2d));
677
678 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
679 cfis->pm_port_c = 0x80; /* is command */
680 cfis->command = ATA_CMD_FLUSH;
681
682 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
683}
684
685static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
686 u8 *buffer, int is_write)
687{
688 struct ahci_probe_ent *probe_ent =
689 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 690 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
691 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 692 u8 port = probe_ent->hard_port_no;
693 u64 block;
694
695 block = (u64)start;
696
697 memset(cfis, 0, sizeof(struct sata_fis_h2d));
698
699 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
700 cfis->pm_port_c = 0x80; /* is command */
701
702 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
703 : ATA_CMD_READ_EXT;
704
705 cfis->lba_high_exp = (block >> 40) & 0xff;
706 cfis->lba_mid_exp = (block >> 32) & 0xff;
707 cfis->lba_low_exp = (block >> 24) & 0xff;
708 cfis->lba_high = (block >> 16) & 0xff;
709 cfis->lba_mid = (block >> 8) & 0xff;
710 cfis->lba_low = block & 0xff;
711 cfis->device = ATA_LBA;
712 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
713 cfis->sector_count = blkcnt & 0xff;
714
715 if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
716 ATA_SECT_SIZE * blkcnt, is_write) > 0)
717 return blkcnt;
718 else
719 return 0;
720}
721
722u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
723 u8 *buffer, int is_write)
724{
725 struct ahci_probe_ent *probe_ent =
726 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 727 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
728 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 729 u8 port = probe_ent->hard_port_no;
730 u64 block;
731
732 if (sata_dev_desc[dev].lba48 != 1) {
733 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
734 return -1;
735 }
736
737 block = (u64)start;
738
739 memset(cfis, 0, sizeof(struct sata_fis_h2d));
740
741 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
742 cfis->pm_port_c = 0x80; /* is command */
743
744 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
745 : ATA_CMD_FPDMA_READ;
746
747 cfis->lba_high_exp = (block >> 40) & 0xff;
748 cfis->lba_mid_exp = (block >> 32) & 0xff;
749 cfis->lba_low_exp = (block >> 24) & 0xff;
750 cfis->lba_high = (block >> 16) & 0xff;
751 cfis->lba_mid = (block >> 8) & 0xff;
752 cfis->lba_low = block & 0xff;
753
754 cfis->device = ATA_LBA;
755 cfis->features_exp = (blkcnt >> 8) & 0xff;
756 cfis->features = blkcnt & 0xff;
757
758 /* Use the latest queue */
759 ahci_exec_ata_cmd(probe_ent, port, cfis,
760 buffer, ATA_SECT_SIZE * blkcnt, is_write);
761
762 return blkcnt;
763}
764
765void dwc_ahsata_flush_cache_ext(int dev)
766{
767 struct ahci_probe_ent *probe_ent =
768 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
2dbe64ca
EN		 769 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
770 struct sata_fis_h2d *cfis = &h2d;
9f472e65
SB		 771 u8 port = probe_ent->hard_port_no;
772
773 memset(cfis, 0, sizeof(struct sata_fis_h2d));
774
775 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
776 cfis->pm_port_c = 0x80; /* is command */
777 cfis->command = ATA_CMD_FLUSH_EXT;
778
779 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
780}
781
782static void dwc_ahsata_init_wcache(int dev, u16 *id)
783{
784 struct ahci_probe_ent *probe_ent =
785 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
786
787 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
788 probe_ent->flags |= SATA_FLAG_WCACHE;
789 if (ata_id_has_flush(id))
790 probe_ent->flags |= SATA_FLAG_FLUSH;
791 if (ata_id_has_flush_ext(id))
792 probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
793}
794
795u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
dac87571 796 const void *buffer, int is_write)
9f472e65
SB		 797{
798 u32 start, blks;
799 u8 *addr;
800 int max_blks;
801
802 start = blknr;
803 blks = blkcnt;
804 addr = (u8 *)buffer;
805
806 max_blks = ATA_MAX_SECTORS_LBA48;
807
808 do {
809 if (blks > max_blks) {
810 if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
811 max_blks, addr, is_write))
812 return 0;
813 start += max_blks;
814 blks -= max_blks;
815 addr += ATA_SECT_SIZE * max_blks;
816 } else {
817 if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
818 blks, addr, is_write))
819 return 0;
820 start += blks;
821 blks = 0;
822 addr += ATA_SECT_SIZE * blks;
823 }
824 } while (blks != 0);
825
826 return blkcnt;
827}
828
829u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
dac87571 830 const void *buffer, int is_write)
9f472e65
SB		 831{
832 u32 start, blks;
833 u8 *addr;
834 int max_blks;
835
836 start = blknr;
837 blks = blkcnt;
838 addr = (u8 *)buffer;
839
840 max_blks = ATA_MAX_SECTORS;
841 do {
842 if (blks > max_blks) {
843 if (max_blks != dwc_ahsata_rw_cmd(dev, start,
844 max_blks, addr, is_write))
845 return 0;
846 start += max_blks;
847 blks -= max_blks;
848 addr += ATA_SECT_SIZE * max_blks;
849 } else {
850 if (blks != dwc_ahsata_rw_cmd(dev, start,
851 blks, addr, is_write))
852 return 0;
853 start += blks;
854 blks = 0;
855 addr += ATA_SECT_SIZE * blks;
856 }
857 } while (blks != 0);
858
859 return blkcnt;
860}
861
862/*
863 * SATA interface between low level driver and command layer
864 */
dac87571 865ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
9f472e65
SB		 866{
867 u32 rc;
868
869 if (sata_dev_desc[dev].lba48)
870 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
871 buffer, READ_CMD);
872 else
873 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
874 buffer, READ_CMD);
875 return rc;
876}
877
dac87571 878ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
9f472e65
SB		 879{
880 u32 rc;
881 struct ahci_probe_ent *probe_ent =
882 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
883 u32 flags = probe_ent->flags;
884
885 if (sata_dev_desc[dev].lba48) {
886 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
887 buffer, WRITE_CMD);
888 if ((flags & SATA_FLAG_WCACHE) &&
889 (flags & SATA_FLAG_FLUSH_EXT))
890 dwc_ahsata_flush_cache_ext(dev);
891 } else {
892 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
893 buffer, WRITE_CMD);
894 if ((flags & SATA_FLAG_WCACHE) &&
895 (flags & SATA_FLAG_FLUSH))
896 dwc_ahsata_flush_cache(dev);
897 }
898 return rc;
899}
900
901int scan_sata(int dev)
902{
903 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
904 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
905 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
906 u16 *id;
907 u64 n_sectors;
908 struct ahci_probe_ent *probe_ent =
909 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
910 u8 port = probe_ent->hard_port_no;
911 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
912
2dbe64ca
EN		 913 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
914 roundup(ARCH_DMA_MINALIGN,
915 (ATA_ID_WORDS * 2)));
9f472e65
SB		 916 if (!id) {
917 printf("id malloc failed\n\r");
918 return -1;
919 }
920
921 /* Identify device to get information */
922 dwc_ahsata_identify(dev, id);
923
924 /* Serial number */
925 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
926 memcpy(pdev->product, serial, sizeof(serial));
927
928 /* Firmware version */
929 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
930 memcpy(pdev->revision, firmware, sizeof(firmware));
931
932 /* Product model */
933 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
934 memcpy(pdev->vendor, product, sizeof(product));
935
936 /* Totoal sectors */
937 n_sectors = ata_id_n_sectors(id);
938 pdev->lba = (u32)n_sectors;
939
940 pdev->type = DEV_TYPE_HARDDISK;
941 pdev->blksz = ATA_SECT_SIZE;
942 pdev->lun = 0 ;
943
944 /* Check if support LBA48 */
945 if (ata_id_has_lba48(id)) {
946 pdev->lba48 = 1;
947 debug("Device support LBA48\n\r");
948 }
949
950 /* Get the NCQ queue depth from device */
951 probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
952 probe_ent->flags |= ata_id_queue_depth(id);
953
954 /* Get the xfer mode from device */
955 dwc_ahsata_xfer_mode(dev, id);
956
957 /* Get the write cache status from device */
958 dwc_ahsata_init_wcache(dev, id);
959
960 /* Set the xfer mode to highest speed */
961 ahci_set_feature(dev, port);
962
963 free((void *)id);
964
965 dwc_ahsata_print_info(dev);
966
967 is_ready = 1;
968
969 return 0;
970}
"Das U-Boot" Source Tree