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3f85ce27 WD |
1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (XXXXXXXXXXXXXXXX) | |
4 | * | |
5 | * This source code is free software; you can redistribute it | |
6 | * and/or modify it in source code form under the terms of the GNU | |
7 | * General Public License as published by the Free Software | |
8 | * Foundation; either version 2 of the License, or (at your option) | |
9 | * any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA | |
19 | */ | |
3f85ce27 WD |
20 | |
21 | /* | |
22 | * The Xilinx SystemACE chip support is activated by defining | |
6d0f6bcf | 23 | * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE |
3f85ce27 WD |
24 | * to set the base address of the device. This code currently |
25 | * assumes that the chip is connected via a byte-wide bus. | |
26 | * | |
27 | * The CONFIG_SYSTEMACE also adds to fat support the device class | |
28 | * "ace" that allows the user to execute "fatls ace 0" and the | |
29 | * like. This works by making the systemace_get_dev function | |
30 | * available to cmd_fat.c:get_dev and filling in a block device | |
31 | * description that has all the bits needed for FAT support to | |
32 | * read sectors. | |
8f79e4c2 | 33 | * |
fe599e17 WD |
34 | * According to Xilinx technical support, before accessing the |
35 | * SystemACE CF you need to set the following control bits: | |
984618f3 GL |
36 | * FORCECFGMODE : 1 |
37 | * CFGMODE : 0 | |
38 | * CFGSTART : 0 | |
3f85ce27 WD |
39 | */ |
40 | ||
984618f3 GL |
41 | #include <common.h> |
42 | #include <command.h> | |
43 | #include <systemace.h> | |
44 | #include <part.h> | |
45 | #include <asm/io.h> | |
3f85ce27 | 46 | |
3f85ce27 WD |
47 | /* |
48 | * The ace_readw and writew functions read/write 16bit words, but the | |
49 | * offset value is the BYTE offset as most used in the Xilinx | |
6d0f6bcf | 50 | * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined |
3f85ce27 WD |
51 | * to be the base address for the chip, usually in the local |
52 | * peripheral bus. | |
53 | */ | |
5340a7f1 MS |
54 | |
55 | static u32 base = CONFIG_SYS_SYSTEMACE_BASE; | |
56 | static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; | |
57 | ||
58 | static void ace_writew(u16 val, unsigned off) | |
59 | { | |
60 | if (width == 8) { | |
a5bbcc3c | 61 | #if !defined(__BIG_ENDIAN) |
5340a7f1 MS |
62 | writeb(val >> 8, base + off); |
63 | writeb(val, base + off + 1); | |
a5bbcc3c | 64 | #else |
5340a7f1 MS |
65 | writeb(val, base + off); |
66 | writeb(val >> 8, base + off + 1); | |
a5bbcc3c | 67 | #endif |
7cde9f35 AB |
68 | } else |
69 | out16(base + off, val); | |
5340a7f1 MS |
70 | } |
71 | ||
72 | static u16 ace_readw(unsigned off) | |
73 | { | |
74 | if (width == 8) { | |
75 | #if !defined(__BIG_ENDIAN) | |
76 | return (readb(base + off) << 8) | readb(base + off + 1); | |
a5bbcc3c | 77 | #else |
5340a7f1 | 78 | return readb(base + off) | (readb(base + off + 1) << 8); |
a5bbcc3c | 79 | #endif |
5340a7f1 | 80 | } |
3f85ce27 | 81 | |
5340a7f1 MS |
82 | return in16(base + off); |
83 | } | |
3f85ce27 | 84 | |
984618f3 | 85 | static unsigned long systemace_read(int dev, unsigned long start, |
ac1048ae | 86 | lbaint_t blkcnt, void *buffer); |
3f85ce27 | 87 | |
984618f3 | 88 | static block_dev_desc_t systemace_dev = { 0 }; |
3f85ce27 WD |
89 | |
90 | static int get_cf_lock(void) | |
91 | { | |
984618f3 | 92 | int retry = 10; |
3f85ce27 WD |
93 | |
94 | /* CONTROLREG = LOCKREG */ | |
984618f3 GL |
95 | unsigned val = ace_readw(0x18); |
96 | val |= 0x0002; | |
97 | ace_writew((val & 0xffff), 0x18); | |
3f85ce27 WD |
98 | |
99 | /* Wait for MPULOCK in STATUSREG[15:0] */ | |
984618f3 | 100 | while (!(ace_readw(0x04) & 0x0002)) { |
3f85ce27 | 101 | |
984618f3 GL |
102 | if (retry < 0) |
103 | return -1; | |
3f85ce27 | 104 | |
984618f3 GL |
105 | udelay(100000); |
106 | retry -= 1; | |
107 | } | |
3f85ce27 | 108 | |
984618f3 | 109 | return 0; |
3f85ce27 WD |
110 | } |
111 | ||
112 | static void release_cf_lock(void) | |
113 | { | |
984618f3 GL |
114 | unsigned val = ace_readw(0x18); |
115 | val &= ~(0x0002); | |
116 | ace_writew((val & 0xffff), 0x18); | |
3f85ce27 WD |
117 | } |
118 | ||
df3fc526 | 119 | #ifdef CONFIG_PARTITIONS |
984618f3 | 120 | block_dev_desc_t *systemace_get_dev(int dev) |
3f85ce27 WD |
121 | { |
122 | /* The first time through this, the systemace_dev object is | |
123 | not yet initialized. In that case, fill it in. */ | |
984618f3 GL |
124 | if (systemace_dev.blksz == 0) { |
125 | systemace_dev.if_type = IF_TYPE_UNKNOWN; | |
126 | systemace_dev.dev = 0; | |
127 | systemace_dev.part_type = PART_TYPE_UNKNOWN; | |
128 | systemace_dev.type = DEV_TYPE_HARDDISK; | |
129 | systemace_dev.blksz = 512; | |
0472fbfd | 130 | systemace_dev.log2blksz = LOG2(systemace_dev.blksz); |
984618f3 GL |
131 | systemace_dev.removable = 1; |
132 | systemace_dev.block_read = systemace_read; | |
fe599e17 | 133 | |
d93e2212 | 134 | /* |
8274ec0b | 135 | * Ensure the correct bus mode (8/16 bits) gets enabled |
d93e2212 | 136 | */ |
5340a7f1 | 137 | ace_writew(width == 8 ? 0 : 0x0001, 0); |
d93e2212 | 138 | |
984618f3 | 139 | init_part(&systemace_dev); |
fe599e17 | 140 | |
984618f3 | 141 | } |
3f85ce27 | 142 | |
984618f3 | 143 | return &systemace_dev; |
3f85ce27 | 144 | } |
df3fc526 | 145 | #endif |
3f85ce27 WD |
146 | |
147 | /* | |
148 | * This function is called (by dereferencing the block_read pointer in | |
149 | * the dev_desc) to read blocks of data. The return value is the | |
150 | * number of blocks read. A zero return indicates an error. | |
151 | */ | |
984618f3 | 152 | static unsigned long systemace_read(int dev, unsigned long start, |
ac1048ae | 153 | lbaint_t blkcnt, void *buffer) |
3f85ce27 | 154 | { |
984618f3 GL |
155 | int retry; |
156 | unsigned blk_countdown; | |
eb867a76 | 157 | unsigned char *dp = buffer; |
984618f3 GL |
158 | unsigned val; |
159 | ||
160 | if (get_cf_lock() < 0) { | |
161 | unsigned status = ace_readw(0x04); | |
162 | ||
163 | /* If CFDETECT is false, card is missing. */ | |
164 | if (!(status & 0x0010)) { | |
165 | printf("** CompactFlash card not present. **\n"); | |
166 | return 0; | |
167 | } | |
168 | ||
169 | printf("**** ACE locked away from me (STATUSREG=%04x)\n", | |
170 | status); | |
171 | return 0; | |
172 | } | |
e7c85689 | 173 | #ifdef DEBUG_SYSTEMACE |
984618f3 | 174 | printf("... systemace read %lu sectors at %lu\n", blkcnt, start); |
e7c85689 WD |
175 | #endif |
176 | ||
984618f3 GL |
177 | retry = 2000; |
178 | for (;;) { | |
179 | val = ace_readw(0x04); | |
3f85ce27 | 180 | |
984618f3 GL |
181 | /* If CFDETECT is false, card is missing. */ |
182 | if (!(val & 0x0010)) { | |
183 | printf("**** ACE CompactFlash not found.\n"); | |
184 | release_cf_lock(); | |
185 | return 0; | |
186 | } | |
3f85ce27 | 187 | |
984618f3 GL |
188 | /* If RDYFORCMD, then we are ready to go. */ |
189 | if (val & 0x0100) | |
190 | break; | |
3f85ce27 | 191 | |
984618f3 GL |
192 | if (retry < 0) { |
193 | printf("**** SystemACE not ready.\n"); | |
194 | release_cf_lock(); | |
195 | return 0; | |
196 | } | |
3f85ce27 | 197 | |
984618f3 GL |
198 | udelay(1000); |
199 | retry -= 1; | |
200 | } | |
3f85ce27 | 201 | |
e7c85689 WD |
202 | /* The SystemACE can only transfer 256 sectors at a time, so |
203 | limit the current chunk of sectors. The blk_countdown | |
204 | variable is the number of sectors left to transfer. */ | |
3f85ce27 | 205 | |
984618f3 GL |
206 | blk_countdown = blkcnt; |
207 | while (blk_countdown > 0) { | |
208 | unsigned trans = blk_countdown; | |
3f85ce27 | 209 | |
984618f3 GL |
210 | if (trans > 256) |
211 | trans = 256; | |
3f85ce27 | 212 | |
e7c85689 | 213 | #ifdef DEBUG_SYSTEMACE |
984618f3 | 214 | printf("... transfer %lu sector in a chunk\n", trans); |
e7c85689 | 215 | #endif |
984618f3 GL |
216 | /* Write LBA block address */ |
217 | ace_writew((start >> 0) & 0xffff, 0x10); | |
d93e2212 | 218 | ace_writew((start >> 16) & 0x0fff, 0x12); |
984618f3 GL |
219 | |
220 | /* NOTE: in the Write Sector count below, a count of 0 | |
221 | causes a transfer of 256, so &0xff gives the right | |
222 | value for whatever transfer count we want. */ | |
223 | ||
224 | /* Write sector count | ReadMemCardData. */ | |
225 | ace_writew((trans & 0xff) | 0x0300, 0x14); | |
226 | ||
d62f64cc | 227 | /* |
32556443 MS |
228 | * For FPGA configuration via SystemACE is reset unacceptable |
229 | * CFGDONE bit in STATUSREG is not set to 1. | |
230 | */ | |
231 | #ifndef SYSTEMACE_CONFIG_FPGA | |
984618f3 GL |
232 | /* Reset the configruation controller */ |
233 | val = ace_readw(0x18); | |
234 | val |= 0x0080; | |
235 | ace_writew(val, 0x18); | |
32556443 | 236 | #endif |
984618f3 GL |
237 | |
238 | retry = trans * 16; | |
239 | while (retry > 0) { | |
240 | int idx; | |
241 | ||
242 | /* Wait for buffer to become ready. */ | |
243 | while (!(ace_readw(0x04) & 0x0020)) { | |
244 | udelay(100); | |
245 | } | |
246 | ||
247 | /* Read 16 words of 2bytes from the sector buffer. */ | |
248 | for (idx = 0; idx < 16; idx += 1) { | |
249 | unsigned short val = ace_readw(0x40); | |
250 | *dp++ = val & 0xff; | |
251 | *dp++ = (val >> 8) & 0xff; | |
252 | } | |
253 | ||
254 | retry -= 1; | |
255 | } | |
256 | ||
257 | /* Clear the configruation controller reset */ | |
258 | val = ace_readw(0x18); | |
259 | val &= ~0x0080; | |
260 | ace_writew(val, 0x18); | |
261 | ||
262 | /* Count the blocks we transfer this time. */ | |
263 | start += trans; | |
264 | blk_countdown -= trans; | |
265 | } | |
266 | ||
267 | release_cf_lock(); | |
268 | ||
269 | return blkcnt; | |
3f85ce27 | 270 | } |