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clk: add clk_release_all()
[people/ms/u-boot.git] / drivers / clk / clk-uclass.c
CommitLineData
f26c8a8e
SG
1/*
2 * Copyright (C) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
135aa950 4 * Copyright (c) 2016, NVIDIA CORPORATION.
f26c8a8e
SG
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <clk.h>
135aa950 11#include <clk-uclass.h>
f26c8a8e 12#include <dm.h>
7423daa6 13#include <dt-structs.h>
f26c8a8e 14#include <errno.h>
f26c8a8e 15
e70cc438
SG
16DECLARE_GLOBAL_DATA_PTR;
17
135aa950 18static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
f26c8a8e 19{
135aa950 20 return (struct clk_ops *)dev->driver->ops;
f26c8a8e
SG
21}
22
135aa950 23#if CONFIG_IS_ENABLED(OF_CONTROL)
7423daa6
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24# if CONFIG_IS_ENABLED(OF_PLATDATA)
25int clk_get_by_index_platdata(struct udevice *dev, int index,
26 struct phandle_2_cell *cells, struct clk *clk)
27{
28 int ret;
29
30 if (index != 0)
31 return -ENOSYS;
32 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
33 if (ret)
34 return ret;
35 clk->id = cells[0].id;
36
37 return 0;
38}
39# else
135aa950 40static int clk_of_xlate_default(struct clk *clk,
a4e0ef50 41 struct ofnode_phandle_args *args)
f26c8a8e 42{
135aa950 43 debug("%s(clk=%p)\n", __func__, clk);
f26c8a8e 44
135aa950
SW
45 if (args->args_count > 1) {
46 debug("Invaild args_count: %d\n", args->args_count);
47 return -EINVAL;
48 }
f26c8a8e 49
135aa950
SW
50 if (args->args_count)
51 clk->id = args->args[0];
52 else
53 clk->id = 0;
f26c8a8e 54
135aa950 55 return 0;
f26c8a8e
SG
56}
57
135aa950 58int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
e70cc438 59{
e70cc438 60 int ret;
aa9bb094 61 struct ofnode_phandle_args args;
135aa950
SW
62 struct udevice *dev_clk;
63 struct clk_ops *ops;
64
65 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
e70cc438 66
135aa950 67 assert(clk);
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PC
68 clk->dev = NULL;
69
aa9bb094
SG
70 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
71 index, &args);
e70cc438
SG
72 if (ret) {
73 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
74 __func__, ret);
75 return ret;
76 }
77
aa9bb094 78 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
e70cc438
SG
79 if (ret) {
80 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
81 __func__, ret);
82 return ret;
83 }
3f56b132
WY
84
85 clk->dev = dev_clk;
86
135aa950
SW
87 ops = clk_dev_ops(dev_clk);
88
89 if (ops->of_xlate)
aa9bb094 90 ret = ops->of_xlate(clk, &args);
135aa950 91 else
aa9bb094 92 ret = clk_of_xlate_default(clk, &args);
135aa950
SW
93 if (ret) {
94 debug("of_xlate() failed: %d\n", ret);
95 return ret;
96 }
97
98 return clk_request(dev_clk, clk);
99}
9e0758b7 100# endif /* OF_PLATDATA */
135aa950
SW
101
102int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
103{
104 int index;
105
106 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
82a8a669 107 clk->dev = NULL;
135aa950 108
aa9bb094 109 index = dev_read_stringlist_search(dev, "clock-names", name);
135aa950 110 if (index < 0) {
b02e4044 111 debug("fdt_stringlist_search() failed: %d\n", index);
135aa950
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112 return index;
113 }
114
115 return clk_get_by_index(dev, index, clk);
e70cc438 116}
7423daa6 117#endif /* OF_CONTROL */
135aa950
SW
118
119int clk_request(struct udevice *dev, struct clk *clk)
120{
121 struct clk_ops *ops = clk_dev_ops(dev);
122
123 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
124
125 clk->dev = dev;
126
127 if (!ops->request)
128 return 0;
129
130 return ops->request(clk);
131}
132
133int clk_free(struct clk *clk)
134{
135 struct clk_ops *ops = clk_dev_ops(clk->dev);
136
137 debug("%s(clk=%p)\n", __func__, clk);
138
139 if (!ops->free)
140 return 0;
141
142 return ops->free(clk);
143}
144
145ulong clk_get_rate(struct clk *clk)
146{
147 struct clk_ops *ops = clk_dev_ops(clk->dev);
148
149 debug("%s(clk=%p)\n", __func__, clk);
150
151 if (!ops->get_rate)
152 return -ENOSYS;
153
154 return ops->get_rate(clk);
155}
156
157ulong clk_set_rate(struct clk *clk, ulong rate)
158{
159 struct clk_ops *ops = clk_dev_ops(clk->dev);
160
161 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
162
163 if (!ops->set_rate)
164 return -ENOSYS;
165
166 return ops->set_rate(clk, rate);
167}
168
169int clk_enable(struct clk *clk)
170{
171 struct clk_ops *ops = clk_dev_ops(clk->dev);
172
173 debug("%s(clk=%p)\n", __func__, clk);
174
175 if (!ops->enable)
176 return -ENOSYS;
177
178 return ops->enable(clk);
179}
180
181int clk_disable(struct clk *clk)
182{
183 struct clk_ops *ops = clk_dev_ops(clk->dev);
184
185 debug("%s(clk=%p)\n", __func__, clk);
186
187 if (!ops->disable)
188 return -ENOSYS;
189
190 return ops->disable(clk);
191}
e70cc438 192
82a8a669
PC
193int clk_release_all(struct clk *clk, int count)
194{
195 int i, ret;
196
197 for (i = 0; i < count; i++) {
198 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
199
200 /* check if clock has been previously requested */
201 if (!clk[i].dev)
202 continue;
203
204 ret = clk_disable(&clk[i]);
205 if (ret && ret != -ENOSYS)
206 return ret;
207
208 ret = clk_free(&clk[i]);
209 if (ret && ret != -ENOSYS)
210 return ret;
211 }
212
213 return 0;
214}
215
f26c8a8e
SG
216UCLASS_DRIVER(clk) = {
217 .id = UCLASS_CLK,
218 .name = "clk",
219};