[people/ms/u-boot.git] / drivers / clk / clk-uclass.c

/*
 * Copyright (C) 2015 Google, Inc
 * Written by Simon Glass <sjg@chromium.org>
 * Copyright (c) 2016, NVIDIA CORPORATION.
 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dm/read.h>
#include <dt-structs.h>
#include <errno.h>

static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
	return (const struct clk_ops *)dev->driver->ops;
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
# if CONFIG_IS_ENABLED(OF_PLATDATA)
int clk_get_by_index_platdata(struct udevice *dev, int index,
			      struct phandle_1_arg *cells, struct clk *clk)
{
	int ret;

	if (index != 0)
		return -ENOSYS;
	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
	if (ret)
		return ret;
	clk->id = cells[0].arg[0];

	return 0;
}
# else
static int clk_of_xlate_default(struct clk *clk,
				struct ofnode_phandle_args *args)
{
	debug("%s(clk=%p)\n", __func__, clk);

	if (args->args_count > 1) {
		debug("Invaild args_count: %d\n", args->args_count);
		return -EINVAL;
	}

	if (args->args_count)
		clk->id = args->args[0];
	else
		clk->id = 0;

	return 0;
}

static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
				   int index, struct clk *clk)
{
	int ret;
	struct ofnode_phandle_args args;
	struct udevice *dev_clk;
	const struct clk_ops *ops;

	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);

	assert(clk);
	clk->dev = NULL;

	ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
					 index, &args);
	if (ret) {
		debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
		      __func__, ret);
		return ret;
	}

	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
	if (ret) {
		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
		      __func__, ret);
		return ret;
	}

	clk->dev = dev_clk;

	ops = clk_dev_ops(dev_clk);

	if (ops->of_xlate)
		ret = ops->of_xlate(clk, &args);
	else
		ret = clk_of_xlate_default(clk, &args);
	if (ret) {
		debug("of_xlate() failed: %d\n", ret);
		return ret;
	}

	return clk_request(dev_clk, clk);
}

int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
}

static int clk_set_default_parents(struct udevice *dev)
{
	struct clk clk, parent_clk;
	int index;
	int num_parents;
	int ret;

	num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
						  "#clock-cells");
	if (num_parents < 0) {
		debug("%s: could not read assigned-clock-parents for %p\n",
		      __func__, dev);
		return 0;
	}

	for (index = 0; index < num_parents; index++) {
		ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
					      index, &parent_clk);
		if (ret) {
			debug("%s: could not get parent clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			return ret;
		}

		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
					      index, &clk);
		if (ret) {
			debug("%s: could not get assigned clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			return ret;
		}

		ret = clk_set_parent(&clk, &parent_clk);

		/*
		 * Not all drivers may support clock-reparenting (as of now).
		 * Ignore errors due to this.
		 */
		if (ret == -ENOSYS)
			continue;

		if (ret) {
			debug("%s: failed to reparent clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			return ret;
		}
	}

	return 0;
}

static int clk_set_default_rates(struct udevice *dev)
{
	struct clk clk;
	int index;
	int num_rates;
	int size;
	int ret = 0;
	u32 *rates = NULL;

	size = dev_read_size(dev, "assigned-clock-rates");
	if (size < 0)
		return 0;

	num_rates = size / sizeof(u32);
	rates = calloc(num_rates, sizeof(u32));
	if (!rates)
		return -ENOMEM;

	ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
	if (ret)
		goto fail;

	for (index = 0; index < num_rates; index++) {
		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
					      index, &clk);
		if (ret) {
			debug("%s: could not get assigned clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			continue;
		}

		ret = clk_set_rate(&clk, rates[index]);
		if (ret < 0) {
			debug("%s: failed to set rate on clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			break;
		}
	}

fail:
	free(rates);
	return ret;
}

int clk_set_defaults(struct udevice *dev)
{
	int ret;

	/* If this is running pre-reloc state, don't take any action. */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	debug("%s(%s)\n", __func__, dev_read_name(dev));

	ret = clk_set_default_parents(dev);
	if (ret)
		return ret;

	ret = clk_set_default_rates(dev);
	if (ret < 0)
		return ret;

	return 0;
}
# endif /* OF_PLATDATA */

int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
	int index;

	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
	clk->dev = NULL;

	index = dev_read_stringlist_search(dev, "clock-names", name);
	if (index < 0) {
		debug("fdt_stringlist_search() failed: %d\n", index);
		return index;
	}

	return clk_get_by_index(dev, index, clk);
}

int clk_release_all(struct clk *clk, int count)
{
	int i, ret;

	for (i = 0; i < count; i++) {
		debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);

		/* check if clock has been previously requested */
		if (!clk[i].dev)
			continue;

		ret = clk_disable(&clk[i]);
		if (ret && ret != -ENOSYS)
			return ret;

		ret = clk_free(&clk[i]);
		if (ret && ret != -ENOSYS)
			return ret;
	}

	return 0;
}

#endif /* OF_CONTROL */

int clk_request(struct udevice *dev, struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(dev);

	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);

	clk->dev = dev;

	if (!ops->request)
		return 0;

	return ops->request(clk);
}

int clk_free(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->free)
		return 0;

	return ops->free(clk);
}

ulong clk_get_rate(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->get_rate)
		return -ENOSYS;

	return ops->get_rate(clk);
}

ulong clk_set_rate(struct clk *clk, ulong rate)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);

	if (!ops->set_rate)
		return -ENOSYS;

	return ops->set_rate(clk, rate);
}

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);

	if (!ops->set_parent)
		return -ENOSYS;

	return ops->set_parent(clk, parent);
}

int clk_enable(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->enable)
		return -ENOSYS;

	return ops->enable(clk);
}

int clk_disable(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->disable)
		return -ENOSYS;

	return ops->disable(clk);
}

UCLASS_DRIVER(clk) = {
	.id		= UCLASS_CLK,
	.name		= "clk",
};
Commit	Line	Data
f26c8a8e SG	1	/*
	2	* Copyright (C) 2015 Google, Inc
	3	* Written by Simon Glass <sjg@chromium.org>
135aa950	4	* Copyright (c) 2016, NVIDIA CORPORATION.
f4fcba5c	5	* Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
f26c8a8e SG	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <clk.h>
135aa950	12	#include <clk-uclass.h>
f26c8a8e	13	#include <dm.h>
f4fcba5c	14	#include <dm/read.h>
7423daa6	15	#include <dt-structs.h>
f26c8a8e	16	#include <errno.h>
f26c8a8e	17
268453be	18	static inline const struct clk_ops clk_dev_ops(struct udevice dev)
f26c8a8e	19	{
268453be	20	return (const struct clk_ops *)dev->driver->ops;
f26c8a8e SG	21	}
f26c8a8e SG	22
135aa950	23	#if CONFIG_IS_ENABLED(OF_CONTROL)
7423daa6 SG	24	# if CONFIG_IS_ENABLED(OF_PLATDATA)
7423daa6 SG	25	int clk_get_by_index_platdata(struct udevice *dev, int index,
0d15463c	26	struct phandle_1_arg cells, struct clk clk)
7423daa6 SG	27	{
	28	int ret;
	29
	30	if (index != 0)
	31	return -ENOSYS;
	32	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
	33	if (ret)
	34	return ret;
bc79617f	35	clk->id = cells[0].arg[0];
7423daa6 SG	36
	37	return 0;
	38	}
	39	# else
135aa950	40	static int clk_of_xlate_default(struct clk *clk,
a4e0ef50	41	struct ofnode_phandle_args *args)
f26c8a8e	42	{
135aa950	43	debug("%s(clk=%p)\n", __func__, clk);
f26c8a8e	44
135aa950 SW	45	if (args->args_count > 1) {
	46	debug("Invaild args_count: %d\n", args->args_count);
	47	return -EINVAL;
	48	}
f26c8a8e	49
135aa950 SW	50	if (args->args_count)
	51	clk->id = args->args[0];
	52	else
	53	clk->id = 0;
f26c8a8e	54
135aa950	55	return 0;
f26c8a8e SG	56	}
f26c8a8e SG	57
95f9a7e5 PT	58	static int clk_get_by_indexed_prop(struct udevice dev, const char prop_name,
95f9a7e5 PT	59	int index, struct clk *clk)
e70cc438	60	{
e70cc438	61	int ret;
aa9bb094	62	struct ofnode_phandle_args args;
135aa950	63	struct udevice *dev_clk;
268453be	64	const struct clk_ops *ops;
135aa950 SW	65
135aa950 SW	66	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
e70cc438	67
135aa950	68	assert(clk);
82a8a669 PC	69	clk->dev = NULL;
82a8a669 PC	70
95f9a7e5	71	ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
268453be	72	index, &args);
e70cc438 SG	73	if (ret) {
	74	debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
	75	__func__, ret);
	76	return ret;
	77	}
	78
aa9bb094	79	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
e70cc438 SG	80	if (ret) {
	81	debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
	82	__func__, ret);
	83	return ret;
	84	}
3f56b132 WY	85
	86	clk->dev = dev_clk;
	87
135aa950 SW	88	ops = clk_dev_ops(dev_clk);
	89
	90	if (ops->of_xlate)
aa9bb094	91	ret = ops->of_xlate(clk, &args);
135aa950	92	else
aa9bb094	93	ret = clk_of_xlate_default(clk, &args);
135aa950 SW	94	if (ret) {
	95	debug("of_xlate() failed: %d\n", ret);
	96	return ret;
	97	}
	98
	99	return clk_request(dev_clk, clk);
	100	}
95f9a7e5 PT	101
	102	int clk_get_by_index(struct udevice dev, int index, struct clk clk)
	103	{
	104	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
	105	}
f4fcba5c PT	106
	107	static int clk_set_default_parents(struct udevice *dev)
	108	{
	109	struct clk clk, parent_clk;
	110	int index;
	111	int num_parents;
	112	int ret;
	113
	114	num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
	115	"#clock-cells");
	116	if (num_parents < 0) {
	117	debug("%s: could not read assigned-clock-parents for %p\n",
	118	__func__, dev);
	119	return 0;
	120	}
	121
	122	for (index = 0; index < num_parents; index++) {
	123	ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
	124	index, &parent_clk);
	125	if (ret) {
	126	debug("%s: could not get parent clock %d for %s\n",
	127	__func__, index, dev_read_name(dev));
	128	return ret;
	129	}
	130
	131	ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
	132	index, &clk);
	133	if (ret) {
	134	debug("%s: could not get assigned clock %d for %s\n",
	135	__func__, index, dev_read_name(dev));
	136	return ret;
	137	}
	138
	139	ret = clk_set_parent(&clk, &parent_clk);
	140
	141	/*
	142	* Not all drivers may support clock-reparenting (as of now).
	143	* Ignore errors due to this.
	144	*/
	145	if (ret == -ENOSYS)
	146	continue;
	147
	148	if (ret) {
	149	debug("%s: failed to reparent clock %d for %s\n",
	150	__func__, index, dev_read_name(dev));
	151	return ret;
	152	}
	153	}
	154
	155	return 0;
	156	}
	157
	158	static int clk_set_default_rates(struct udevice *dev)
	159	{
	160	struct clk clk;
	161	int index;
	162	int num_rates;
	163	int size;
	164	int ret = 0;
	165	u32 *rates = NULL;
	166
	167	size = dev_read_size(dev, "assigned-clock-rates");
	168	if (size < 0)
	169	return 0;
170
171	num_rates = size / sizeof(u32);
172	rates = calloc(num_rates, sizeof(u32));
173	if (!rates)
174	return -ENOMEM;
175
176	ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
177	if (ret)
178	goto fail;
179
180	for (index = 0; index < num_rates; index++) {
181	ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
182	index, &clk);
183	if (ret) {
184	debug("%s: could not get assigned clock %d for %s\n",
185	__func__, index, dev_read_name(dev));
186	continue;
187	}
188
189	ret = clk_set_rate(&clk, rates[index]);
190	if (ret < 0) {
191	debug("%s: failed to set rate on clock %d for %s\n",
192	__func__, index, dev_read_name(dev));
193	break;
194	}
195	}
196
197	fail:
198	free(rates);
199	return ret;
200	}
201
202	int clk_set_defaults(struct udevice *dev)
203	{
204	int ret;
205
206	/* If this is running pre-reloc state, don't take any action. */
207	if (!(gd->flags & GD_FLG_RELOC))
208	return 0;
209
210	debug("%s(%s)\n", __func__, dev_read_name(dev));
211
212	ret = clk_set_default_parents(dev);
213	if (ret)
214	return ret;
215
216	ret = clk_set_default_rates(dev);
217	if (ret < 0)
218	return ret;
219
220	return 0;
221	}
9e0758b7	222	# endif /* OF_PLATDATA */
135aa950 SW	223
	224	int clk_get_by_name(struct udevice dev, const char name, struct clk *clk)
	225	{
	226	int index;
	227
	228	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
82a8a669	229	clk->dev = NULL;
135aa950	230
aa9bb094	231	index = dev_read_stringlist_search(dev, "clock-names", name);
135aa950	232	if (index < 0) {
b02e4044	233	debug("fdt_stringlist_search() failed: %d\n", index);
135aa950 SW	234	return index;
	235	}
	236
	237	return clk_get_by_index(dev, index, clk);
e70cc438	238	}
b108d8a0 PC	239
	240	int clk_release_all(struct clk *clk, int count)
	241	{
	242	int i, ret;
	243
	244	for (i = 0; i < count; i++) {
	245	debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
	246
	247	/* check if clock has been previously requested */
	248	if (!clk[i].dev)
	249	continue;
	250
	251	ret = clk_disable(&clk[i]);
	252	if (ret && ret != -ENOSYS)
	253	return ret;
	254
	255	ret = clk_free(&clk[i]);
	256	if (ret && ret != -ENOSYS)
	257	return ret;
	258	}
	259
	260	return 0;
	261	}
	262
7423daa6	263	#endif /* OF_CONTROL */
135aa950 SW	264
	265	int clk_request(struct udevice dev, struct clk clk)
	266	{
268453be	267	const struct clk_ops *ops = clk_dev_ops(dev);
135aa950 SW	268
	269	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
	270
	271	clk->dev = dev;
	272
	273	if (!ops->request)
	274	return 0;
	275
	276	return ops->request(clk);
	277	}
	278
	279	int clk_free(struct clk *clk)
	280	{
268453be	281	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	282
	283	debug("%s(clk=%p)\n", __func__, clk);
	284
	285	if (!ops->free)
	286	return 0;
	287
	288	return ops->free(clk);
	289	}
	290
	291	ulong clk_get_rate(struct clk *clk)
	292	{
268453be	293	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	294
	295	debug("%s(clk=%p)\n", __func__, clk);
	296
	297	if (!ops->get_rate)
	298	return -ENOSYS;
	299
	300	return ops->get_rate(clk);
	301	}
	302
	303	ulong clk_set_rate(struct clk *clk, ulong rate)
	304	{
268453be	305	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	306
	307	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
	308
	309	if (!ops->set_rate)
	310	return -ENOSYS;
	311
	312	return ops->set_rate(clk, rate);
	313	}
	314
f7d1046d PT	315	int clk_set_parent(struct clk clk, struct clk parent)
	316	{
	317	const struct clk_ops *ops = clk_dev_ops(clk->dev);
	318
	319	debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
	320
	321	if (!ops->set_parent)
	322	return -ENOSYS;
	323
	324	return ops->set_parent(clk, parent);
	325	}
	326
135aa950 SW	327	int clk_enable(struct clk *clk)
135aa950 SW	328	{
268453be	329	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	330
	331	debug("%s(clk=%p)\n", __func__, clk);
	332
	333	if (!ops->enable)
	334	return -ENOSYS;
	335
	336	return ops->enable(clk);
	337	}
	338
	339	int clk_disable(struct clk *clk)
	340	{
268453be	341	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	342
	343	debug("%s(clk=%p)\n", __func__, clk);
	344
	345	if (!ops->disable)
	346	return -ENOSYS;
	347
	348	return ops->disable(clk);
	349	}
e70cc438	350
f26c8a8e SG	351	UCLASS_DRIVER(clk) = {
	352	.id = UCLASS_CLK,
	353	.name = "clk",
	354	};