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Commit | Line | Data |
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e66c49fa | 1 | /* |
712f99a5 | 2 | * (C) Copyright 2017 |
e66c49fa VM |
3 | * Vikas Manocha, <vikas.manocha@st.com> |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
e66c49fa | 7 | #include <common.h> |
712f99a5 VM |
8 | #include <clk-uclass.h> |
9 | #include <dm.h> | |
e66c49fa VM |
10 | #include <asm/io.h> |
11 | #include <asm/arch/rcc.h> | |
12 | #include <asm/arch/stm32.h> | |
13 | #include <asm/arch/stm32_periph.h> | |
14 | ||
288f17e6 PC |
15 | #include <dt-bindings/mfd/stm32f7-rcc.h> |
16 | ||
bad5188b MK |
17 | #define RCC_CR_HSION BIT(0) |
18 | #define RCC_CR_HSEON BIT(16) | |
19 | #define RCC_CR_HSERDY BIT(17) | |
20 | #define RCC_CR_HSEBYP BIT(18) | |
21 | #define RCC_CR_CSSON BIT(19) | |
22 | #define RCC_CR_PLLON BIT(24) | |
23 | #define RCC_CR_PLLRDY BIT(25) | |
ba0a3c16 | 24 | |
bad5188b MK |
25 | #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) |
26 | #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) | |
27 | #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) | |
28 | #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) | |
29 | #define RCC_PLLCFGR_PLLSRC BIT(22) | |
30 | #define RCC_PLLCFGR_PLLM_SHIFT 0 | |
31 | #define RCC_PLLCFGR_PLLN_SHIFT 6 | |
32 | #define RCC_PLLCFGR_PLLP_SHIFT 16 | |
33 | #define RCC_PLLCFGR_PLLQ_SHIFT 24 | |
ba0a3c16 | 34 | |
bad5188b MK |
35 | #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) |
36 | #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) | |
37 | #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) | |
38 | #define RCC_CFGR_SW0 BIT(0) | |
39 | #define RCC_CFGR_SW1 BIT(1) | |
40 | #define RCC_CFGR_SW_MASK GENMASK(1, 0) | |
41 | #define RCC_CFGR_SW_HSI 0 | |
42 | #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 | |
43 | #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 | |
44 | #define RCC_CFGR_SWS0 BIT(2) | |
45 | #define RCC_CFGR_SWS1 BIT(3) | |
46 | #define RCC_CFGR_SWS_MASK GENMASK(3, 2) | |
47 | #define RCC_CFGR_SWS_HSI 0 | |
48 | #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 | |
49 | #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 | |
50 | #define RCC_CFGR_HPRE_SHIFT 4 | |
51 | #define RCC_CFGR_PPRE1_SHIFT 10 | |
52 | #define RCC_CFGR_PPRE2_SHIFT 13 | |
ba0a3c16 TN |
53 | |
54 | /* | |
55 | * Offsets of some PWR registers | |
56 | */ | |
bad5188b MK |
57 | #define PWR_CR1_ODEN BIT(16) |
58 | #define PWR_CR1_ODSWEN BIT(17) | |
59 | #define PWR_CSR1_ODRDY BIT(16) | |
60 | #define PWR_CSR1_ODSWRDY BIT(17) | |
ba0a3c16 TN |
61 | |
62 | struct pll_psc { | |
63 | u8 pll_m; | |
64 | u16 pll_n; | |
65 | u8 pll_p; | |
66 | u8 pll_q; | |
67 | u8 ahb_psc; | |
68 | u8 apb1_psc; | |
69 | u8 apb2_psc; | |
70 | }; | |
71 | ||
bad5188b MK |
72 | #define AHB_PSC_1 0 |
73 | #define AHB_PSC_2 0x8 | |
74 | #define AHB_PSC_4 0x9 | |
75 | #define AHB_PSC_8 0xA | |
76 | #define AHB_PSC_16 0xB | |
77 | #define AHB_PSC_64 0xC | |
78 | #define AHB_PSC_128 0xD | |
79 | #define AHB_PSC_256 0xE | |
80 | #define AHB_PSC_512 0xF | |
ba0a3c16 | 81 | |
bad5188b MK |
82 | #define APB_PSC_1 0 |
83 | #define APB_PSC_2 0x4 | |
84 | #define APB_PSC_4 0x5 | |
85 | #define APB_PSC_8 0x6 | |
86 | #define APB_PSC_16 0x7 | |
ba0a3c16 | 87 | |
199a2178 PC |
88 | struct stm32_clk { |
89 | struct stm32_rcc_regs *base; | |
90 | }; | |
91 | ||
ba0a3c16 TN |
92 | #if !defined(CONFIG_STM32_HSE_HZ) |
93 | #error "CONFIG_STM32_HSE_HZ not defined!" | |
94 | #else | |
95 | #if (CONFIG_STM32_HSE_HZ == 25000000) | |
96 | #if (CONFIG_SYS_CLK_FREQ == 200000000) | |
97 | /* 200 MHz */ | |
98 | struct pll_psc sys_pll_psc = { | |
99 | .pll_m = 25, | |
100 | .pll_n = 400, | |
101 | .pll_p = 2, | |
102 | .pll_q = 8, | |
103 | .ahb_psc = AHB_PSC_1, | |
104 | .apb1_psc = APB_PSC_4, | |
105 | .apb2_psc = APB_PSC_2 | |
106 | }; | |
107 | #endif | |
108 | #else | |
109 | #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" | |
110 | #endif | |
111 | #endif | |
112 | ||
199a2178 | 113 | static int configure_clocks(struct udevice *dev) |
ba0a3c16 | 114 | { |
199a2178 PC |
115 | struct stm32_clk *priv = dev_get_priv(dev); |
116 | struct stm32_rcc_regs *regs = priv->base; | |
117 | ||
ba0a3c16 | 118 | /* Reset RCC configuration */ |
199a2178 PC |
119 | setbits_le32(®s->cr, RCC_CR_HSION); |
120 | writel(0, ®s->cfgr); /* Reset CFGR */ | |
121 | clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON | |
ba0a3c16 | 122 | | RCC_CR_PLLON)); |
199a2178 PC |
123 | writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ |
124 | clrbits_le32(®s->cr, RCC_CR_HSEBYP); | |
125 | writel(0, ®s->cir); /* Disable all interrupts */ | |
ba0a3c16 TN |
126 | |
127 | /* Configure for HSE+PLL operation */ | |
199a2178 PC |
128 | setbits_le32(®s->cr, RCC_CR_HSEON); |
129 | while (!(readl(®s->cr) & RCC_CR_HSERDY)) | |
ba0a3c16 TN |
130 | ; |
131 | ||
199a2178 | 132 | setbits_le32(®s->cfgr, (( |
ba0a3c16 TN |
133 | sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) |
134 | | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) | |
135 | | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); | |
136 | ||
137 | /* Configure the main PLL */ | |
138 | uint32_t pllcfgr = 0; | |
139 | pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ | |
140 | pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; | |
141 | pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; | |
142 | pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; | |
143 | pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; | |
199a2178 | 144 | writel(pllcfgr, ®s->pllcfgr); |
ba0a3c16 TN |
145 | |
146 | /* Enable the main PLL */ | |
199a2178 PC |
147 | setbits_le32(®s->cr, RCC_CR_PLLON); |
148 | while (!(readl(®s->cr) & RCC_CR_PLLRDY)) | |
ba0a3c16 TN |
149 | ; |
150 | ||
151 | /* Enable high performance mode, System frequency up to 200 MHz */ | |
199a2178 | 152 | setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); |
ba0a3c16 TN |
153 | setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); |
154 | /* Infinite wait! */ | |
155 | while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY)) | |
156 | ; | |
157 | /* Enable the Over-drive switch */ | |
158 | setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN); | |
159 | /* Infinite wait! */ | |
160 | while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY)) | |
161 | ; | |
162 | ||
163 | stm32_flash_latency_cfg(5); | |
199a2178 PC |
164 | clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); |
165 | setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); | |
ba0a3c16 | 166 | |
199a2178 | 167 | while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != |
ba0a3c16 TN |
168 | RCC_CFGR_SWS_PLL) |
169 | ; | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
288f17e6 PC |
174 | static unsigned long stm32_clk_get_rate(struct clk *clk) |
175 | { | |
176 | struct stm32_clk *priv = dev_get_priv(clk->dev); | |
177 | struct stm32_rcc_regs *regs = priv->base; | |
178 | u32 sysclk = 0; | |
179 | u32 shift = 0; | |
180 | /* Prescaler table lookups for clock computation */ | |
181 | u8 ahb_psc_table[16] = { | |
182 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 | |
183 | }; | |
184 | u8 apb_psc_table[8] = { | |
185 | 0, 0, 0, 0, 1, 2, 3, 4 | |
186 | }; | |
187 | ||
188 | if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == | |
189 | RCC_CFGR_SWS_PLL) { | |
190 | u16 pllm, plln, pllp; | |
191 | pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); | |
192 | plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) | |
193 | >> RCC_PLLCFGR_PLLN_SHIFT); | |
194 | pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) | |
195 | >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); | |
196 | sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; | |
197 | } else { | |
198 | return -EINVAL; | |
199 | } | |
200 | ||
201 | switch (clk->id) { | |
202 | /* | |
203 | * AHB CLOCK: 3 x 32 bits consecutive registers are used : | |
204 | * AHB1, AHB2 and AHB3 | |
205 | */ | |
206 | case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): | |
207 | shift = ahb_psc_table[( | |
208 | (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) | |
209 | >> RCC_CFGR_HPRE_SHIFT)]; | |
210 | return sysclk >>= shift; | |
211 | break; | |
212 | /* APB1 CLOCK */ | |
213 | case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): | |
214 | shift = apb_psc_table[( | |
215 | (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) | |
216 | >> RCC_CFGR_PPRE1_SHIFT)]; | |
217 | return sysclk >>= shift; | |
218 | break; | |
219 | /* APB2 CLOCK */ | |
220 | case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): | |
221 | shift = apb_psc_table[( | |
222 | (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) | |
223 | >> RCC_CFGR_PPRE2_SHIFT)]; | |
224 | return sysclk >>= shift; | |
225 | break; | |
226 | default: | |
9b643e31 | 227 | pr_err("clock index %ld out of range\n", clk->id); |
288f17e6 PC |
228 | return -EINVAL; |
229 | break; | |
230 | } | |
231 | } | |
232 | ||
712f99a5 VM |
233 | static int stm32_clk_enable(struct clk *clk) |
234 | { | |
199a2178 PC |
235 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
236 | struct stm32_rcc_regs *regs = priv->base; | |
712f99a5 VM |
237 | u32 offset = clk->id / 32; |
238 | u32 bit_index = clk->id % 32; | |
239 | ||
240 | debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", | |
241 | __func__, clk->id, offset, bit_index); | |
199a2178 | 242 | setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); |
712f99a5 VM |
243 | |
244 | return 0; | |
245 | } | |
ba0a3c16 | 246 | |
e66c49fa VM |
247 | void clock_setup(int peripheral) |
248 | { | |
249 | switch (peripheral) { | |
081de09d MK |
250 | case SYSCFG_CLOCK_CFG: |
251 | setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); | |
252 | break; | |
253 | case TIMER2_CLOCK_CFG: | |
254 | setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); | |
255 | break; | |
b20b70fc MK |
256 | case STMMAC_CLOCK_CFG: |
257 | setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); | |
258 | setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); | |
259 | setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); | |
260 | break; | |
e66c49fa VM |
261 | default: |
262 | break; | |
263 | } | |
264 | } | |
712f99a5 VM |
265 | |
266 | static int stm32_clk_probe(struct udevice *dev) | |
267 | { | |
268 | debug("%s: stm32_clk_probe\n", __func__); | |
199a2178 PC |
269 | |
270 | struct stm32_clk *priv = dev_get_priv(dev); | |
271 | fdt_addr_t addr; | |
272 | ||
273 | addr = devfdt_get_addr(dev); | |
274 | if (addr == FDT_ADDR_T_NONE) | |
275 | return -EINVAL; | |
276 | ||
277 | priv->base = (struct stm32_rcc_regs *)addr; | |
278 | ||
279 | configure_clocks(dev); | |
712f99a5 VM |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
a4e0ef50 | 284 | static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) |
712f99a5 VM |
285 | { |
286 | debug("%s(clk=%p)\n", __func__, clk); | |
287 | ||
288 | if (args->args_count != 2) { | |
289 | debug("Invaild args_count: %d\n", args->args_count); | |
290 | return -EINVAL; | |
291 | } | |
292 | ||
293 | if (args->args_count) | |
294 | clk->id = args->args[1]; | |
295 | else | |
296 | clk->id = 0; | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | static struct clk_ops stm32_clk_ops = { | |
302 | .of_xlate = stm32_clk_of_xlate, | |
303 | .enable = stm32_clk_enable, | |
288f17e6 | 304 | .get_rate = stm32_clk_get_rate, |
712f99a5 VM |
305 | }; |
306 | ||
307 | static const struct udevice_id stm32_clk_ids[] = { | |
308 | { .compatible = "st,stm32f42xx-rcc"}, | |
309 | {} | |
310 | }; | |
311 | ||
312 | U_BOOT_DRIVER(stm32f7_clk) = { | |
0cc40dfc PC |
313 | .name = "stm32f7_clk", |
314 | .id = UCLASS_CLK, | |
315 | .of_match = stm32_clk_ids, | |
316 | .ops = &stm32_clk_ops, | |
317 | .probe = stm32_clk_probe, | |
318 | .priv_auto_alloc_size = sizeof(struct stm32_clk), | |
319 | .flags = DM_FLAG_PRE_RELOC, | |
712f99a5 | 320 | }; |