projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f77b5a4c MV |
1 | /* |
| 2 | * Renesas R8A7795 CPG MSSR driver | |
| 3 | * | |
| 4 | * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> | |
| 5 | * | |
| 6 | * Based on the following driver from Linux kernel: | |
| 7 | * r8a7796 Clock Pulse Generator / Module Standby and Software Reset | |
| 8 | * | |
| 9 | * Copyright (C) 2016 Glider bvba | |
| 10 | * | |
| 11 | * SPDX-License-Identifier: GPL-2.0+ | |
| 12 | */ | |
| 13 | ||
| 14 | #include <common.h> | |
| 15 | #include <clk-uclass.h> | |
| 16 | #include <dm.h> | |
| 17 | ||
| 18 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> | |
| 19 | ||
| 20 | #include "renesas-cpg-mssr.h" | |
| 21 | ||
| f11c9679 MV |
22 | enum clk_ids { |
| 23 | /* Core Clock Outputs exported to DT */ | |
| 24 | LAST_DT_CORE_CLK = R8A7795_CLK_S0D12, | |
| 25 | ||
| 26 | /* External Input Clocks */ | |
| 27 | CLK_EXTAL, | |
| 28 | CLK_EXTALR, | |
| 29 | ||
| 30 | /* Internal Core Clocks */ | |
| 31 | CLK_MAIN, | |
| 32 | CLK_PLL0, | |
| 33 | CLK_PLL1, | |
| 34 | CLK_PLL2, | |
| 35 | CLK_PLL3, | |
| 36 | CLK_PLL4, | |
| 37 | CLK_PLL1_DIV2, | |
| 38 | CLK_PLL1_DIV4, | |
| 39 | CLK_S0, | |
| 40 | CLK_S1, | |
| 41 | CLK_S2, | |
| 42 | CLK_S3, | |
| 43 | CLK_SDSRC, | |
| 44 | CLK_RPCSRC, | |
| 45 | CLK_SSPSRC, | |
| 46 | CLK_RINT, | |
| 47 | ||
| 48 | /* Module Clocks */ | |
| 49 | MOD_CLK_BASE | |
| 50 | }; | |
| 51 | ||
| f77b5a4c MV |
52 | static const struct cpg_core_clk r8a7795_core_clks[] = { |
| 53 | /* External Clock Inputs */ | |
| 54 | DEF_INPUT("extal", CLK_EXTAL), | |
| 55 | DEF_INPUT("extalr", CLK_EXTALR), | |
| 56 | ||
| 57 | /* Internal Core Clocks */ | |
| 58 | DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), | |
| 59 | DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), | |
| 60 | DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), | |
| 61 | DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), | |
| 62 | DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), | |
| 63 | DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), | |
| 64 | ||
| 65 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), | |
| 66 | DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), | |
| 67 | DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), | |
| 68 | DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), | |
| 69 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), | |
| 70 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), | |
| 71 | DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), | |
| 72 | DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), | |
| 73 | ||
| 74 | /* Core Clock Outputs */ | |
| 75 | DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), | |
| 76 | DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), | |
| 77 | DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), | |
| 78 | DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), | |
| 79 | DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), | |
| 80 | DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), | |
| 81 | DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), | |
| 82 | DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), | |
| 83 | DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), | |
| 84 | DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), | |
| 85 | DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), | |
| 86 | DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), | |
| 87 | DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), | |
| 88 | DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), | |
| 89 | DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), | |
| 90 | DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), | |
| 91 | DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), | |
| 92 | DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), | |
| 93 | DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), | |
| 94 | DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), | |
| 95 | ||
| 96 | DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), | |
| 97 | DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), | |
| 98 | DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), | |
| 99 | DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), | |
| 100 | ||
| 101 | DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), | |
| 102 | ||
| 103 | DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), | |
| 104 | DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), | |
| 105 | ||
| 106 | /* NOTE: HDMI, CSI, CAN etc. clock are missing */ | |
| 107 | ||
| 108 | DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), | |
| 109 | }; | |
| 110 | ||
| 111 | static const struct mssr_mod_clk r8a7795_mod_clks[] = { | |
| 112 | DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 113 | DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), | |
| 114 | DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), | |
| 115 | DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), | |
| 116 | DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), | |
| 117 | DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), | |
| 118 | DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), | |
| 119 | DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), | |
| 120 | DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), | |
| 121 | DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), | |
| 122 | DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), | |
| 123 | DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), | |
| 124 | DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), | |
| 125 | DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), | |
| 126 | DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), | |
| 127 | DEF_MOD("cmt3", 300, R8A7795_CLK_R), | |
| 128 | DEF_MOD("cmt2", 301, R8A7795_CLK_R), | |
| 129 | DEF_MOD("cmt1", 302, R8A7795_CLK_R), | |
| 130 | DEF_MOD("cmt0", 303, R8A7795_CLK_R), | |
| 131 | DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), | |
| 132 | DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), | |
| 133 | DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), | |
| 134 | DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), | |
| 135 | DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), | |
| 136 | DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), | |
| 137 | DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), | |
| 138 | DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), | |
| 139 | DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ | |
| 140 | DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), | |
| 141 | DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), | |
| 142 | DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), | |
| 143 | DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), | |
| 144 | DEF_MOD("rwdt", 402, R8A7795_CLK_R), | |
| 145 | DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), | |
| 146 | DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), | |
| 147 | DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), | |
| 148 | DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), | |
| 149 | DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), | |
| 150 | DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), | |
| 151 | DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), | |
| 152 | DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), | |
| 153 | DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), | |
| 154 | DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), | |
| 155 | DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), | |
| 156 | DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), | |
| 157 | DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), | |
| 158 | DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), | |
| 159 | DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), | |
| 160 | DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), | |
| 161 | DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), | |
| 162 | DEF_MOD("thermal", 522, R8A7795_CLK_CP), | |
| 163 | DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), | |
| 164 | DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 165 | DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), | |
| 166 | DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), | |
| 167 | DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), | |
| 168 | DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), | |
| 169 | DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), | |
| 170 | DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 171 | DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), | |
| 172 | DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), | |
| 173 | DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 174 | DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), | |
| 175 | DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), | |
| 176 | DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 177 | DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 178 | DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), | |
| 179 | DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 180 | DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), | |
| 181 | DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), | |
| 182 | DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), | |
| 183 | DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), | |
| 184 | DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), | |
| 185 | DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ | |
| 186 | DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), | |
| 187 | DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), | |
| 188 | DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), | |
| 189 | DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), | |
| 190 | DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), | |
| 191 | DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), | |
| 192 | DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), | |
| 193 | DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), | |
| 194 | DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ | |
| 195 | DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), | |
| 196 | DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), | |
| 197 | DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), | |
| 198 | DEF_MOD("du3", 721, R8A7795_CLK_S2D1), | |
| 199 | DEF_MOD("du2", 722, R8A7795_CLK_S2D1), | |
| 200 | DEF_MOD("du1", 723, R8A7795_CLK_S2D1), | |
| 201 | DEF_MOD("du0", 724, R8A7795_CLK_S2D1), | |
| 202 | DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), | |
| 203 | DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), | |
| 204 | DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), | |
| 205 | DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), | |
| 206 | DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), | |
| 207 | DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), | |
| 208 | DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), | |
| 209 | DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), | |
| 210 | DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), | |
| 211 | DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), | |
| 212 | DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), | |
| 213 | DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), | |
| 214 | DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), | |
| 215 | DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), | |
| 216 | DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), | |
| 217 | DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), | |
| 218 | DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), | |
| 219 | DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), | |
| 220 | DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), | |
| 221 | DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), | |
| 222 | DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), | |
| 223 | DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), | |
| 224 | DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), | |
| 225 | DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), | |
| 226 | DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), | |
| 227 | DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), | |
| 228 | DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), | |
| 229 | DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), | |
| 230 | DEF_MOD("rpc", 917, R8A7795_CLK_RPC), | |
| 231 | DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), | |
| 232 | DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), | |
| 233 | DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), | |
| 234 | DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), | |
| 235 | DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), | |
| 236 | DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), | |
| 237 | DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), | |
| 238 | DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), | |
| 239 | DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), | |
| 240 | DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), | |
| 241 | DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), | |
| 242 | DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), | |
| 243 | DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), | |
| 244 | DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), | |
| 245 | DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), | |
| 246 | DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), | |
| 247 | DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), | |
| 248 | DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), | |
| 249 | DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), | |
| 250 | DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), | |
| 251 | DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), | |
| 252 | DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), | |
| 253 | DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), | |
| 254 | DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), | |
| 255 | DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), | |
| 256 | DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), | |
| 257 | DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), | |
| 258 | DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), | |
| 259 | DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), | |
| 260 | DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), | |
| 261 | DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), | |
| 262 | DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), | |
| 263 | DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), | |
| 264 | DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), | |
| 265 | }; | |
| 266 | ||
| 7c885563 MV |
267 | /* |
| 268 | * CPG Clock Data | |
| 269 | */ | |
| 270 | ||
| 271 | /* | |
| 272 | * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 | |
| 273 | * 14 13 19 17 (MHz) | |
| 274 | *------------------------------------------------------------------- | |
| 275 | * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 | |
| 276 | * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 | |
| 277 | * 0 0 1 0 Prohibited setting | |
| 278 | * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 | |
| 279 | * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 | |
| 280 | * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 | |
| 281 | * 0 1 1 0 Prohibited setting | |
| 282 | * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 | |
| 283 | * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 | |
| 284 | * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 | |
| 285 | * 1 0 1 0 Prohibited setting | |
| 286 | * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 | |
| 287 | * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 | |
| 288 | * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 | |
| 289 | * 1 1 1 0 Prohibited setting | |
| 290 | * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 | |
| 291 | */ | |
| 292 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ | |
| 293 | (((md) & BIT(13)) >> 11) | \ | |
| 294 | (((md) & BIT(19)) >> 18) | \ | |
| 295 | (((md) & BIT(17)) >> 17)) | |
| 296 | ||
| 297 | static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { | |
| 298 | /* EXTAL div PLL1 mult/div PLL3 mult/div */ | |
| 299 | { 1, 192, 1, 192, 1, }, | |
| 300 | { 1, 192, 1, 128, 1, }, | |
| 301 | { 0, /* Prohibited setting */ }, | |
| 302 | { 1, 192, 1, 192, 1, }, | |
| 303 | { 1, 160, 1, 160, 1, }, | |
| 304 | { 1, 160, 1, 106, 1, }, | |
| 305 | { 0, /* Prohibited setting */ }, | |
| 306 | { 1, 160, 1, 160, 1, }, | |
| 307 | { 1, 128, 1, 128, 1, }, | |
| 308 | { 1, 128, 1, 84, 1, }, | |
| 309 | { 0, /* Prohibited setting */ }, | |
| 310 | { 1, 128, 1, 128, 1, }, | |
| 311 | { 2, 192, 1, 192, 1, }, | |
| 312 | { 2, 192, 1, 128, 1, }, | |
| 313 | { 0, /* Prohibited setting */ }, | |
| 314 | { 2, 192, 1, 192, 1, }, | |
| 315 | }; | |
| 316 | ||
| f77b5a4c MV |
317 | static const struct mstp_stop_table r8a7795_mstp_table[] = { |
| 318 | { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 }, | |
| 319 | { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 }, | |
| 320 | { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 }, | |
| 321 | { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 }, | |
| 322 | { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 }, | |
| 323 | { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 }, | |
| 324 | }; | |
| 325 | ||
| 7c885563 MV |
326 | static const void *r8a7795_get_pll_config(const u32 cpg_mode) |
| 327 | { | |
| 328 | return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; | |
| 329 | } | |
| 330 | ||
| f77b5a4c MV |
331 | static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { |
| 332 | .core_clk = r8a7795_core_clks, | |
| 333 | .core_clk_size = ARRAY_SIZE(r8a7795_core_clks), | |
| 334 | .mod_clk = r8a7795_mod_clks, | |
| 335 | .mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks), | |
| 336 | .mstp_table = r8a7795_mstp_table, | |
| 337 | .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table), | |
| 338 | .reset_node = "renesas,r8a7795-rst", | |
| 339 | .extalr_node = "extalr", | |
| f11c9679 MV |
340 | .mod_clk_base = MOD_CLK_BASE, |
| 341 | .clk_extal_id = CLK_EXTAL, | |
| 342 | .clk_extalr_id = CLK_EXTALR, | |
| 7c885563 | 343 | .get_pll_config = r8a7795_get_pll_config, |
| f77b5a4c MV |
344 | }; |
| 345 | ||
| 346 | static const struct udevice_id r8a7795_clk_ids[] = { | |
| 347 | { | |
| 348 | .compatible = "renesas,r8a7795-cpg-mssr", | |
| 349 | .data = (ulong)&r8a7795_cpg_mssr_info | |
| 350 | }, | |
| 351 | { } | |
| 352 | }; | |
| 353 | ||
| 354 | U_BOOT_DRIVER(clk_r8a7795) = { | |
| 355 | .name = "clk_r8a7795", | |
| 356 | .id = UCLASS_CLK, | |
| 357 | .of_match = r8a7795_clk_ids, | |
| 358 | .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), | |
| 359 | .ops = &gen3_clk_ops, | |
| 360 | .probe = gen3_clk_probe, | |
| 361 | .remove = gen3_clk_remove, | |
| 362 | }; |