[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3368.c

/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 * Author: Andy Yan <andy.yan@rock-chips.com>
 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <mapmem.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3368.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>

DECLARE_GLOBAL_DATA_PTR;

#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_plat {
	struct dtd_rockchip_rk3368_cru dtd;
};
#endif

struct pll_div {
	u32 nr;
	u32 nf;
	u32 no;
};

#define OSC_HZ		(24 * 1000 * 1000)
#define APLL_L_HZ	(800 * 1000 * 1000)
#define APLL_B_HZ	(816 * 1000 * 1000)
#define GPLL_HZ		(576 * 1000 * 1000)
#define CPLL_HZ		(400 * 1000 * 1000)

#define RATE_TO_DIV(input_rate, output_rate) \
		((input_rate) / (output_rate) - 1);

#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _nr, _no) { \
	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
		       "divisors on line " __stringify(__LINE__));

#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
#if !defined(CONFIG_TPL_BUILD)
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
#endif
#endif

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
				   enum rk3368_pll_id pll_id)
{
	uint32_t nr, no, nf;
	uint32_t con;
	struct rk3368_pll *pll = &cru->pll[pll_id];

	con = readl(&pll->con3);

	switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
	case PLL_MODE_SLOW:
		return OSC_HZ;
	case PLL_MODE_NORMAL:
		con = readl(&pll->con0);
		no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
		nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
		con = readl(&pll->con1);
		nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;

		return (24 * nf / (nr * no)) * 1000000;
	case PLL_MODE_DEEP_SLOW:
	default:
		return 32768;
	}
}

#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
			 const struct pll_div *div)
{
	struct rk3368_pll *pll = &cru->pll[pll_id];
	/* All PLLs have same VCO and output frequency range restrictions*/
	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
	uint output_hz = vco_hz / div->no;

	debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
	      pll, div->nf, div->nr, div->no, vco_hz, output_hz);

	/* enter slow mode and reset pll */
	rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
		     PLL_RESET << PLL_RESET_SHIFT);

	rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
		     ((div->nr - 1) << PLL_NR_SHIFT) |
		     ((div->no - 1) << PLL_OD_SHIFT));
	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
	/*
	 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
	 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
	 */
	clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);

	udelay(10);

	/* return from reset */
	rk_clrreg(&pll->con3, PLL_RESET_MASK);

	/* waiting for pll lock */
	while (!(readl(&pll->con1) & PLL_LOCK_STA))
		udelay(1);

	rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
		     PLL_MODE_NORMAL << PLL_MODE_SHIFT);

	return 0;
}
#endif

#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static void rkclk_init(struct rk3368_cru *cru)
{
	u32 apllb, aplll, dpll, cpll, gpll;

	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
#if !defined(CONFIG_TPL_BUILD)
	/*
	 * If we plan to return to the boot ROM, we can't increase the
	 * GPLL rate from the SPL stage.
	 */
	rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
	rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
#endif

	apllb = rkclk_pll_get_rate(cru, APLLB);
	aplll = rkclk_pll_get_rate(cru, APLLL);
	dpll = rkclk_pll_get_rate(cru, DPLL);
	cpll = rkclk_pll_get_rate(cru, CPLL);
	gpll = rkclk_pll_get_rate(cru, GPLL);

	debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
	       __func__, apllb, aplll, dpll, cpll, gpll);
}
#endif

static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
	u32 div, con, con_id, rate;
	u32 pll_rate;

	switch (clk_id) {
	case SCLK_SDMMC:
		con_id = 50;
		break;
	case SCLK_EMMC:
		con_id = 51;
		break;
	case SCLK_SDIO0:
		con_id = 48;
		break;
	default:
		return -EINVAL;
	}

	con = readl(&cru->clksel_con[con_id]);
	switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
	case MMC_PLL_SEL_GPLL:
		pll_rate = rkclk_pll_get_rate(cru, GPLL);
		break;
	case MMC_PLL_SEL_24M:
		pll_rate = OSC_HZ;
		break;
	case MMC_PLL_SEL_CPLL:
	case MMC_PLL_SEL_USBPHY_480M:
	default:
		return -EINVAL;
	}
	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
	rate = DIV_TO_RATE(pll_rate, div);

	return rate >> 1;
}

static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
				ulong clk_id, ulong rate)
{
	u32 div;
	u32 con_id;
	u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);

	div = RATE_TO_DIV(gpll_rate, rate << 1);

	switch (clk_id) {
	case SCLK_SDMMC:
		con_id = 50;
		break;
	case SCLK_EMMC:
		con_id = 51;
		break;
	case SCLK_SDIO0:
		con_id = 48;
		break;
	default:
		return -EINVAL;
	}

	if (div > 0x3f) {
		div = RATE_TO_DIV(OSC_HZ, rate);
		rk_clrsetreg(&cru->clksel_con[con_id],
			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
			     (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
			     (div << MMC_CLK_DIV_SHIFT));
	} else {
		rk_clrsetreg(&cru->clksel_con[con_id],
			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
			     (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
			     div << MMC_CLK_DIV_SHIFT);
	}

	return rk3368_mmc_get_clk(cru, clk_id);
}

static ulong rk3368_clk_get_rate(struct clk *clk)
{
	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate = 0;

	debug("%s id:%ld\n", __func__, clk->id);
	switch (clk->id) {
	case HCLK_SDMMC:
	case HCLK_EMMC:
		rate = rk3368_mmc_get_clk(priv->cru, clk->id);
		break;
	default:
		return -ENOENT;
	}

	return rate;
}

static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
	ulong ret = 0;

	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
	switch (clk->id) {
	case SCLK_SDMMC:
	case SCLK_EMMC:
		ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
		break;
	default:
		return -ENOENT;
	}

	return ret;
}

static struct clk_ops rk3368_clk_ops = {
	.get_rate = rk3368_clk_get_rate,
	.set_rate = rk3368_clk_set_rate,
};

static int rk3368_clk_probe(struct udevice *dev)
{
	struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rk3368_clk_plat *plat = dev_get_platdata(dev);

	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
#endif
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
	rkclk_init(priv->cru);
#endif

	return 0;
}

static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rk3368_clk_priv *priv = dev_get_priv(dev);

	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
#endif

	return 0;
}

static int rk3368_clk_bind(struct udevice *dev)
{
	int ret;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
	if (ret)
		error("bind RK3368 reset driver failed: ret=%d\n", ret);

	return ret;
}

static const struct udevice_id rk3368_clk_ids[] = {
	{ .compatible = "rockchip,rk3368-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rk3368_cru) = {
	.name		= "rockchip_rk3368_cru",
	.id		= UCLASS_CLK,
	.of_match	= rk3368_clk_ids,
	.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	.platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
#endif
	.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
	.ops		= &rk3368_clk_ops,
	.bind		= rk3368_clk_bind,
	.probe		= rk3368_clk_probe,
};
Commit	Line	Data
d1dcf852 AY	1	/*
	2	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
	3	* Author: Andy Yan <andy.yan@rock-chips.com>
ddfe77df	4	* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
d1dcf852 AY	5	* SPDX-License-Identifier: GPL-2.0
	6	*/
	7
	8	#include <common.h>
	9	#include <clk-uclass.h>
	10	#include <dm.h>
bee61801	11	#include <dt-structs.h>
d1dcf852	12	#include <errno.h>
bee61801	13	#include <mapmem.h>
d1dcf852 AY	14	#include <syscon.h>
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/cru_rk3368.h>
	17	#include <asm/arch/hardware.h>
	18	#include <asm/io.h>
	19	#include <dm/lists.h>
	20	#include <dt-bindings/clock/rk3368-cru.h>
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
bee61801 PT	24	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	25	struct rk3368_clk_plat {
	26	struct dtd_rockchip_rk3368_cru dtd;
	27	};
	28	#endif
	29
d1dcf852 AY	30	struct pll_div {
	31	u32 nr;
	32	u32 nf;
	33	u32 no;
	34	};
	35
	36	#define OSC_HZ (24 * 1000 * 1000)
	37	#define APLL_L_HZ (800 * 1000 * 1000)
	38	#define APLL_B_HZ (816 * 1000 * 1000)
	39	#define GPLL_HZ (576 * 1000 * 1000)
	40	#define CPLL_HZ (400 * 1000 * 1000)
	41
	42	#define RATE_TO_DIV(input_rate, output_rate) \
	43	((input_rate) / (output_rate) - 1);
	44
	45	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	46
	47	#define PLL_DIVISORS(hz, _nr, _no) { \
	48	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
	49	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
	50	(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
	51	"divisors on line " __stringify(__LINE__));
	52
4bebf94e	53	#if IS_ENABLED(CONFIG_SPL_BUILD) \|\| IS_ENABLED(CONFIG_TPL_BUILD)
d1dcf852 AY	54	static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
d1dcf852 AY	55	static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
4bebf94e	56	#if !defined(CONFIG_TPL_BUILD)
d1dcf852 AY	57	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
d1dcf852 AY	58	static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
4bebf94e PT	59	#endif
4bebf94e PT	60	#endif
d1dcf852 AY	61
	62	/* Get pll rate by id */
	63	static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
	64	enum rk3368_pll_id pll_id)
	65	{
	66	uint32_t nr, no, nf;
	67	uint32_t con;
	68	struct rk3368_pll *pll = &cru->pll[pll_id];
	69
	70	con = readl(&pll->con3);
	71
	72	switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
	73	case PLL_MODE_SLOW:
	74	return OSC_HZ;
	75	case PLL_MODE_NORMAL:
	76	con = readl(&pll->con0);
	77	no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
	78	nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
	79	con = readl(&pll->con1);
	80	nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
	81
	82	return (24 * nf / (nr * no)) * 1000000;
	83	case PLL_MODE_DEEP_SLOW:
	84	default:
	85	return 32768;
	86	}
	87	}
	88
4bebf94e	89	#if IS_ENABLED(CONFIG_SPL_BUILD) \|\| IS_ENABLED(CONFIG_TPL_BUILD)
d1dcf852	90	static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
ddfe77df	91	const struct pll_div *div)
d1dcf852 AY	92	{
	93	struct rk3368_pll *pll = &cru->pll[pll_id];
	94	/* All PLLs have same VCO and output frequency range restrictions*/
	95	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
	96	uint output_hz = vco_hz / div->no;
	97
	98	debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
	99	pll, div->nf, div->nr, div->no, vco_hz, output_hz);
	100
	101	/* enter slow mode and reset pll */
	102	rk_clrsetreg(&pll->con3, PLL_MODE_MASK \| PLL_RESET_MASK,
	103	PLL_RESET << PLL_RESET_SHIFT);
	104
	105	rk_clrsetreg(&pll->con0, PLL_NR_MASK \| PLL_OD_MASK,
	106	((div->nr - 1) << PLL_NR_SHIFT) \|
	107	((div->no - 1) << PLL_OD_SHIFT));
	108	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
ddfe77df PT	109	/*
	110	* BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
	111	* Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
	112	*/
	113	clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
	114
d1dcf852 AY	115	udelay(10);
	116
	117	/* return from reset */
	118	rk_clrreg(&pll->con3, PLL_RESET_MASK);
	119
	120	/* waiting for pll lock */
	121	while (!(readl(&pll->con1) & PLL_LOCK_STA))
	122	udelay(1);
	123
	124	rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
	125	PLL_MODE_NORMAL << PLL_MODE_SHIFT);
	126
	127	return 0;
	128	}
4bebf94e	129	#endif
d1dcf852	130
4bebf94e	131	#if IS_ENABLED(CONFIG_SPL_BUILD) \|\| IS_ENABLED(CONFIG_TPL_BUILD)
d1dcf852 AY	132	static void rkclk_init(struct rk3368_cru *cru)
	133	{
	134	u32 apllb, aplll, dpll, cpll, gpll;
	135
ddfe77df PT	136	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
ddfe77df PT	137	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
4bebf94e PT	138	#if !defined(CONFIG_TPL_BUILD)
	139	/*
	140	* If we plan to return to the boot ROM, we can't increase the
	141	* GPLL rate from the SPL stage.
	142	*/
ddfe77df PT	143	rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
ddfe77df PT	144	rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
4bebf94e	145	#endif
d1dcf852 AY	146
	147	apllb = rkclk_pll_get_rate(cru, APLLB);
	148	aplll = rkclk_pll_get_rate(cru, APLLL);
	149	dpll = rkclk_pll_get_rate(cru, DPLL);
	150	cpll = rkclk_pll_get_rate(cru, CPLL);
	151	gpll = rkclk_pll_get_rate(cru, GPLL);
	152
	153	debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
	154	__func__, apllb, aplll, dpll, cpll, gpll);
	155	}
4bebf94e	156	#endif
d1dcf852 AY	157
	158	static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
	159	{
	160	u32 div, con, con_id, rate;
	161	u32 pll_rate;
	162
	163	switch (clk_id) {
	164	case SCLK_SDMMC:
	165	con_id = 50;
	166	break;
	167	case SCLK_EMMC:
	168	con_id = 51;
	169	break;
	170	case SCLK_SDIO0:
	171	con_id = 48;
	172	break;
	173	default:
	174	return -EINVAL;
	175	}
	176
	177	con = readl(&cru->clksel_con[con_id]);
	178	switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
	179	case MMC_PLL_SEL_GPLL:
	180	pll_rate = rkclk_pll_get_rate(cru, GPLL);
	181	break;
	182	case MMC_PLL_SEL_24M:
	183	pll_rate = OSC_HZ;
	184	break;
	185	case MMC_PLL_SEL_CPLL:
	186	case MMC_PLL_SEL_USBPHY_480M:
	187	default:
	188	return -EINVAL;
	189	}
	190	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
	191	rate = DIV_TO_RATE(pll_rate, div);
	192
	193	return rate >> 1;
	194	}
	195
	196	static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
	197	ulong clk_id, ulong rate)
	198	{
	199	u32 div;
	200	u32 con_id;
	201	u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
	202
	203	div = RATE_TO_DIV(gpll_rate, rate << 1);
	204
	205	switch (clk_id) {
	206	case SCLK_SDMMC:
	207	con_id = 50;
	208	break;
	209	case SCLK_EMMC:
	210	con_id = 51;
	211	break;
	212	case SCLK_SDIO0:
	213	con_id = 48;
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
	219	if (div > 0x3f) {
	220	div = RATE_TO_DIV(OSC_HZ, rate);
221	rk_clrsetreg(&cru->clksel_con[con_id],
222	MMC_PLL_SEL_MASK \| MMC_CLK_DIV_MASK,
223	(MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) \|
224	(div << MMC_CLK_DIV_SHIFT));
225	} else {
226	rk_clrsetreg(&cru->clksel_con[con_id],
227	MMC_PLL_SEL_MASK \| MMC_CLK_DIV_MASK,
228	(MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) \|
229	div << MMC_CLK_DIV_SHIFT);
230	}
231
232	return rk3368_mmc_get_clk(cru, clk_id);
233	}
234
235	static ulong rk3368_clk_get_rate(struct clk *clk)
236	{
237	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
238	ulong rate = 0;
239
240	debug("%s id:%ld\n", __func__, clk->id);
241	switch (clk->id) {
242	case HCLK_SDMMC:
243	case HCLK_EMMC:
244	rate = rk3368_mmc_get_clk(priv->cru, clk->id);
245	break;
246	default:
247	return -ENOENT;
248	}
249
250	return rate;
251	}
252
253	static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
254	{
255	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
256	ulong ret = 0;
257
258	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
259	switch (clk->id) {
260	case SCLK_SDMMC:
261	case SCLK_EMMC:
262	ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
263	break;
264	default:
265	return -ENOENT;
266	}
267
268	return ret;
269	}
270
271	static struct clk_ops rk3368_clk_ops = {
272	.get_rate = rk3368_clk_get_rate,
273	.set_rate = rk3368_clk_set_rate,
274	};
275
276	static int rk3368_clk_probe(struct udevice *dev)
277	{
4bebf94e	278	struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
bee61801 PT	279	#if CONFIG_IS_ENABLED(OF_PLATDATA)
bee61801 PT	280	struct rk3368_clk_plat *plat = dev_get_platdata(dev);
d1dcf852	281
bee61801 PT	282	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
bee61801 PT	283	#endif
4bebf94e	284	#if IS_ENABLED(CONFIG_SPL_BUILD) \|\| IS_ENABLED(CONFIG_TPL_BUILD)
d1dcf852	285	rkclk_init(priv->cru);
4bebf94e	286	#endif
d1dcf852 AY	287
	288	return 0;
	289	}
	290
	291	static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
	292	{
bee61801	293	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
d1dcf852 AY	294	struct rk3368_clk_priv *priv = dev_get_priv(dev);
	295
	296	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
bee61801	297	#endif
d1dcf852 AY	298
	299	return 0;
	300	}
	301
	302	static int rk3368_clk_bind(struct udevice *dev)
	303	{
	304	int ret;
	305
	306	/* The reset driver does not have a device node, so bind it here */
	307	ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
	308	if (ret)
	309	error("bind RK3368 reset driver failed: ret=%d\n", ret);
	310
	311	return ret;
	312	}
	313
	314	static const struct udevice_id rk3368_clk_ids[] = {
	315	{ .compatible = "rockchip,rk3368-cru" },
	316	{ }
	317	};
	318
	319	U_BOOT_DRIVER(rockchip_rk3368_cru) = {
	320	.name = "rockchip_rk3368_cru",
	321	.id = UCLASS_CLK,
	322	.of_match = rk3368_clk_ids,
cdc6080a	323	.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
bee61801 PT	324	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	325	.platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
	326	#endif
d1dcf852 AY	327	.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
	328	.ops = &rk3368_clk_ops,
	329	.bind = rk3368_clk_bind,
	330	.probe = rk3368_clk_probe,
	331	};